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Full text of "westernDigital :: dataBooks :: 1986 Storage Management Products Handbook"


storage Management 
Products Handbook 
1986 



yi/BSr£Riy DiGiTAL 



1986 

Storage Management 

Products Handbook 



Corita Kent, the cover artist, is an American whose vjorK presents an optimistic, yet philosophical view of the 
world we live in. A former Catholic nun and teacher, Corita now devotes her life and energies to her artwork 
and the "human needs she feels transcend national and religious barriers." A true "citizen of the world," Corita's 
philosophy positions her "on the positive side of hope." Her depiction of the Western Digital mission . . . "IVIaking 
the leading edge work for you" . . . dramatizes the spectrum of solutions we provide our customers. 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western 
Digital Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is 
granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the 
right to change specifications at any time without notice. 

COPYRIGHT © 1984, 1985, 1986 WESTERN DIGITAL CORPORATION 
ALL RIGHTS RESERVED 

This document Is protected by copyright, and contains information proprietary to Western Digital Corporation. Any copying, adaptation, distribution, 
public performance, or public display of this document without the express written consent of Western Digital Corporation is strictly prohibited. 
The receipt or possesion of this document does not convey any rights to reproduce or distribute its contents, or to manufacture, use, or sell anything 
that it may describe, in whole or in part, without the specific written consent of Western Digital Corporation. 



Making the Leading Edge 
Work for You 

This handbook is designed for you, the engineer. It's intended 
to be a usefui tool, enabling you to mal<e a preliminary evalua- 
tion of our products and later, with samples in hand, design 
our products into your own systems. 

The data in these pages have been reviewed by our IVIarketing, 
Engineering, Manufacturing, and Quality groups. Now we 
would like you to review the information we've provided and 
tell us how we can improve it. Please feel free to suggest any 
changes, additions, or clarifications that occur to you. And 
don't hesitate to call to our attention any sins of omission or 
commission we may have made. 

We're eager to help upgrade the quality of information our 
industry provides to its customers. So, please, help us. Direct 
your comments to: 

WESTERN DIGITAL CORPORATION 
Literature Department 
2445 McCabe Way 
Irvine, CA 92714 
(714) 863-0102 



WESTERN DIGITAL 

CORPORATION 

Regional and District Sales Offices 



NORTHEASTERN 

UNITED STATES/EASTERN CANADA 

Corporate Place 1-95 
100 Corporate Place 
Suite 302 

Peabody, MA 01960 
(617) 535-5914 

111 Madison Avenue 
Morrlstown, NJ 07960 
(201) 292-1490 

NORTH CENTRAL 
UNITED STATES 

3600 West 80th Street 
Bloomington, MN 55431 
(612) 835-1003 

1827 Walden Office Sq. 
Suite 308 

Schaumburg, IL 60195 
(312) 397-3111 



SOUTHERN 
UNITED STATES 

3483 Satellite Blvd. 
Suite 221 
Duluth, GA 30136 
(404) 476-7704 

2300 W. Meadowvlew Road 
Suite 209 

Greensboro, NC 27407 
(919) 299-6733 

2611 Westgrove Drive 
Suite 113 

Carrollton, TX 91361 
(214) 248-6785 

AMTEC CENTER 
6405 Congress Avenue 
Suite 110 

Boca Rotan, FL 33431 
(305) 994-6900 



WESTERN 

UNITED STATES/WESTERN CANADA 

2302 Martin Street 
Suite 325 
Irvine, CA 92714 
(714) 851-1221 

5743 Corsa Avenue 
Suite 201 

Westlake Village, CA 91361 
(818) 991-2556 

201 San Antonio Circle 
Building E, Suite 172 
Mountain View, CA 94040 
(415) 941-0216 



INTERNATIONAL OFFICES 

Western Digital (U.K.) Ltd. 
55 East Street 
Epsom, Surrey KT17 IBP 
United Kingdom 
(03727) 42955 

Western Digital Deutschland GmbH 
Prinzregentenstr. 120 
D-8000 Muenchen 80 
Federal Republic of Germany 
(089) 470-7021 



Western Digital Corp. 
12 Rue Auber 
75009 Paris, France 
(01) 266-1020 

Western Digital Japan Ltd. 
8th Floor Dai-44 Kowa BIdg 
1-2-7, Higashlyama, Meguro-Ku 
Tokyo 153 Japan 
(03) 791-2001 



WESTERN DIGITAL 

CORPORATION 

2445 McCabe Way 
Irvine, CA 92714 



(714)863-0102 



Table of Contents 

Functional Index vii 

Numerical Index ix 

System Product Quality/Reliability 1 

Quality/Reliability to Leading Edge Technology 5 

Announcing Burn-In Program Availability/Warranties 11 

Hi-Rel "K" Testing Program 13 

Floppy Disk Controller Devices 1-1 

Floppy Disk Support Devices 2-1 

Winchester Disk Controller Devices 3-1 

Winchester Disk Support Devices 4-1 

SCSI-Bus Interface Controller 5-1 

Winchester Board Products 6-1 

Tape Drive Controller Products 7-1 

Main Memory Devices 8-1 

Integrated Drive Electronics 9-1 

Ordering Information 10-1 

Package Diagrams 11-1 

Terms and Conditions 11-5 



Data Sheets with the Heading below: 

Advance Information: This product has not been produced in volume and is subject to functional and tim- 
ing revisions. Prior to designing with the product, it is necessary to contact Western Digital Corporation 
for current information. 



Functional Index 



STORAGE MANAGEMENT PRODUCTS 
FLOPPY DISK CONTROLLER DEVICES 



WD177X-00 
WD177X-00 
WD1 772-02 
WD1 772-02 
FD179X-02 
FD179X-02 
WD279X-02 
WD279X-02 



Floppy Disk Formatter/Controller 

AppI Notes 

Floppy Disk Formatter/Controller 

Appi Notes 

Floppy Disk Formatter/Controller Family 

AppI Notes 

Floppy Disk Formatter/Controller Family 
AppI Notes 



-1 

-25 

-27 

-51 

-53 

-77 

-91 

-117 



FLOPPY DISK SUPPORT DEVICES 



WD1691 Floppy Support Logic 2-1 

WD16C92 Floppy Disk Read/Write Support 2-9 

WD2143-03 Four Phase Clock Generator 2-13 

WD9216-00/01 Floppy Disk Data Separator 2-17 

WD92C32-00 Floppy Digital Data Separator 2-21 

WINCHESTER DISK CONTROLLER DEVICES 



WD1010-05 
WD1010-05 
WD1050 
WD1050 
WD1100 
WD1 100-01 
WD1 100-03 
WD1 100-04 
WD1 100-05 
WD1 100-06 
WD1 100-07 
WD1 100-09 
WD1 100-12 
WD2010-05 



Winchester Disk Controller 3-1 

AppI Notes 3-25 

SMD Controller/Formatter 3-31 

AppI Notes 3-61 

Series Winchester Controller Chips 3-69 

Serial/Parallel Converter 3-71 

AM Detector 3-75 

CRC Generator/Checker 3-79 

Parallel/Serial Converter 3-83 

ECC/CRC Logic 3-87 

Host Interface Logic 3-93 

Data Separator Support Logic 3-97 

Improved MFM Generator 3-101 

Winchester Disk Controller 3-107 



WINCHESTER DISK SUPPORT DEVICES 

WD10C20-05 Self-Adjusting Data Separator 4-1 

WD1014 Error Detection/Support Logic Device 4-15 

WD1015 Buffer Manager Control Processor 4-27 

WD1100-21 Buffer Manager Support Device 4-31 

WD11C00-13 ECC Support Device 4-37 

WD11C00-17 PC/XT Host Interface Logic Device 4-45 

SCSI-BUS INTERFACE CONTROLLER 



WD33C92/93 



SCSI-Bus Interface Controller 5-1 



WINCHESTER BOARD PRODUCTS 



WD1002-05 Winchester/Floppy Controller 6-1 

WD1002-HDO Winchester Controller 6-11 

WD1002-SHD Winchester Disk Controller 6-19 

WD1002-SAS Winchester/Floppy Disk Controller 6-31 

WD1002-WX1 Winchester Disk Controller 6-49 

WD1002S-SHD Winchester Disk Controller 6-51 

WD1002C-WX2 Winchester Controller Board 6-89 

WD1002S-WX2 Winchester Controller Board 6-91 

WD1002-WAH Winchester Disk Controller 6-119 

WD1002-WA2 Winchester Disk Controller 6-137 

WD1003-SCS Winchester Disk Controller 6-157 

WD1003-WA2 Winchester Disk Controller 6-173 

WD1003-WAH Winchester Disk Controller 6-175 

TAPE DRIVE CONTROLLER PRODUCTS 

WD2401 Buffer Management Tape Controller 7-1 

WD2404 Tape Data Separator Module 7-17 

WD24C02 Read/Write Formatter 7-21 

WD1036R-SHD Streaming Tape Controller 7-25 

WD1036S-WX2 Streaming Tape Controller 7-35 

MAIN MEMORY DEVICE 

WD8206 Error Detection and Correction Unit 8-1 

INTEGRATED DRIVE ELECTRONICS 

WD93020 Integrated Drives 9-1 



Numerical index 

Part Number Page 

WD1002-05 6-1 

WD1002-HDO 6-11 

WD1002-SAS 6-31 

WD1002-SHD 6-19 

WD1002-WAH 6-119 

WD1002-WA2 6-137 

WD1002-WX1 6-49 

WD1002S-SHD 6-51 

WD1002C-WX2 6-89 

WD1002S-WX2 6-91 

WD1003-SCS 6-157 

WD1003-WAH 6-175 

WD1003-WA2 6-173 

WD1010-05 3-1 

WD1014 4-15 

WD1015 4-27 

WD1036R-SHD 7-25 

WD1036S-WX2 7-35 

WD1050 3-31 

WD10C20-05 4-1 

WD1100 3-69 

WD1100-01 3-71 

WD1100-03 3-75 

WD1100-04 3-79 

WD1100-05 3-83 

WD1100-06 3-87 

WD1100-07 3-93 

WD1100-09 3-97 

WD1100-12 3-101 

WD1100-21 4-31 

WD11C00-13 4-37 

WD11C00-17 4-45 

WD1691 2-1 

WD16C92 2-9 

WD177X-00 1-1 

WD1772-02 1-27 

FD179X-02 1-53 

WD2010-05 3-107 

WD2143-03 2-13 

WD2401 7-1 

WD2404 7-17 

WD24C02 7-21 

WD279X-02 1-91 

WD33C92/3 5-1 

WD8206 8-1 

WD9216-00/01 2-17 

WD92C32 2-21 

WD93020 9-1 



WESTERN DIGITAL 

CORPORATION 

System Product Quality/Reliability 



QUALITY PROGRAM DESCRIPTION 

The Quality Organization shown on the attached 
organization chart (Figure 2) reports directly to the 
President of Western Digital. It assures compliance 
to design control, quality, and reliability specifications 
pursuant to corporate policy. Quality assurance pro- 
visions are derived in part from MIL-Q-9858, as applied 
to high grade commercial products. 

CORPORATE QUALITY POLICY 

It is the policy of Western Digital Corporation that 
every employee be committed to quality excellence 
in producing products/processes which conform to 
acceptable requirements. The total quality program 
is managed and monitored by the quality assurance 
organization. Quality assurance is chartered to review 
marketing product requirements, qualify hardware and 
software designs, certify manufacturing operations 
and monitor performance/control conformance to pro- 
duct specifications. 

Primary responsibility for execution of the quality pro- 
gram rests with functional organizations to design, 
produce, and market high quality and high reliability 
products specified to our customers. 



DESIGNING FOR RELIABILITY 

The premise upon which board and system manufac- 
turing operations are based is that quality is planned 
and designed-in, not screened-in or selected. A well- 
tested, high-quality design is far more reliable than 
a marginal design with any amount of burn-in or fixes. 
To assure top quality design, Western Digital main- 
tains one of the most experienced board/system 
design staffs in the industry. A tightly controlled 
design review team comprising members from Quality 
Assurance, Marketing, Manufacturing and several 
experienced design engineers, provides review of 
each new design several times during its development 
to ensure widest possible performance margins. The 
production release procedure assures a checklist for: 

Q'Test Method/Program Qualifications 

& Characterization Report 

Q- Field Test (Beta Test) Report 

rSr Product Qualification Audit 

[3* Documentation Package Release for 

Document Control 
Q* Software/Diagnostics Qualification 



MAINTAINING QUALITY/RELIABILITY IN PRODUCTION 

The Quality Control Testing Fiow Chart shown on 
Figure 1 defines the exact stages contained in the 
production process. Internally manufactured LSI com- 
ponents undergo 100% testing at maximum specified 
operating temperatures as well as strict quality con- 
trols defined to assure high quality and reliability. 
Components not designed and manufactured by 
Western Digital are also 100% screened during 
incoming inspection at 70°C. The tests performed 
include selective active component burn-in perfomned 
at 125°C for 160 hours to insure guaranteed levels of 
reliability. This 125°C accelerated testing eliminates 
defects that cannot effectively be accelerated by 
burning-in boards and systems which have 
temperature limitations. Key quality control pro- 
cedures include: 

S* Incoming Inspection Procedure 

B* In-Process Travel Card Traceability 

(3' Workmanship Standards 

B* Quality Corrective Action Notice/MRB Procedure 

CS* Quality Audit Procedure 

PRODUCT FINAL TEST/CORRECTIVE ACTION 

All boards are 100% in-circuit tested and 100% func- 
tional tested for acceptable performance according 
to applicable test specifications on testers qualified 
by QA. Products are tested at maximum specified 
temperature and voltage margins using diagnostic 
software to ensure greater performance margins. 
Failures are logged on a travel card specifically 
designed to insure traceability to manufacturing steps 
and to maintain failure records for QA corrective 
action. 

If the board is designed to perform in a Host system, 
further diagnostics are performed in an environment 
configured to actual customer requirements. 

PRODUCT ACCEPTANCE 

Upon completing the final test, the board/system 
undergoes QC final workmanship standards inspec- 
tion and selective samples are audited to the func- 
tional product specification to guarantee quality at 
specified operating margins to the customer. 



\ QC / Receiving Inspection 
\ / • 100% Bare Board Testing 
\/ • 100% LSI Test (max. temp.) 
^ • 100% ICTestat 70'C 

• Power Supply Inspections 

• Mechanical/Visual Inspections 



Selective Static/Dynamic Burn-in 
(Active components) 



6 




P.C. Board Assembly 



Assembly Test (Bed of Nails) 

• Stiorts/Opens 

• Orientation 



Assembly Outgoing Inspection 



\QC / Jest Incoming/Travel Card 
\ / Traceability 



V 



Functional Test 

• Voltage Margins 

• Temperature Margins 

• Diagnostic Software 



Final Inspection 

• Revision Control 



Functional Audit 
Travel Card Review 



^ 



LEGEND: 

[ J Mfg. Operation 



o> 



Ship Board Product 



n Mfg 




Mainframe Mechanical 
Assembly 



Travel Card Traceability 




Mainframe Inspection 



System Configuration 

Functional Test 

• Temp. Margins 

• Diagnostic Software 



Final inspection 

HZZ 



^ 



Ship System 



. Inspection Gate 



V 



QC Gate 



Figure 1. QUALITY CONTROL TESTING FLOW CHART 





WESTERN DIGITAL CORPORATION 
CHIEF EXECUTIVE 


















CORPORATE 
QUALITY ASSURANCE 






































SYSTEMS QUALITY 




PRODUCT RELIABILITY 




LSI PRODUCT ASSURANCE 




LSI MATERIAL ASSURANCE 



Systems Quality 

New Product 

Qualification 

System Test 

Qualification 

Software 

Qualification 



LSI Qualification 

Burn-In/Stress 

Requirements 

Reliability Monitor 

Data 

Reliability Testing 



Document Control 
Wafer Defects Control 
Subsidiary/Offsfiore QC 
Process Qualification 



Incoming QC 

Vendor Quality 

LSI Burn-In 

LSI Package Monitors 

Precap Visuals (883 optional) 

100% Test Audit 

Failure Analysis 

Package Qualification 

Calibration Control 



"Systems Design 
Control" 



'LSI Design Control" 



"Manufacturing Assurance" 



Figure 2. QUALITY ORGANIZATION 



WESTERN DIGITAL 

CORPORATION 

Quality/Reliability To Leading Edge Technology 



QUALITY ASSURANCE PROGRAM HIGHLIGHTS 

• LSI manufacturing assurance provisions are 
derived in part from MIL-M-38510 and MIL- 
STD-883B as applied to high grade commerical 
components. 

• All process raw materials used in the Mask/Wafer 
fabrication and assembly operations are 
monitored by Material Assurance. 

• Material Assurance maintains a thorough control 
of incoming material and has developed unique 
"use/stress tests" (look ahead sample build accep- 
tance) which critical material must pass before 
acceptance. 

• The product assurance Department continuously 
monitors the internal and external manufacturing 
flow (shown in Figure 1) and issues process con- 
trol reports displaying detailed data and trends for 
the associated areas. 

- Document control is an integral part of Product 
Assurance. All specifications are issued and 
controlled by this activity. 

- The Western Digital Malaysian assembly 
operation uses specifications and quality con- 
trol provisions controlled by Document Control. 
Indicators of Malaysia quality are reviewed 
weekly. 

- Purchased FAB and assembly operations are 
individually qualified and are certified against 
standard specifications during vendor 
qualification and monitored against reliability 
criteria. 



- Defect control within the process assures the 
highest levels of built-in reliability. 

Quality audits and gates are located throughout 
the manufacturing process in order to assure a 
stable process and thus, a quality product to our 
customers. Figure 1 illustrates the manufactur- 
ing/screening/inspection flow diagram and iden- 
tifies the steps as they relate to the production 
of LSI devices. 

Testing assures quality margins through 100% 
testing by manufacturing and, in addition, all pro- 
ducts must pass a specified AQL sample test per- 
formed by QA at maximum operating temperature 
as follows: 

Outgoing Quality Levels 



SUBGROUPS 



INSPECTION LEVEL 



Subgroup 1-Final 100% Electrical 
Audit @ Max °C 0.5 AQL 

Subgroup 2-Visual (Marking, Lead 
Integrity, Package, Verify customer 
shipper) 1.0 AQL 

Subgroup 3-Shipping Visual Audit 1.0 AQL 



*The double sampling techniques used allow con- 
siderably better AQL's in most all cases. 

• LSI devices are 100% tested on industry standard 
test systems. Quality outgoing testing (auditing) 
is done on the Fairchild Sentry Series 20 where 
possible to allow better correlation with 
customers. 



• PROGRAMS TO ASSURE OPTIMUM RELIABILITY 

improved levels of reliability are available under custom reliability programs using static and dynamic burn-In 
to further improve reliability. These programs focus on MOS failure mechanisms as follows: 

FAILURE MECHANISMS IN MOS 



FAILURE 


EFFECT ON 


ESTIMATED 


SCREENING 


MECHANISM 


DEVICE 


ACTIVATION ENERGY 


METHOD 


Slow Trapping 


Wearout 


1.0 eV 


Static Burn-In 


Contamination 


Wearout/ 
Infant 


1.4 eV 


Static Burn-In 


Surface Charge 


Wearout 


0.5-1.0 eV 


Static Burn-In 


Polarization 


Wearout 


1.0 eV 


Static Burn-In 


Electromigration 


Wearout 


1.0 eV 


Dynamic Burn-in 


Microcracks 


Random 


- 


100% Temp. Cycling 


Contacts 


Wearout/ 
Infant 


• 


Dynamic Burn-in 


Oxide Defects 


Infant 


0.3 eV 


Dynamic Burn-In 




Random 




at max. voltage 


Electron Injection 


Wearout 


■ 


Low Temp. Voltage 
Operating Life. 



Temperature Acceleration of Failure 

The Arrhenius Plot defines a failure rate propor- 
tional to exp (- Ea/kt) where Ea is the activation 
energy for the failure mechanism. The figure on 
the right indicates that lower activation energy 
failures are not effectively accelerated by 
temperature alone; hense, maximum voltage 
operation is selectively applied to optimize the 
burn-In process. 

Static Burn-In (125°C-48 hours or 160 hours) 

Provided on a sample basis for process 
monitor/control of 0.5 eV - 1.0 eV failure 
mechanisms. 100% static burn-in may be 
specified at an additional cost. However, static 
burn-in is considered only partially effective for 
internal LSI gates at logic "O" levels. 

Dynamic Burn-In (Pattern test/1 25°C - 8 hours to 160 
hours) 

Accelerated functional dynamic operating life 
effectively controls internal MOS gate defects 
buried from external pin access. The input pattern 
is optionally pseudo-random or fixed pattern pro- 
grammable to simulate 1000-3000 hours of field 
operation at maximum operating voltage(s). 

High-Re! "K" Testing Program 

General conformance to MIL-STD-883B method 
5004.4, Class B with static Burn-In (Dynamic Burn- 
In may be specified as an option). 




75 100 125 150 175 200 
TEMPERATURE (°C) 



RELIABILITY MEANS LASTING VALUE 

DESIGNING FOR RELIABLILITY 

The Production release procedure for an LSI device 
is designed to assure maximum reliability with a 
Quality checklist for: 

0* Test Program Qualifications 
0" Characterization report 
0* Field test (Beta Test) report 
0' Reliability Lifetest Qualifications 
Infrared Thermal Analysis 
0* Static Protection 

All New devices and major process changes must 
pass reliability qualification before incorporation into 
production using the criteria defined in Tables 2-4. The 
infrared microscope assures optimum burn-in 
temperatures and margins of safety. The dynamic 
burn-in system is one of two custom designed 
systems which assure protective device isolation dur- 
ing burn-in. 

• MAINTAINING RELIABILITY IN PRODUCTION 

Process defect controls are defined to continually 
measure built-in reliability, as measured by the follow- 
ing criteria: 

TABLE 1 



PROCESS RELIABILITY CONTROL 


METHOD 


CONDITION 


SAMPLE* 


Subgroup 1-Defects Control 
a. Oxide Integrity 


Non-destructive 
bubble test 


Pinhole defect density 


5 wafers 


b.Polysilicon Integrity 

Subgroup 2-Electro-Migration Control 

Metal Step Coverage 


SEM Analysis 

MIL-STD-883 
Method 2018 


Visual 

SEM Analysis 


5 wafers 
5 wafers 


Subgroup 3-Defect Density 


Critical layers 

Field 

Gate 

Contact 

Metal 


Visual of Photo defects 
(Defects/in^ 


8 wafers 
each layer 


Subgroup 4-Passivation/lnsulation 
Priority 


MIL-STD-883 Method 


Visual of Pinhole 


Final Silox 




2021 


defect density 


5 wafers 

Intermediate 

5 wafers 



Inspection intervals are defined by the in-line process control data reviewed on a lot-by-lot basis. 



LSI RELIABILITY STANDARDS 



TABLE 2 STANDARD RELIABILITY LEVELS 



TEST 


METHOD 


CONDITION 


FAILURE 


Infant 


Static 


125°C - 160 hrs. 


<0.5% 


Mortality 


Burn-In 






(see note) 








Long Term 


Dynamic 


125°C - 1000 hrs. 


<.05%/1000 hrs. 


Failure Rate 


Life Test 




@55°C 
60% Confidence 



NOTE: Devices failing the infant mortality target remain in burn-in until acceptable failure rates are obtained. 
TABLE 3 GROUP A DEVICE RELIABILITY MONITORS 



TEST 


METHOD 


CONDITIONS 


LTPD 


Subgroup 1 
a.lnternal Visual 
b.Thermal Shock 
C.Bond Strength 
d.Die Shear Strength 


1011 
2011 
2019 


Test Failure Used (cond. B or C) 
Test Failures (cond.B) 
Test Failures 


15 


Subgroup 2 
a.Seal-Gross Leak 

b.Seal-Fine Leak 


1014 


Fluorocarbon detection 10-3 

atm/cc/sec 

Test Condition A 


15 


Subgroup 3 

a.Rotating Steady State Life Test 

b. Electrical Parameters 


1005 


Static 160 hr. Burn-In 125°C 
plus 125°C Lifetest - 1000 hrs. 
Final electrical @ 25°C (with data @ 
70°C) 


5 



TABLE 4 GROUP B PACKAGE RELIABILITY MONITORS 



TEST 


METHOD 


CONDITIONS 


LTPD 


Subgroup 1 

a. Thermal Shock 

b. Temperature Cycling 

c. Seal-Gross Leak 

d. Seal-Fine Leak (ceramic 

e. Electrical Parameters 

f. 85/85 Moisture Resistance 
(plastic only) 
g.Electrical Parameters 


1011 
1010 

1014 


Test Condition B or C 

Test Condition B or C 

Fluorocarbon detection 10"^ 

atm/cc/sec 

Test Conditoin A 

Electrical at max-C 

85% RH/85°C for 1000 hours 

PDA = 10% 

Final electrical @25°C 


15 


Subgroup 2 

a. High Temp. Storage 

b. Mechanical Shock 

c. Seal - Gross Leak 

d. Seal - Fine Leak 
(ceramic) 

e. Electrical Parameters 


1008 
2002 

1014 


Test Condition B or C 
Test Condition B 
Fluorocarbon detection 10"^ 
atm/cc/sec 
Test Condition A 

Final electrical @ 25°C/max. C 


15 


Subgroup 3 

a. Lead Integrity 

b. Seal ■ Gross Leak 

c. Seal - Fine Leak 
(ceramic) 


2004 
1014 


Test Condition B2 
(Lead Fatigue) 
Fluorocarbon detection 10"^ 
atm/cc/sec 
Test Condition A 


15 



WESTERN DIGITAL CORPORATION 
CHIEF EXECUTIVE 



CORPORATE 
QUALITY ASSURANCE 



SYSTEMS QUALITY 



PRODUCT RELIABILITY 



LSI PRODUCT ASSURANCE 



LSI MATERIAL ASSURANCE 



Systems Quality 

New Product 

Qualification 

System Test 

Qualification 

Software 

Qualification 



LSI Qualification 

Burn-In/Stress 

Requirements 

Reliability Monitor 

Data 

Reliability Testing 



Document Control 
Wafer Defects Control 
Subsidiary/Offshore QC 
Process Qualification 



Incoming QC 

Vendor Quality 

LSI Burn-In 

LSI Package Monitors 

Precap Visuals (883 optional) 

100% Test Audit 

Failure Analysis 

Package Qualification 

Calibration Control 



"Systems Design 
Conlrol" 



'LSI Design Control" 



"Manufacturing Assurance' 



Figure 2 QUALITY ORGANIZATION 



10 



WESTERN DIGITAL 

CORPORATION 

Announcing Burn-in Program Availability/Warranties 

Western Digital now supports customer burn-in 
requirements for both static and dynamic burn-in 
under the strict control of the QA-Reliability 
Organization. 

This burn-in provides high peformance 125°C static 
and dynamic burn-in for 8-160 hours to eliminate in- 
fant mortality and improve reliability. This process is 
executed using custom modified 32Bit, AEHR test 
commerical burn-in equipment which provide 
monitored fixed pattern or pseudo random burn-in 
with power supply and resistor device pin isolation. 

LSI dynamic burn-in is verified in all cases by the 
design engineer for proper functioning. LSI Chip sets 
are also individually burned-in with dynamic equiv- 
alency to assure high performance bundled reliability. 

The warranty on the program will optionally provide 
certificate of compliance to standard or custom 
designed burn-in programs and guarantee 
<.05%/Khrs failure rate. 

CAUTION 

Using outside burn-in methods not certified as accep- 
table by Western Digital may result in voided war- 
ranty, due to mishandling, junction temperature 
stress, or electrical damage. Further, since most burn- 
in houses do not support testing, catastrophic system 
condition can result in substantial damage before a 
problem is identified. 

One consistent problem experienced with outside LSI 
bum-in houses can cause reliability problems; namely, 
parallelling totem pole MOS outputs, where the out- 
put states are not predictable, can cause a single (or 
a few) device(s) to sink all the current from the other 
devices on the burn-in tray - electromigration or cur- 
rent zaps are both possible. 

Western Digital burn-in diagrams, dated after 1/1/82, 
must be used exactly as shown and will be provided 
upon request. 

SEE YOUR LOCAL REPRESENTATIVE FOR COSTS AND 
ORDERING INFORMATION ON THIS NEW PROGRAM. 



11 



12 



WESTERN DIGITAL 

CORPORATION 

Hi-Rel "K" Testing Program 



FEATURES 

GENERAL CONFORMANCE TO MIL-STD-883B, 
METHOD 5004.4, CLASS B (SEE COMPARISON ON 
FOLLOWING PAGES) 

• INCLUDES: 

PRECAP VISUALS 
SEAL INTEGRITY 
POWER CONDITIONING 
ENHANCEMENT OPTIONS 



GENERAL DESCRIPTION 

Western Digital's Hi-Rel "K" program is designed to 
provide higli reliability devices for extended 
temperature environments. Individual enhancements 
may be specified to meet a customer's requirements. 



INITIATE 
LOT 
PACKAGE PROBED WAFERS TRAVELER 



I 



RECEIVING 
INSPECTION 

CLEAN <QC) AUDIT 



BACKSIDE ID 



QC> AUDIT 



LID 

V 



SCRIBE/SAW 

BREAK/SORT 

INSPECT 

CHIPBOND 

INSPECT 

WIRE BOND 

INSPECT 

CLEAN/BAKE/SEAL 

TEMP CYCLE 
10 CYCLES 
-eS'Z + ISO'C 

STABAKE 
24HRS150°C 



QC> AUDIT 



FINE LEAK 



GROSS LEAK 



CUT/ FORM LEADS 



PRE BURN-IN 
ELECTRICALS 



BURN-IN 
160HRS@ 125'C 



CERTIFICATE 

OF 

CONFORMANCE 




HIREL "K" PROGRAM FLOW DIAGRAM 



13 



COMPARISON OF MIL-STD-883 
AND HI-REL "K" TEST PROGRAM 



MIL-STD-883B, METHOD 5004.4, CLASS B 


HI-REL "K" TEST 


3.1.1 internal Visual 




IVIethod 2010.3 


All Hl-Rel "K" devices receive 100% Inspections 


Test Condition B 


prior to lid seal. These inspections together com- 




prise criteria comparable to MII-Std-883, method 




2010.3, test condition B. 


3.1.2 Stabilization Bake 




Method 1008.1 


Same 


Test condition C 




24 hiours at 150°C 




3.1.3 Temperature Cycling 




Method 1010.2, Test condition C 


Same 


-65°C to 150°C for 10 cycles, with 10 minutes 




dwell and 5 minutes maximum transfer time 




3.1.4 Constant Acceleration 




Method 2001.2, Test condition E 30,000 G stress 




level 


Not done Unless Specified 


3.1.5 Visual Inspection 




Visual inspection for catastrophic failures after 




screens 


Same 


3.1.6 Seal Method 1014.2 




(a) Heilum fine leak - Test condition A^. Bomb 


Same 


condition 2 hours at 60 psig. Reject limit 5x10'^ 
torr 




(b) Fluorocarbon gross leak - Test condition C 


Same 


3.1.9 Interim (pre-burn-in) Electricals 




Per applicable device specification 


Preburn-ln test at 25°C. Must meet requirements of 




device data sheets. 


3.1.10 Burn-in Test 




Method 1015.2 160 hours @ 125°C 


Same 


3.1.13 Interim (Post burn-in) electricals 




Per applicable device specification 


Burn-in equipment isolate failures automatically to 




assure no harmful interaction. 


3.1.15 Final Electrical Test 




(a) Static Tests 


Same 


(1) 25°C 




(2) Minimum and Maximum Operating 




Temperatures 




(b) Dynamic and Switching Tests at 25°C 




(c) Functional Tests at 25°C 




3.1.17 Qualification or Quality Conformance 


Not done unless specified using method 5005 as a 


Inspection and Test Sample Selection 


guide. 


3.1.18 External Visual 




Method 2009.2 


Same 



WESTERN DIGITAL RELIABILITY ENHANCEMENT 

OPTIONS 

100% Temperature Testing 

Level -40° to + 85°C 

-55° to +125°C 

Thermal, Shock (Liquid to Liquid) 

Level 0° to + 100°C, 15 cycles 

-55° to +125°C 

-65° to -f150°C 



Extended High Temperature Storage 

+ 150°C for 24 hours standard, other time/tempera- 
ture storage requirements available required. 

Dynamic Burn-In 

Per note previously supplied. 



14 



WESTERN DIGITAL 

CORPORATION 

WD177X-00 Floppy Disk Formatter/Controller 



FEATURES 

28 PIN DIP 

SINGLE 5V SUPPLY 

BUILT-IN DIGITAL DATA SEPARATOR 

BUILT-IN WRITE PRECOMPENSATION 

SINGLE (FM) AND DOUBLE (MFM)t DENSITY 

MOTOR CONTROL (WD1770 AND WD1772) 

128, 256, 512 OR 1024 SECTOR LENGTHS 

TTL COMPATIBLE 

8-BIT BI-DIRECTIONAL DATA BUS 

TWO VERSIONS AVAILABLE 

WD1770/WD1773 = STANDARD 179X STEP 

RATES 

WD1 772 1= FASTER STEP RATES 

• THE WD1773 HAS 100% COMPATIBLE SOFT- 
WARE WITH THE WD1793 

GENERAL DESCRIPTION 

The WD177X-00 is a MOS/LSI device which performs 
the functions of a Floppy Disk Formatter/Controller. 
It is similar to its predecessor, the FD179X, but also 
contains a digital data separator and write 
precompensation circuitry. The drive side of the inter- 
face needs no additional logic except for buf- 
fers/receivers. It is designed for single (FM) or double 
(MFM) density operation. 

The WD177X-00 is implemented in NMOS silicon gate 
technology and is available in a 28-pin dual-in-line as 
well as in quad pack. 

Three versions of the WD177X-00 are available. The 
WD1770, WD1772 and the WD1773. 

With the exception of the enable precomp/ready line, 
the WD1773 is identical to the WD1770 controller. It 
is fully software compatible with the WD1793. The 
WD1770-00 and WD1773-00 are compatible with the 
FD179X stepping rates, while the WD1772-00 offers 
stepping rates of 2, 3, 6, and 12 msec. 

The WD177X-00 devices all contain a built-in digital 
data separator which virtually eliminates all external 
components and adjustments associated with data 



CS 
R/W 

AO 

A1 
DALO 
DAL1 
DAL2 
DAL3 
DAL4 
DAL5 
DAL6 
DAL7 

MR 
GND 





,. ^ 


28 




2 


27 




3 


26 




4 


25 




5 


24 




6 


23 




7 


22 




8 


21 




9 


20 




10 


19 




11 


18 




12 


17 




13 


16 




14 


15 



INTRQ 
DRQ 

ddeKI 

WPRT 
IP 



TROO 

WD 

WG 

MO (RDY/ 

RD ENP) 

CLK 

DIRC 

STEP 

VCC 



DIP PIN DESIGNATION 

recovery in previous designs. A single read line (RD, 
Pin 19) is the only input required to recover serial FM 
or MFM data from the disk drive. The device is design- 
ed for control of floppy disk drives with data rates 
of 125 KBits/Sec (single density) and 250 KBits/Sec 
(double density). In addition, write precompensation 
of 125 nsec from nominal is enabled at any point 
through simple software commands. Another pro- 
grammable feature on the WD1770AA/D1772 is Motor 
On, which enables the spindle motor automatically 
prior to operating a selected drive. 

The processor interface consists of an 8-bit bi- 
directional bus for transfer of status, data, and com- 
mands. All Host communication with the drive occurs 
through these lines. They are capable of driving one 
standard TTL load or three LS loads. 



o 
o 



Floppy Disk Controller Devices 



1-1 



PIN 










NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


1 
2 


CS 

R/W 




1 
1 


A logic low on this input selects the chip and enables 
Host communication with the device. 

A logic high on this input controls the placement of 
data on the D0-D7 lines from a selected register, while 
a logic low causes a write operation to a selected 
register. 


CHIP SELECT 


READ/WRITE 


3,4 


A0,A1 


ADDRESS 0,1 


1 


These two inputs select a register to Read/Write data: 
CS A1 AO R/W = 1 R/W = 

status Reg Commad Reg 
1 Track Reg Track Reg 
1 Sector Reg Sector Reg 
1 1 Data Reg Data Reg 


5-12 


DAL0-DAL7 


DATA ACCESS 

LINES 

THROUGH 7 


I/O 


Eight-bit bi-directional bus used for transfecof data, 
cojTtrol, or status. This bus is enabled by CS and 
RA/V. Each line will drive one TTL load. 


13 


MR 


MASTER RESET 


1 


A logic low pulse on this line resets the device and 
initializes the Status Register (internal pull-up). 


14 


GND 


GROUND 




Ground. 


15 


Vcc 


POWER SUPPLY 


1 


+ 5V±5% power supply input. 


16 


STEP 


STEP 





The Step output contains a pulse for each step of the 
drive's R/W head. The WD177(K)0 and WD1 772-00 offer 
different step rates. 


17 


DIRC 


DIRECTION 





The Direction output is high when stepping in towards 
the center of the diskette, and low when stepping out. 


18 
19 


CLK 
RD 


CLOCK 


1 
1 


This input requires a free-running 50% duty cycle clock 
(for internal timing) at 8 MHz +0.1%. 

This active low input is the raw data line containing 
both clock and data pulses from the drive. 


READ DATA 


20 


RDY/ENP 


READY/ENABLE 

PRECOMP 

(WD1773) 


1 


Serves as a READY input from the drive during 
READ/STEP operations and as a Write Precomp enable 
during Write operations. The state of READY is latched 
upon WG true, and this dual input is used for 
precompensation enable. 


20 


MO 


MOTOR ON 
(WD1770 or 
WD-1772) 





Active high output used to enable the spindle motor 
prior to read, write or stepping operations. (WD1770, 
WD1772 only) 


21 


WG 


WRITE GATE 





This output is made valid prior to writing on the 
diskette. 


22 
23 

24 

25 


WD 
TROO 

IP 


WRITE DATA 




1 
1 
1 


FM or MFM clock and data pulses are placed on this 
line to be written on the diskette. 

This activ^low input informs the WD1770-00 that the 
drive's R/W heads are positioned over Track zero. 

This active low input informs the WD177&O0 when the 

physical Index hole has been encountered on the 

diskette. 

This input is sampled whenever a Write Command is 

received. A logic low on this line will prevent any Write 

Command from executing (internal pull-up). 


TRACK 00 


INDEX PULSE 


WPRT 


WRITE PROTECT 



1-2 



Floppy Disk Controller Devices 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


26 

27 
28 






1 





This input pin selects either single (FM) or double 
(MFM) density. When DDEN = 0, double density is 
selected (internal pull-up). 

This active high output indicates that the Data Register 
is full (on a Read) or empty (on a Write operation). 
This active high output is set at the completion of any 
command, is reset by a read of the Status Register. 


DDEN 

DRQ 
INTRQ 


DOUBLE 
DENSITY 
ENABLE 

DATA REQUEST 

INTERRUPT 
REQUEST 



o 
:>< 

o 
o 



WD 1773-02 ONLY 



D0-D7 
N M 



ENP/ 
RDY 



gndVcc 



RDY 
I 



-JIT. 



WD177X-02 SYSTEM BLOCK DIAGRAM 

ARCHITECTURE 

The primary sections of the Floppy Disk Formatter are 
the Parallel Processor Interface and the Floppy Disk 
Interface. 

Data Shift Register - This 8-bit register assembles 
serial data from the Read Data input (RD) during 
Read operations and transfers serial data to the Write 
Data output during Write operations. 

Data Register - This 8-bit register is used as a holding 
register during Disk Read and Write operations. In 
disk Read operations, the assembled data byte is 
transferred in parallel to the Data Register from the 
Data Shift Register. In Disk Write operations, infor- 
mation is transferred in parallel from the Data 
Register to the Data Shift Register. 

When executing the Seek Command, the Data 
Register holds the address of the desired Track posi- 



tion. This register is loaded from the DAL and gated 
onto the DAL under processor control. 

Track Register - This 8-bit register holds the track 
number of the current ReadAA/rite head position. It is 
incremented by one every time the head is stepped 
in and decremented by one when the head is step- 
ped out (towards track 00). The contents of the 
register are compared with the recorded track number 
in the ID field during disk Read, Write, and Verify 
operations. The Track Register can be loaded from 
or transferred to the DAL. This Register is not loaded 
when the device is busy. 

Sector Register (SR) - This 8-bit register holds the 
address of the desired sector position. The contents 
of the register are compared with the recorded sec- 
tor number in the ID field during disk Read or Write 
operations. The Sector Register contents can be 
loaded from or transferred to the DAL. This register 
is not loaded when the device is busy. 

Command Register (CR) - This 8-bit register holds the 
command presently being executed. This register is 
not loaded when the device Is busy unless the new 
command is a force interrupt. The Command Register 
is loaded from the DAL, but not read onto the DAL. 

Status Register (STR) - This 8-bit register holds device 
Status information. The meaning of the Status bits 
is a function of the type of command previously 
executed. This register is read onto the DAL, but not 
loaded from the DAL. 

CRC Logic - This logic is used to check or to generate 

the 16-bit Cyclic Redundancy Check (CRC). The 

polynomial is: 

G(x) = x^s + x^2 + x5 +1. 

The CRC includes all information starting with the 

address mark and up to the CRC characters. The CRC 

Register is preset to ones prior to data being shifted 

through the circuit. 

Arithmetic/Logic Unit (ALU) - The ALU is a serial com- 
parator, incrementer, and decrementer and is used 
for register modification and comparisons with the 
disk recorded ID field. 



Floppy Disk Controller Devices 



1-3 



:>< 

O 

o 



(DAL) 



DATA OUT 
BUFFERS 



DATA 
REG 



COMMAND 
REG 



DATA 
SHIFT 
REG 



SECTOR 
REG 



<] 



AM DETECTOR 



CRC LOGIC 



,— I TRACK 
REG 



-tl 



rn 



STATUS 
REG 



♦-< RD 



WRITE 
PRECOMP 



DATA 
SEPARATOR 



DRQ 


COMPUTER 
INTERFACE 
CONTROL 


CONTROL 


PLA 
CONTROL 
(240X19) 


CONTROL 


DISK 
INTERFACE 
CONTROL 




WG 


^ INTRO 




WPRT 


MR 






CS * 


IP 


:= ► 

R/W 




TROO 








AO 






STEP 


*■• » 


DIRC 






RDY 


CLK (8-MHZ) _ 




(MOTOR ON) 


bD^N 









FIGURE 1. WD177X-00 BLOCK DIAGRAM 



Timing and Control - All computer and Floppy Disk 
interface controls are generated through this logic. 
The internal device timing is generated from an exter- 
nal crystal clock. The WD177X-00 has two different 
modes of operation according to the state of 
DDEN. 



When DDEN = 0, double density (MFM) is enabled. 
When DDEN = 1, single density is enabled. 

AM Detector - The address mark detector detects ID, 
data and index address marks during read and write 
operations. 

Data Separator - A digital data separator consisting 
of a ring shift register and data window detection 
logic provides read data and a recovery clock to the 
AM detector. 



PROCESSOR INTERFACE 

The interface to the processor is accomplished 
through the eight Data Access Lines (DAL) and 
associated control signals. The DAL are used to 
transfer Data, Status, and Control words out of, or 
into the WD177X-00. The DAL are three state buffers 
that^ are enabled as output drivers when CS and 
RA/V =_[ are active or act as input receivers when CS 
and RAA/ = are active. 

When transfer of data with the Floppy Disk Controller 
is required by the Host processor, the device address 
is decoded and CS is made low. The address bits A1 
and AO, combined with the signal FVW during a 
Read operation or Write operation are interpreted as 
selecting the following registers: 



1-4 



Floppy Disk Controller Devices 



A1 - AO 



READ (R/W = 1) 



Status Register 
Track Register 
Sector Register 
Data Register 



WRITE (R/W = 0) 



Command Register 
Tracl< Register 
Sector Register 
Data Register 



After any register is written to, tlie same register can- 
not be read from until 16 /isec in MFM or 32 fisec in 
FM have elapsed. 

During Direct Memory Access (DMA) types of data 
transfers between the Data Register of the WD177X-00 
and the processor, the Data Request (DRQ) output 
is used in Data Transfer control. This signal also 
appears as status bit 1 during Read and Write 
operations. 

On Disk Read operations the Data Request bit is 
activated (set high) when an assembled serial input 
byte is transferred in parallel to the Data Register. This 
bit is cleared when the Data Register is read by the 
processor. If the Data Register is read after one or 
more characters are lost, by having new data transfer- 
red into the register prior to processor readout, the 
Lost Data bit is set in the Status Register. The Read 
operations continue until the end of sector is reached. 

On Disk Write operations the Data Request bit is 
activated when the Data Register transfers its con- 
tents to the Data Shift Register, and requires a new 
data byte. It is reset when the Data Register is loaded 
with new data by the processor. If new data is not 
loaded at the time the next serial byte is required by 
the Floppy Disk, a byte of zeroes is written on the 
diskette and the Lost Data bit is set in the Status 
Register. 

At the completion of every command an INTRO is 
generated. INTRO is reset by either reading the Status 
Register or by loading the Command Register with 
a new command. In addition, INTRO is generated if 
a Force Interrupt Command condition is met. 

The WD177X-00 h as two modes of ope ration accor- 
ding to the state DDEN. When DDEN = 1, single 
density is selected. In either case, the CLK input is 
at 8 MHz. 

GENERAL DISK READ OPERATIONS 

Sector lengths of 128, 256, 512 or 1024 are obt ainable 
in either FM or MFM formats. For F M. DDE N 
is placed to logical 1. For MFM formats, DDEN is 
placed to a logical 0. Sector lengths are determined 
at format time by the fourth byte in the ID field. 



SECTOR LENGTH TABLE 



SECTOR LENGTH 
FIELD (HEX) 



NUMBER OF BYTES 
IN SECTOR (DECIMAL) 



00 
01 
02 
03 



128 
256 
512 
1024 



The number of sectors per track for the WD177X-00 
are from 1 to 240. The number of tracks for the 
WD177X-00 are to 240. 

GENERAL DISK WRITE OPERATION 

When writing on the diskette the WG output is 
activated, allowing current to flow into the ReadA/Vrite 
head. As a precaution to erroneous writing the first 
data byte is loaded into the Data Register in response 
to a Data Request from the device before the WG is 
activated. 

Writing is inhibited when the WPRT input is asser- 
ted, in which case any Write Command is 
immediately terminated, an interrupt is generated and 
the Write Protect Status bit is set. 

For Write operations, the WD177X-00 provides WG to 
enable a Write condition, and WD which consists of 
a series of active high pulses. These pulses contain 
both Clock and Data information in FM and MFM. WD 
provides the unique missing clock patterns for recor- 
ding Address Marks. 

The WD1773-00 enables write precompensation when 
RDY/ENP is asserted. When WG is asserted the 
READY status has been latched. WG is then used to 
demultiplex drive Ready Status from Host supplied 
enable for write precompensation at desired tracks. 

On the WD177(H)2 or WD1772-00, the Precomp Enable 
bit in Write Commands allows automatic Write 
precompensation to take place. The outgoing Write 
Data stream is delayed or advanced from nominal by 
125 nsec according to the following table: 



PATTERN 


MFM 


FM 


X 
X 


1 


1 





1 
1 







1 
1 




Early 
Late 
Early 
Late 


N/A 
N/A 
N/A 
N/A 


A i 






L 


- Next Bit to be sent 














- Previous Bits sent 



Precompensation is typically enabled on the inner- 
most tracks where bit shifts usually occur and bit 
density is at its maximum. READY is true for 
read/write operations (all Type II and III Command 
executions). 

COMMAND DESCRIPTION 

The WD177X-00 accepts 11 commands. Command 
words are only loaded in the Command Register when 
the Busy Status bit is off (Status bit 0). The one ex- 
ception is the Force Interrupt Command. Whenever 
a command is being executed, the Busy Status bit 
is set. When a command is completed, an interrupt 
is generated and the Busy Status bit is reset. The 
Status Register indicates whether the completed 
command encountered an error or was fault free. 
Commands are divided into four types and are sum- 
marized in the following pages. 



O 

.^ 

o 
o 



Floppy Disk Controller Devices 



1-5 



COMMAND SUMMARY 











BITS 








TYPE COMMAND 


7 


6 


5 


4 


3 


2 


1 





1 Restore 














h 


V 


ri 


rn 


1 Seek 











1 


h 


V 


i"i 


rn 


1 Step 








1 


u 


h 


V 


r^ 


rn 


1 Step-in 





1 





u 


h 


V 


h 


rn 


1 Step-out 





1 


1 


u 


h 


V 


r 


Tn 


II Read Sector 


1 








m 


h/s 


E 


0/C 





II Write Sector 


1 





1 


m 


h/s 


E 


P/C 


an 


III Read 


















Address 


1 


1 








li/o 


E 








III Read Tracl< 


1 


1 


1 





h/o 


E 








Hi Write Tracl< 


1 


1 


1 


1 


h/o 


E 


P/0 





iV Force 


















Interrupt 


1 


1 





1 


I3 


I2 


I1 


lo 



FLAG SUMMARY 



TYPE I COMMANDS 



h = Motor On Flag (Bit 3) (1770/2). 

h = 0, Enable Spin-up Sequence 
li = 1, Disable Spin-up Sequence 

V = Verify Flag (Bit 2) (1770/2/3) 

V = 0, No Verify 

V = 1, Verify on Destination Tracl< 

T^, Tq = Stepping Rate (Bits 1,0) 
WD1 770-00 
Th rn WD1 773-00 WD1 772-00 



6 ms 
12 ms 
20 ms 
30 ms 



6 ms 
12 ms 

2 ms 

3 ms 



u = Update Flag (Bit 4) (1770/2/3) 

u = 0, No Update 

u = 1, Update Track Register 



TYPE II & III COMMANDS 



m = Multiple Sector Flag (Bit 4) (1770/2/3) 

m = 0, Single Sector 
m = 1, Multiple Sector 

H - Motor on Flag (Bit 3) (1770/2) 

H = 0, Enable Spin-up Sequence 
H = 1, Disable Spin-up Sequence 

S = Side Compare Flag (Bit 3) (1773 only) 

S = 0, Compare for side 
S = 1, Compare ;for side 1 
For all Type III commands bit 3 must be 0. 

ap = Data Address Mark (Bit 0) (1770/2/3) 

ao = 0, Write Normal Data Mark 
ao = 1, Write Deleted Data Mark 



TYPE II & III COMMANDS (Continued) 



E = 30ms Settling Delay (Bit 2) (1770/2/3) 

E = 0, No Delay 

E = 1, Add 30ms Delay (1772 Add 15ms Delay* 

C = Side Compare Flag (Bit 1) (1773 only) 

C =: 0, Disable Side Compare 
C = 1, Enable Side Compare 
For all Type III commands bit 1 must be 0. 

P = Write Precompensation (Bit 1) (1770/2/3) 

P = O.Enable Write Precomp 
P = 1, Disable Write Precomp 



TYPE IV COMMANDS 



I3-I0 Interrupt Condition (Bits 3-0) 



In = 



I1 = 



'2 = 
I3 = 
l3-lo 



Not Used (WD1 770-00, WD1 772-00) 
Not Ready to Ready Transition (WD1773<X)) 
Not Used (WD1 770-00, WD1 772-00) 
Ready to Not Ready Transition (WD1 773-00) 
interrupt on Index Pulse 
Immediate Interrupt 
= Terminate without interrupt 



TYPE I COMMANDS 

The Type i Commands include the Restore, Seek, 
Step, Step-in, and Step-Out Commands. Each of the 
Type I Commands contains a rate field (ro,ri), which 
determines the stepping motor rate. 

A 4 fisec (MFM) or 8 fisec (FM) pulse is provided as 
an output to the drive. For every step pulse issued, 
the drive moves one track location in a direction deter- 
mined by the direction output. The chip steps the drive 
in the same direction it last stepped unless the com- 
mand changes the direction. 

The Direction signal is active high when stepping in 
and low when stepping out. The Direction signal is 
valid 24 f/sec before the first stepping pulse is 
generated. 

After the last directional step an additional *30 msec 
of head settling time takes place if the Verify flag is 
set in Type I Commands. There is also a *30 msec 
head settling time if the E flag is set in any Type II 
or III Command. 

When a Seek, Step or Restore Command is executed, 
an optional verification of Read/Write head position 
can be performed by setting bit 2 (V = 1) in the com- 
mand word to a logic 1. The verification operation 
begins at the end of the *30 msec settling time after 
the head is loaded against the media. The track 
number from the first encountered ID Field is com- 
pared against the contents of the Track Register. If 
the track numbers compare and the ID Field CRC is 
correct, the verify operation is complete and an INTRQ 
is generated with no errors. If there is a match but not 



1-6 



Floppy Disk Controller Devices 



a valid CRC, the CRC error status bit is set (Status 
Bit 3), and \he next encountered ID Field is read from 
the disk for the verification operation. 

The WD177X-00 finds an ID Field with correct track 
number and correct CRC within 5 revolutions of the 
media, or the seek error is set and an INTRQ Is 
generated. If V = 0, no verification is performed. 

On the WD1 770-00 and WD1 772-00 only, all com- 
mands, except the Force Interrupt Command, are pro- 



grammed via the h Flag to delay for spindle motor 
start up time. If the h Flag Is not set and the MO 
signal is low when a command is received, the 
WD1 770/2-00 forces MO to a logic 1 and waits 6 
revolutions before executing the command. At 300 
RPM, this guarantees a one second spindle start up 
time. If after finishing the command, the device 
remains idle for 9 revolutions, the MO signal goes 
back to a logic 0. If a command Is issued while MO 



:>< 

o 
o 




SET BUSY, RESET CRC, 
SEEK ERROR, DRQ, INTRQ 



SET MO 
WAIT 6 INDEX PULSES 




K 



YES 


SET 
DIRECTION 












YES 


RESET 
DIRECTION 






YES 








' 



FFhTOTR 




^ <<) 



^ 



^ 




SET DIRECTION 



ISSUE 
ONE STEP PULSE 



DELAY ACCORDING 
TO Ri.Rq FIELD 




^ 



TYPE I COMMAND FLOW 



TYPE I COMMAND FLOW 



Floppy Disk Controller Devices 



1-7 



O 
O 



is high, the command executes immediately, 
defeating the 6 revolution start up. This feature allows 
consecutive Read or Write commands without waiting 
for motor start up each time; the WD1 770/2-00 
assumes the spindle motor is up to speed. 

RESTORE (SEEK TRACK 0) 

Upon receipt of this co mman d, the Track 00 
(TROO) input is sampled. If TROO is active low 
indicating the Read/Write head is positioned over 
track 0, the Track Register is loade d with zeroes and 
an interrupt is generated. If TROO is not active low, 
stepping pulses at a rate specified by the t-^Jq field 
are issued until the TROO input is activated. 

At this time, the Track Register is loa ded wi th zeroes 
and an interrupt is generated. If the TROO input 
does not go active low after 255 stepping pulses, the 
WD177X-00 terminates operation, interrupts, and sets 
the Seek Error status bit, providing the V flag is set. 



VERIFY 
SEQUENCE 




INTRO RESET BUSY 



I) 



INTRQ, RESET BUSY 
SET SEEK ERROR 



; 



RESET 
CRC 



(INTRQ A 

RESET BUSY J' 



TYPE I COMMAND FLOW 



A verification operation also takes place if the V flag 
is set. The h bit allows the Motor On option at the 
start of a command. 

SEEK 

This command assumes that the Track Register con- 
tains the track number of the current position of the 
Read/Write head and the Data Register contains the 
desired track number. The WD177X-00 updates the 
Track Register and Issues stepping pulses in the 
appropriate direction until the contents of the Track 
Register are equal to the contents of the Data 
Register (the desired track location). A verification 
operation takes place if the V flag is on. The h bit 
allows the Motor On option at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. Note: When using multiple drives, the 
Track Register is updated for the drive selected before 
seeks are issued. 

STEP 

Upon receipt of this command, the WD177X-00 issues 
one Stepping Pulse to the disk drive. The stepping 
motor direction is the same as in the previous step 
command. After a delay determined by the t-^Jq field, 
a verification takes place if the V flag is on. If the U 
flag is on, the Track Register is updated. The h bit 
allows the Motor On option at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. 

STEP-IN 

Upon receipt of this command, the WD177X-00 issues 
one Stepping Pulse in the direction towards track 76. 
If the U flag is on, the Track Register is incremented 
by one. After a delay determined by the t-^Jq field, a 
verification takes place if the V flag is on. The h bit 
allows the Motor On option at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. 

STEP-OUT 

Upon receipt of this command, the WD177X-00 issues 
one stepping pulse in the direction towards track 0. 
If theU flag is on, the Track Register is decremented 
by one. After delay determined by the r^ro field, a 
verification takes place if the V flag is on. The h bit 
allows the Motor On option at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. 

TYPE II COMMANDS 

The Type II Commands are the Read Sector and Write 
Sector commands. Prior to loading the Type II Com- 
mand into the Command Register, the computer 
loads the Sector Register with the desired sector 
number. Upon receipt of the Type II command, the 
Busy Status bit is set. If the E flag =: 1 the command 
executes after a 30 msec delay. 

When an ID field is located on the disk, the 
WD177X-00 compares the Track Number on the ID 
field with the Track Register. If there is not a match, 
the next encountered ID field is read and a com- 
parison is again made. If there is a match, the Sec- 



1-8 



Floppy Disk Controller Devices 




SET BUSY, RESET DRQ, LOST 

DATA, RECORD NOT FOUND, & 

STATUS BITS5& 6 INTRO 




SET MO 

WAIT 

6 INDEX PULSES 




TYPE II COMMAND 

tor Number of the ID field is compared with the 
Sector Register. If there is no Sector match, the next 
encountered ID field is read off the disk and com- 
parisons again made. If the ID field CRC is correct, 
the data field is located and is either written into, or 
read from, depending upon the command. The 
WD177X-00 finds an ID field with a Track number, Sec- 
tor number, and CRC within four revolutions of the 
disk, or, the Record Not Found Status bit is set (Status 
Bit 4) and the command is terminated with an INTRQ. 



Each of the Type II Commands contains an m flag 
which determines if multiple records (sectors) are read 
or written, depending upon the command. If m = 0, 
a single sector is read or written and an interrupt is 
generated at the completion of the command. If m 
= 1, multiple records are read or written with the Sec- 
tor Register internally updated so that an address 
verification occurs on the next record. The WD177X-00 
continues to read or write multiple records and 
updates the Sector Register in numerical ascending 
sequence until the Sector Register exceeds the 
number of sectors on the track or until the Force Inter- 
rupt Command is loaded into the Command Register, 
which terminates the command and generates an 
interrupt. 

For example: If the WD177X-00 is instructed to read 
sector 27 and there are only 26 on the track, the Sec- 
tor Register exceeds the number available. The 
WD177X-00 searches for 5 disk revolutions, interrupts 
out, resets Busy, and sets the Record Not Found 
Status Bit. 

READ SECTOR 

Upon receipt of the Read Sector Command, the Busy 
Status Bit is set, then when an ID field is encountered 
that has the correct track number, correct sector 
number, and correct CRC, the data field is presented 
to the computer. The Data Address Mark of the data 
field is found with 30 bytes in single density and 43 
bytes in double density of the last ID field CRC byte. 
If not, the ID field is searched for and verified again 
followed by the Data Address Mark search. If, after 
five revolutions the DAM is not found, the Record Not 
Found Status Bit is set and the operation is ter- 
minated. When the first character or byte of the data 
field is shifted through the DSR, it Is transferred to 
the DR, and DRQ is generated. When the next byte 
is accumulated in the DSR, it is transferred to the DR 
and another DRQ is generated. If the computer has 
not read the previous contents of the DR before a new 
character is transferred that character is lost and the 
Lost Data Status Bit is set. This sequence continues 
until the complete data field Is inputted to the com- 
puter. If there is a CRC error at the end of the data 
field, the CRC Error Status bit is set, and the com- 
mand is terminated (even if it is a multiple record 
command). 

At the end of the Read operation, the type of Data 
Address Mark encountered in the data field is 
recorded in the Status Register (Bit 5) as shown: 



STATUS BIT 5 



Deleted Data Mark 
Data Mark 



WRITE SECTOR 

Upon receipt of the Write Sector Command, the Busy 
Status Bit is set. When an ID field is encountered that 
has the correct track number, correct sector number, 
and correct CRC, a DRQ is generated. The WD177X-00 
counts off 11 bytes in single density and 22 bytes in 
double density from the CRC field and the WG 



O 

.^ 
■>J 

o 
o 



Floppy Disk Controller Devices 



1-9 



o 

X 




INTRQ, RESET BUSY 
SET RECORD-NOT FOUN 



5 



BRING IN SECTOR LENGTH FIELD 

STORE LENGTH IN INTERNAL 

REGISTER 



SET CRC 
STATUS ERROR 




RESET 
CRC 




TYPE II COMMAND 



output is made active if the DRQ is serviced (i.e., the 
DR is loaded by the computer). If DRQ is not serviced, 
the command Is terminated and the Lost Data Status 
Bit is set. If the DRQ is serviced, the WG is made 
active and six bytes of zeroes In single density and 
12 bytes in double density are written on the disk. The 
Data Address Marl< is then written on the disk as de- 
termined by the ao field of the command as shown: 



DATA ADDRESS MARK (BIT 0) 



Deleted Data Mark 
Data Mark 



The WD177X-00 writes the data field and generates 
DRQ's to the computer. If the DRQ is not serviced 
in time for continuous writing the Lost Data Status 



1-10 



Floppy Disk Controller Devices 




READ SECTOR 
SEQUENCE 



PUT RECORD TYPE IN 
STATUS REG BIT 5 



c 



INTRQ, RESET BUSY 
SETCRC ERROR 



) 



+ 1 TO 
SECTOR REG 



^ 




^^ 



NTRQ RESET BUSY 







TYPE II COMMAND 



Floppy Disk Controller Devices 



1-11 




SEQUENCE 



DELAY 2 BYTES OF GAP 



DELAY 9 BYTES OF GAP 



INTRO, RESET BUSY 
SET LOST DATA 




) 



DELAY 1 BYTE OF GAP 



TURN ON WG & WRITE 
6 BYTES OF ZEROES 



DELAY 11 BYTES 



WRITE DATA AM 

ACCORDING TO Aq FIELD 

OF WRITE COMMAND 



TURN ON WG & WRITE 
12 BYTES OF ZEROES 



DRTO DSR, SET DRQ 



WRITE BYTE TO DISK 




NO 



SET DATA LOST 
WRITE BYTE 
OF ZEROES 



YES 



WRITE 1 BYTE OF FF 



TURN OFF WG 
I 




TYPE II COMMAND 



1-12 



Floppy Disk Controller Devices 



Bit is set and a byte of zeroes is written on the disk. 
The command is not terminated. After the last data 
byte is written on the disk, the two-byte CRC is com- 
puted internally and written on the disk followed by 
one byte of logic ones in FM or in MFM. The WG out- 
put is then deactivated. INTRQ sets 24 psec (MFM) 
after the last CRC byte is written. For partial sector 
writing, the proper method is to write data and fill the 
balance with zeroes. 

TYPE III COMMANDS 

Read Address 

Upon receipt of the Read Address Command, the 
Busy Status Bit is set. The next encountered ID field 
is then read in from the disk, and six data bytes of 
the ID field are assembled and transferred to the DR, 
and a DRQ is generated for each byte. The six bytes 
of the ID field are shown: 



TRACK 
ADDR 


SIDE 
NUMBER 


SECTOR 
ADDR 


SECTOR 
LENGTH 


CRC 

1 


CRC 
2 


1 


2 


3 


4 


5 


6 



Although the CRC characters are transferred to the 
computer, the WD177X-00 checks for validity and the 
CRC error status bit is set if there is a CRC error. The 
Track Address of the ID field is written into the sec- 
tor register so that a comparison can be made by the 
user. At the end of the operation an interrupt is 
generated and the Busy Status is reset. 

Read Track 

Upon receipt of the Read Track Command, the head 
is loaded and the Busy Status bit is set. Reading 
starts with the leading edge of the first encountered 
index pulse and continues until the next index pulse. 
All Gap, Header, and data bytes are assembled and 
transferred to the data register and DRQ's are 
generated for each byte. The accumulation of bytes 
is synchronized to each address mark encountered. 
An interrupt is generated at the completion of the 
command. 

This command has several characteristics which 
make it suitable for diagnostic purposes. They are: 
no CRC checking is performed; gap information is 



included in the data stream; and the Address Mark 
Detector is on for the duration of the command. 
Because the AM detector is always on, write splices 
or noise may cause the chip to look for an AM. 

The ID AM, ID field, ID CRC bytes, DAM, Data, and 
Data CRC Bytes for each sector are correct. The Gap 
Bytes may be read incorrectly during write-splice time 
because of synchronization. 

WRITE TRACK FORMATTING THE DISK 

(Refer to section on TYPE III commands for flow 
diagrams.) 

Data and gap information are provided at the com- 
puter interface. Formatting the disk is accomplished 
by positioning the R/W head over the desired track 
number and issuing the Write Track Command. 

Upon receipt of the Write Track Command, the Busy 
Status Bit is set. Writing starts with the leading edge 
of the first encountered Index Pulse and continues 
until the next Index Pulse, at which time the interrupt 
is activated. The Data Request is activated 
immediately upon receiving the command, but writing 
does not start until after the first byte is loaded into 
the Data Register. If the DR is not loaded within three 
byte times, the operation is terminated making the 
device Not Busy, the Lost Data Status Bit is set, and 
the interrupt is activated. If a byte is not present in 
the DR when needed, a byte of zeroes is substituted. 

This sequence continues from one Index Pulse to the 
next. Normally whatever data pattern appears in the 
Data Register is written on the disk with a normal 
clock pattern. However, if the WD177X-00 detects a 
data pattern of F5 through FE in the Data Register, 
this is interpreted as Data Address Marks with miss- 
ing clocks or CRC generation. 

The CRC generator is initialized when any data byte 
from F8 to FE is transferred from the DR to the DSR 
in FM or by receipt of F5 in MFM. An F7 pattern 
generates two CRC characters in FM or MFM. As a 
consequence, the patterns F5 through FE do not 
appear in the gaps, data field, or ID fields. Also, CRC's 
are generated by an F7 pattern. 

Disks are formatted in IBM 3740 or System 34 formats 
with sector lengths of 128, 256, 512, or 1024 bytes. 



a 

X 

I 

o 
o 



DATA PATTERN 
' IN DR (HEX) 






IN FM (DDEN = 1) 


IN MFM (DDEN = 0) 


00 thru F4 


Write 00 thru F4 with CLK = FF 


Write 00 thru F4, in MFM 


F5 


Not Allowed 


Write A1* in MFM, Present CRC 


F6 


Not Allowed 


Write C2** in MFM 


F7 


Generate 2 CRC bytes 


Generate 2 CRC bytes 


F8 thru FB 


Write F8 thru FB, CLK = C7, Preset CRC 


Write F8 thru FB, in MFM 


FC 


Write FC with CLK = D7 


Write FC in MFM 


FD 


Write FD with CLK = FF 


Write FD in MFM 


FE 


Write FE, CLK = C7, Preset CRC 


Write FE in MFM 


FF 


Write FF with CLK = FF 


Write FF in MFM 



"Missing clock transition between bits 4 and 5. 
'Missing clock transition between bits 3 and 4. 



Floppy Disk Controller Devices 



1-13 




SET BUSY, RESET DRQ, 

LOST DATA STATUS 

BITS 4, 5 



SET MO 




DELAY 6 
INDEX PULSES 



{ INTRQ RESET 
\BUSY SET WPRT 



DELAY 3 BYTE 
TIMES 



SET INTRQ 
LOST DATA 
RESET BUSY 




SET DRQ 



^ 




TYPE III COMMAND WRITE TRACK 



M4 



Floppy Disk Controller Devices 

















1 




YES(MFM) 


^ DDEN ^S 










^NO(FM) 




y^ DOES^S. ' 
<' DSR = F7 ^ 


fES 


WRITE 2 ORG 
CHARS. CLK = FF 










\ 


^fNO 




^"^DOES^V. 

<r DSR = FC >■ 


KES 


WRITE FC 
CLK = D7 






^Tno 




/^DOEs\. YES 

<^DSR = FD, FE/S- ^ 

\. OR F8-FB/^ 


WRITE FD, FE OR 
F8F9, CLK = C7 
INITIALIZE CRC 




^NO 






WRITE DSR 
CLK = FF 










YES 


5 ^^ PHYS^\ 
<C INDEX MARK> 


i 


f INTRO RESET \ 
y^ BUSY / 




Y NO 




YES 


./^HAS^S. 
X^ DR BEEN ^ 
\. LOADED^/^ 


NO 


WRITE 
BYTE OF ZEROES 
SET DATA LOST 


, 1 








K') 






N/ 




JL 


^/^ DOES ^\ "^ES^^ 
S. DSR = F5 v^ ^ 


WRITE A1 IN MFM 

WITH MISSING 

CLOCK INITIALIZE 

CRC 












^^0 




^^DOES^S^ 

C DSR = F6 >■ 


YES 


WRITE 02 IN MFM 

WITH MISSING 

CLOCK 






^^0 




v^DOES^X. YES 
<r DSR - FF ■> » 


WRITE 2 CRC 
CHARS. 




^NO 






WRITE DSR 
IN MFM 

























o 

o 
o 



TYPE III COMMAND WRITE TRACK 



Floppy Disk Controller Devices 



1-15 



:>< 

o 
o 



TYPE IV COMMANDS 

The Forced Interrupt Command is used to terminate 
a multiple sector read or write command or to insure 
Type I status In the Status Register. This command 
is loaded Into the Command Register at any time. If 
there Is a current command under execution (Busy 
Status Bit set) the command is terminated and the 
Busy Status Bit reset. 

The lower four bits of the command determine the 
conditional interrupt as follows: 

lo = Not used (WD1 770-00, WD1 772-00), Not Ready 
To Ready Transition (WD1 773-00) 

li = Not Used (WD1 770-00, WD1 772-00), Ready To 
Not Ready Transition (WD1 773-00) 

12 = Every Index Pulse 

13 = Immediate Interrupt 

The conditional interrupt is enabled when the cor- 
responding bit positions of the command (I3-I0) are 
set to a 1. When the condition for interrupt is met the 
INTRQ line goes high signifying that the condition 
specified has occurred. If I3-I0 are all set to zero (Hex 
DO), no interrupt occurs but any command presently 
under execution is immediately terminated. When us- 
ing the immediate interrupt condition (I3 = 1) an in- 
terrupt is immediately generated and the current 
command terminated. Reading the status or writing 
to the Command Register does not automatically 
clear the interrupt. The Hex DO is the only command 
that enables the immediate interrupt (Hex D8) to clear 
on a subsequent load Command Register or Read 
Status Register operation. Follow a Hex D8 with DO 
command. 

Wait 16 /isec (double density) or 32 i^sec (single den- 
sity) before issuing a new command after issuing a 
forced interrupt. Loading a new command sooner 
than this nullifies the forced interrupt. 

Forced interrupt stops any command at the end of 
an internal micro-Instruction and generates INTRQ 
when the specified condition is met. Forced interrupt 
waits until ALU operations in progress are complete 
(CRC calculations, compares, etc.). 

Status Register 

Upon receipt of any command, except the Force Inter- 
rupt Command, the Busy Status Bit is set and the rest 
of the status bits are updated or cleared for the new 
command. If the Force Interrupt Command is received 
when there is a current command under execution, 
the Busy Status Bit is reset, and the rest of the status 
bits are unchanged. If the Force Interrupt Command 
is received when there is not a current command 
under execution, the Busy Status Bit is reset and the 
rest of the status bits are updated or cleared. In this 
case. Status reflects the Type I commands. 

The user has the option of reading the Status Register 
through program control or using the DRQ line with 
DMA or interrupt methods. When the Data Register 
is read the DRQ bit in the Status Register and the 
DRQ line are automatically reset. A write to the Data 
Register also causes both DRQ's to reset. 



The Busy Bit In the status may be monitored with a 
user program to determine when a command Is com- 
plete, in lieu of using the INTRQ line. When using the 
INTRQ, a Busy Status check is not recommended 
because a read of the Status Register to determine 
the condition of busy resets the INTRQ line. 

The format of the Status Register is shown below: 



(BITS) 


7 


6 


5 


4 


3 


2 


1 





S7 


S6 


S5 


S4 


S3 


S2 


SI 


SO 



Because of internal sync cycles, certain time delays 
are observed when operating under programmed I/O, 
as shown. 



Operation 


Next Operation 


Delay Req'd. 
FM MFM 


Write to 
Command Reg. 


Read Busy Bit 
(Status Bit 0) 


48jusec 


24^sec 


Write to 
Command Reg. 


Read Status 
Bits 1-7 


64pjsec 


32fisec 


Write 
Register 


Read Same 
Register 


32/iSec 


16/isec 



RECOMMENDED - 128 BYTES/SECTOR 

The recommended single-density format with 128 
bytes/sector is shown. In order to format a disl<ette, 
the user issues the Write Traclc Command, and loads 
the Data Register with the following values. For every 
byte to be written, there is one Data Request. 



NUMBER 




OF BYTES 


HEX VALUE OF BYTE WRITTEN 




40 
6 


FF (or 00) 
00 




1 
1 


FE (ID Address Marl<) 
Track Number 




1 
1 
1 
1 
11 
6 


Side Number (00 or 01) 
Sector Number (1 thru 10) 
00 (Sector Length) 
F7 (2 CRC's written) 
FF (or 00) 
00 




1 
128 

1 

10 

369** 


FB (Data Address IVIark) 
Data (IBM uses E5) 
F7 (2 CRC's written) 
FF (or 00) 
FF (or 00) 



'Write bracketed field 16 times. 
'Continue writing until WD177X-00 interrupts out. 
Approx. 369 bytes. 



1-16 



Floppy Disk Controller Devices 



I 



I 

o 

CD 

CD 
CO 



INDEX 
PULSE. 



40 BYTES 
'FF' 



REPEATED 
-FOR EACH SECTOR- 



6 BYTES 
•00' 



ID 
•FE' 



TRACK 



SIDE 

n 



SECTOR 



CRC 
2 



11 BYTES 
•FF- 



6 BYTES 
•00' 



DATA 
ADR 
MARK 



USER DATA 
128 BYTES 



CRC 
2 



10 BYTES 
■FF' 



WRITE GATE- 



SINGLE DENSITY FORMAT 



INDEX 
PULSE. 





^ 
















REACHSECTOF 






































/ 


60 BYTES 
*4E' 


12 BYTES 
•OO' 


3 BYTES 
•AT 


ID 
■FE' 


TRACK 

# 


SIDE 

# 


SECTOR 


LENGTH 


CRC 

1 


CRC 
2 


22 BYTES 
•4E' 


12 BYTES 
■GO' 


3 BYTES 
■A1' 


ID 
■FB' 


USER DATA 
256 BYTES 


CRC 

1 


CRC 
2 


24 BYTES 
■4E 


/ 














ID FIELD 1 










DATA FIELD 









WRITE GATE - 



DOUBLE DENSITY FORMAT 



oo-xzzi-aM 



256 BYTES/SECTOR 

Shown below is the recommended dual-density for- 
mat with 256 bytes/sector. In order to format a 
diskette the user issues the Write Track Command 
and loads the Data Register with the following values. 
For every byte to be written, there is one data request. 



NUMBER 




OF BYTES 


HEX VALUE OF BYTE WRITTEN 


60 


4E 




12 


00 




3 

1 
1 
1 
1 
1 
1 
22 


F5 (Writes A1) 
FE (ID Address Mark) 
Track Number (0 thru 4C) 
Side Number (0 or 1) 
Sector Number (1 thru 10) 
01 (Sector Length) 
F7 (2 CRC's written) 
4E 




12 


00 




3 

1 

256 


F5 (Writes A1) 

FB (Data Address Mark) 

DATA 




1 
24 


F7 (Data Address Mark) 
4E 


668** 


4E 



'Write bracketed field 16 times. 
'Continue Writing until WD177X-00 interrupts out. 
Approx. 668 bytes. 



1. Non-StandarcJ Formats 

Variations in the recommended formats are possible 
to a limited extent if the following requirements are 
met: 

1) Sector size must be 128, 256, 512 of 1024 bytes. 

2) Gap 2 cannot be varied from the recommended 
format. 

3) 3 bytes of A1 must be used in MFM. 

In addition, the Index Address Mark is not required 
for operation by the WD177X-00. Gap 1, 3 and 4 
lengths are as short as 2 bytes for WD177X-00 opera- 
tion, however PLL lock up time, motor speed varia- 
tion, write-splice area, etc. adds more bytes to each 
gap to achieve proper operation. For highest system 
reliability use the recommended format. 





FM 


MFM 


Gap 1 


16 bytes FF 


32 bytes 4E 


Gap II 


11 bytes FF 


22 bytes 4E 


* 


6 bytes 00 


12 bytes 00 


* 




3 bytes A1 


Gap III** 


10 bytes FF 


24 bytes 4E 




4 bytes 00 


8 bytes 00 
3 bytes A1 


Gap IV 


16 bytes FF 


16 bytes 4E 



*Byte counts must be exact. 
'Byte counts are minimum, except exactly 3 bytes 
of A1 must be written. 



STATUS REGISTER DESCRIPTION (WD1770-00 and WD1772-00 only) 



BIT NAME 


MEANING 


S7 MOTOR ON 


This bit reflects the status of the Motor On output. 


S6 WRITE PROTECT 


On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates 
a Write Protect. This bit is reset when updated. 


S5 RECORD 
TYPE/SPIN-UP 


When set, this bit Indicates that the Motor Spin-Up sequence has completed 
(6 revolutions) on Type 1 commands. Type 2 & 3 commands, this bit indicates 
record Type. = Data Mark. 1 = Deleted Data Mark. 


S4 RECORD NOT 
FOUND (RNF) 


When set, it indicates that the desired track, sector, or side were not found. This 
bit is reset when updated. 


S3 CRC ERROR 


If S4 is set, an error is found in one or more ID fields; otherwise it indicates 
error data field. This bit is reset when updated. 


S2 LOST DATA/ 
BYTE 


When set, it indicates the computer did not respond to DRQ in one byte time. 
This bit is reset to zero when updated. On Type 1 commands, this bit reflects the 
status of the TROO signal. 


SI DATA REQUEST 
INDEX 


This bit is a copy of the DRQ output. When set, it indicates the DR is full on a 
Read Operation or the DR is empty on a Write operation. This bit is reset to zero 
when updated. On Type 1 commands, this bit indicates the status of the IP 
signal. 


SO BUSY 


When set, command is under execution. When reset, no command is under 
execution. 



1-18 



Floppy Disk Controller Devices 



STATUS REGISTER SUMMARY (WD1773-00 only) 





ALL TYPE 1 


READ 


READ 


READ 


WRITE 


WRITE 


BIT 


COMMANDS 


ADDRESS 


SECTOR 


TRACK 


SECTOR 


TRACK 


S7 


NOT READY 


NOT READY 


NOT READY 


NOT READY 


NOT READY 


NOT READY 


S6 


WRITE 
PROTECT 











WRITE 
PROTECT 


WRITE 
PROTECT 


S5 


HEAD LOADED 





RECORD TYPE 





WRITE FAULT 


WRITE FAULT 


S4 


SEEK ERROR 


RNF 


RNF 





RNF 





S3 


ORG ERROR 


CRC ERROR 


CRC ERROR 





CRC ERROR 





S2 


TRACK 


LOST DATA 


LOST DATA 


LOST DATA 


LOST DATA 


LOST DATA 


S1 


INDEX PULSE 


DRQ 


DRQ 


DRQ 


DRQ 


DRQ 


SO 


BUSY 


BUSY 


BUSY 


BUSY 


BUSY 


BUSY 



STATUS FOR TYPE I COMMANDS (WD1 773-00 only) 



BIT NAME 


MEANING 


S7 NOT READY 


This bit when set indicates the drive is not ready. When reset it indicates that the 
drive is ready. This bit is an inverted copy of the Ready input and logically "ORed" 
with MR. 


S6 PROTECTED 


When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT 
input. 


S5 HEAD LOADED 


When set, it indicates the head is loaded and engaged. This bit is a logical "and" 
of HLD and HLT signals. 


S4 SEEK ERROR 


When set, the desired track was not verified. This bit is reset to when updated. 


S3 CRC ERROR 


CRC encountered in ID field. 


S2 TRACK 00 


When set, indicates Read/Write head is positioned to Track 0. This bit is an inverted 
copy of the TROO input. 


S1 INDEX 


When, set, indicates index mark detected from drive. This bit is an inverted copy of 
the IP input. 


SO BUSY 


When set, command is in progress. When reset no command is in progress. 



STATUS FOR TYPE II AND III COMMANDS (WD1773-00 ONLY) 



BIT NAME 


MEANING 


S7 NOT READY 


This bit when set indicates the drive is not ready. When reset, it indicates that the 
drive is ready. This bit is an inverted copy of the Ready input and "ORed" with MR. 
The Type II and III Commands will not execute unless the drive is ready. 


S6 WRITE PROTECT 


On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a 
Write Protect. This bit is reset when updated. 


S5 RECORD TYPE 


On Read Record: It indicates the record-type code from data field address mark. 
1 = Deleted Data Mark. = Data Mark. On any Write: Forced to a Zero. 


S4 RECORD NOT 
FOUND (RNF) 


When set, it indicates that the desire track, sector, or side were not found. This bit 
is reset when updated. 


S3 CRC ERROR 


If S4 is set, an error is found in one or more ID fields; otherwise it indicates error 
in data field. This bit is reset when updated. 


S2 LOST DATA 


When set, it indicates the computer did not respond to DRQ in one byte time. This 
bit is reset to zero when updated. 


SI DATA REQUEST 


This bit is a copy of the DRQ output. When set, it indicates the DR is full on a Read 
Operation or the DR is empty on a Write operation. This bit is reset to zero when 
updated. 


SO BUSY 


When set, command is under execution. When reset, no command is under execution. 



Floppy Disk Controller Devices 



1-19 



■>! 

O 
O 



DC ELECTRICAL CHARACTERISTICS 

MAXIMUM RATINGS 

Storage Temperature 55°C (67°F) to 

+ 125°C(257°F) 
Operating Temperature 0°C (32°F) to 

70°C (158°F) Ambient 
Maximum Voltage to Any Input 

with Respect to Vss + 7V to -0.5V 



NOTE 

Maximum limits indicate where permanent device 
damage occurs. Continuous operation at these limits 
is not intended and should be limited to those con- 
ditions specified in the DC Operating Characteristics. 



DC OPERATING CHARACTERISTICS 

TA = 0°C(32°F) to 70°C (158°F), Vgs = OV, Vqc = +5V ± .25V 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


UNITS 


CONDITIONS 


l|L 


Input Leakage 




10 


mA 


V|N = Vcc 


loL 


Output Leakage 




10 


mA 


Vqut - Vcc 


V|H 


Input High Voltage 


2.0 




V 




V,H 


Input Low Voltage 




0.8 


V 




VOH 


Output High Voltage 


2.4 




V 


lo = -100 ^A 


Vol 


Output Low Voltage 




0.40 


V 


Iq = 1.6 mA 


Pd 


Power Dissipation 




.75 


w 




F^PU 


Internal Pull-Up 


100 


1700 


mA 


V|N = OV 


'cc 


Supply Current 


75CTyp) 


150 


mA 





AC TIMING CHARACTERISTICS 

TA = 0°C (320F) to 70°C (158°F), ^SS = OV, ^CC = -f 5V ± .25V 




READ ENABLE TIMING 
READ ENABLE TIMING - RE SUCh that: R/W = 1, CS = 0. 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNITS 


CONDITIONS 


Ire 


RE Pulse Width of CS 


200 






nsec 


Cl= 50 pf 


^DRR 


DRQ Reset from RE 




200 


300 


nsec 




^DV 


Data Valid from RE 




100 


200 


nsec 


Cl= 50 pf 


boH 


Data Hold from RE 
INTRO Reset from RE 


20 




150 
8 


nsec 
/isec 


Cl= 50 pf 



Note: DRQ and INTRO reset are from rising edge (lagging) of RE, whereas resets are from falling edge 
(leading) of WE. Worst case service time for DRQ is 23.5 /i/sec for MFM and 47.5 \xsec for FM. 



1-20 



Floppy Disk Controller Devices 



1 


DALS 
0-7 


X 


VALID 


X 






■< 

— 'WE — 






DH 


-*■ 










CS 




r- 


_y 




'SET ^ 




^ — 




— »> 






— 'hld 


R/W 
AO.AI 


\ 

'AS ^ 

X 


\ 


i^ 








■^ — 




'ah »• 




■^ 










X 














DRQ 


-« 'DRW 


— «\ 









o 
o 



WRITE ENABLE TIMING 



WRITE ENABLE TIMING - WE such that: R/W = 0, CS = 0. 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNITS 


CONDITIONS 


tAS 


Setup ADDR to CS 


50 






nsec 




^SET 


Setup R/W to CS 









nsec 




tAH 


Hold ADDR from CS 


10 






nsec 




^HLD 


Hold R/W from CS 









nsec 




^WE 


WE Pulse Width 


200 






nsec 




^DRW 


DRQ Reset from WE 




100 


200 


nsec 




^DS 


Data Setup to WE 


150 






nsec 




^H 


Data Hold from WE 
INTRQ Reset from WE 







8 


nsec 
;isec 





READ DATA TIMING: 



CHARACTERISTIC 


MIN 


TYP 


MAX 


UNITS 


CONDITIONS 




.200 

.400 

3 




3 
3 


/isec 
fisec 


MFM 
FM 


Raw Read Pulse Width 


Raw Read Cycle Time 



Floppy Disk Controller Devices 



1-21 



WRITE DATA TIMING: 



a 
x 

o 

o 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNITS 


CONDITIONS 




Write Gate to Write Data 




4 
2 




fisec 
fisec 


FM 
MFM 




Write Data Cycle Time 




4,6,8 




/isec 






Write Gate off from WD 




4 
2 




Atsec 
iisec 


FM 
MFM 


twp 


Write Data Pulse Width 




820 
690 
570 
1.38 




nsec 
nsec 
nsec 
ixsec 


Early MFM 

Nominal MFM 

Late MFM 

FM 



CLK 




LATE twP 



WRITE DATA TIMING 



1-22 



Floppy Disk Controller Devices 



VIH 



MR 



t|p »J 



■ 'MR 



VIH 



CLK 



I-*- 'CYC -J 

LTL 



-•H 'CD 



k 



'CD? 



DIRC 



STEP 



STEP IN 



R1R0* 



^ 



L_tD|R-»J 'STpV^ J'STP N^ j-<-'DIR— ►I'SPtI- 



^ 



f 



:>< 

o 
o 



MISCELLANEOUS TIMING 



MISCELLANEOUS TIMING: 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNITS 


CONDITIONS 


tcD1 


Clock Duty (low) 


50 


67 




nsec 




^CD2 


CLock Duty (high) 


50 


67 




nsec 




^STP 


Step Pulse Output 




4 
8 




/isec 


MFM 
FM 


^DIR 


Dir Setup to Step 




24 
48 




f/sec 


MFM 
FM 


^MR 


Master Reset Pulse Width 


50 






usee 




t|P 


Index Pulse Width 


20 






fisec 





Floppy Disk Controller Devices 



1-23 



1-24 Floppy Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD177X-00 Floppy Disk Formatter/Controller Family 

Application Notes 



INTRODUCTION 

To meet the demand for a low cost compact LSI Flop- 
py Disk Controller device, Western Digital has 
developed the WD177X-00. The WD177X-00 is a NMOS 
Floppy Disk Controller device that incorporates the 
FD179X, a digital data separator and write 
precompensation circuitry all in a single chip. The 
device offers soft sector formatting, selectable step- 
ping rates, automatic track seek with verify, and 
variable sector lengths. The FD177X-00 comes in a 
28-pin dual-in-line package or quad pack and operates 
from a single 5 volt only power supply. 

APPLICATIONS 

The Mini-Floppy Controller is targeted for the low cost 
sector of the disk drive market, where digital data 
separation is preferred over analog phase lock loop. 
Included in this market are Personal Computers, Por- 
table Computers and Small Business Computers. 

FOLLOW ON DEVICES 

WD1 772-02 

The device is the same as the WD1 772-00 except for 
an enhanced digital data separator. 

HOST INTERFACING 

Interfacing to a Host processor is accomplished 
through the eight bit bi-directional Data Access Lines 
(DAL) and associated control lines. The DAL is used 
to transfer data, status and control words out of or 
into WD177X-00. The DAL having three states enabled 
as an output when Chip Select (CS) is active low and 
Read/Write (R/W) is high or as input receiver when CS 
and R/W is low. When transfer of data with the device 
Is required by the Host CS is made low. The address 
bits AO and A1 combined with the R/W line select the 
register and the direction of data. 



During Direct Memory Access (DMA) data transfers 
between the WD177X-00 and Host Memory, the Data 
Request (DRQ) line is used in Data Transfer Control. 
This signal also appears as status bit 1 during 
Read/Write operations. On Disk Read operations the 
DRQ is active when an assembled byte is present in 
the Data Register, then reset when read by the Host. 
If the Host fails to read the Data Register before the 
following byte is assembled in the Data Register, the 
lost data bit is set in Status Register. 

At the completion of every command INTRQ is 
asserted. INTRQ is de-asserted by either reading the 
status or by loading the Command Register. 

DISKETTE DRIVE INTERFACING 

The WD177X-00 has two modes of operation depend- 
ing on the state of DDEN, regardless of the state of 
DDEN the CLK input remains at 8 MHz. Disk Reads 
with sector lengths of 128, 256, 512 and 1024 byte sec- 
tor in both FM or MFM diskettes is accomplished via 
the internal digital data separator. Disk Write opera- 
tion in MFM on inner tracks may require write 
precompensation. Write precompensation is enabl- 
ed when bit 1 = 0, in the Write command and a 
precompensation value of 125 nsec is produced. 

The diskettes spindle motor is controlled by bit 3 of 
any Type I, II or III command, upon receiving a com- 
mand with bit 3 = 0, the spin up sequence is 
enabled. 
GENERAL INFORMATION 

A 4-5 volt supply ±5% is used as Vqc. and the 
clock input requires a free running 50% duty cycle 
at 8 MHz ±0.1%. 



O 



O 
O 



Floppy Disk Controller Devices 



1-25 



1-26 Floppy Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 



WD1772-02 Floppy Disk Formatter/Controller 



FEATURES 

28 PIN DIP 

SINGLE 5V SUPPLY 

HIGH PERFORMANCE DPLL BUILT-IN DIGITAL DATA 
SEPARATOR 

BUILT-IN WRITE PRECOMPENSATION, 
INCREASED TO 187 MS 

SINGLE AND DOUBLE DENSITY 

MOTOR CONTROL 

128, 256, 512 OR 1024 SECTOR LENGTHS 

TTL COMPATIBLE 

8-BIT BI-DIRECTIONAL DATA BUS 

100% PIN COMPATIBLE WITH WD1770-00 AND 
WD1 772-00 

ENHANCED STEP/RATES 2,3,6,12 MS 



CS 1 


1. ^ 


28 


1 INTRQ 


H/W 1 


2 


27 


— 1 DRQ 


AO I 


3 


26 


_) DDEN 


A1 CZ 


4 


25 


; 1 WPRT 


DALO 1 


5 


24 


znip" 


DAL1 1 


6 


23 


1 TROD 


DAL2 1 


7 


22 ZD WD 


DAL3 CZ 


8 


21 ZD WG 


DAL4 ( 


9 


20 m MO 


DAL5 I 


10 


19 ZD RD 


DAL6 1 


11 


18 ZD CLK 


DAL7 I ■ 


12 


17 


ZD DIRC 


MR 1 


13 


16 


IZI STEP 


GND 1 


14 


15 


=] Vcc 



lO 
I 

o 



PIN DESIGNATION 



DESCRIPTION 

The WD1 772-02 Is a MOS/LSI device which performs 
the functions of a Floppy Disk Formatter/Controller. 
It is similar to its predecessor, the FD179X, but also 
contains a digital data separator and write 
precompensation circuitry. The drive side of the inter- 
face needs no additional logic except for buf- 
fers/receivers. Designed for single (FM) or double 
(MFM) density operation, the device contains a pro- 
grammable Motor On signal. 

The WD1 772-02 is implemented in NMOS silicon gate 
technology and is available in a 28 pin dual-in-line. 

The WD1 772-02 is a low cost version of the FD179X 
Floppy Disk Controller/Formatter. It is similar to the 
FD179X, but has a built-in digital data separator and 
write precompensation circuits. 



A single read line (RD, Pin 19) is the only input 
required to recover serial FM of MFM data from the 
disk drive. The device is designed for control of floppy 
disk drives with data rates of 125 KBits/Sec (single 
density) and 250 KBits/Sec (double density). In addi- 
tion, write precompensation of 187 nsec from nominal 
is enabled at any point through simple software com- 
mands. Another programmable feature, Motor On, 
enables the spindle motor automatically prior to 
operating a selected drive. 

The WD1772-02 offers stepping rates of 2, 3, 6 and 
12 msec. The processor interface consists of an 8-bit 
bi-directional bus for transfer of status, data, and com- 
mands. All Host communication with the drive occurs 
through these lines. They are capable of driving one 
standard TTL load or three LS loads. 



Floppy Disk Controller Devices 



1-27 



PIN 










NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


1 
2 


CS 

R/W 




1 

1 


A logic low on this input selects the chip and enables 
Host communication with the device. 

A loQic hiah on this input controls the placement of 
data on the D0-D7 lines from a selected register, while 
a logic low causes a write operation to a selected 
register. 


CHIP SELECT 


READ/WRITE 


3,4 


A0,A1 


ADDRESS 0,1 


1 


These two inputs select a register to Read/Write data: 
CS A1 AO R/W = 1 R/W = 

status Reg Command Reg 
1 Track Reg Track Reg 
1 Sector Reg Sector Reg 
1 1 Data Reg Data Reg 


5-12 


DAL0-DAL7 


DATA ACCESS 

LINES 

THROUGH 7 


I/O 


Eight-bit bi-directional bus used for transfer of data, 
cojTtrol, or status. This bus is enabled by CS and 
RA/V. Each line will drive one TTL load. 


13 


MR 


MASTER RESET 




A logic low pulse on this line resets the device and 
initializes the Status Register (internal pull-up). 


14 


GND 


GROUND 




Ground. 


15 


Vcc 


POWER SUPPLY 


1 


+ 5V±5% power supply Input. 


16 


STEP 


STEP 





The Step output contains a pulse for each step of the 
drive's R/W head. 


17 


DIRC 


DIRECTION 





The Direction output is high when stepping in towards 
the center of the diskette, and low when stepping out. 


18 
19 


CLK 
RD 


CLOCK 


1 
1 


This input requires a free-running 50% duty cycle clock 
(for internal timing) at 8 MHz ±0.1%. 

This active low input is the raw data line containing 
both clock and data pulses from the drive. 


READ DATA 


20 


MO 


MOTOR ON 





Active high output used to enable the spindle motor 
prior to read, write or stepping operations. 


21 


WG 


WRITE GATE 





This output is made valid prior to writing on the 
diskette. 


22 
23 


WD 
TROO 


WRITE DATA 


1 


FM or MFM clock and data pulses are placed on this 

line to be written on the diskette. 

This active low input informs the WD1772-02 that 


TRACK 00 


24 


IP 




1 


the drive's R/W heads are positioned over Track 

zero. 

This active low input informs the WD1 772-02 when the 

physical index hole has been encountered on the 


INDEX PULSE 


25 






1 


diskette. 

This input is sampled whenever a Write Command is 
received. A logic low on this line will prevent any Write 
Command from executing (internal pull-up). 


WPRT 


WRITE PROTECT 



1-28 



Floppy Disk Controller Devices 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


26 

27 
28 






1 





This input pin selects either single (FM) or double 
(MFM) density. When DDEN = 0, double density is 
selected (internal pull-up). 

This active high output indicates that the Data Register 
is full (on a Read) or empty (on a Write operation). 
This active high output is set at the completion of any 
command, is reset by a read of the Status Register. 


DDEN 

DRQ 
INTRQ 


DOUBLE 
DENSITY 
ENABLE 

DATA REQUEST 

INTERRUPT 
REQUEST 



to 

I 

o 

N3 







5V.- 

F 
L 

P 
P 
Y 

D 
R 

1 
V 

E 






WD 




< ^ 


WD177X 


IP 




Troo 




WPHT 




MO 




DIRC 




STEP 


gndVcc 




1 1 1 





J- DDEN ^ 



WD1 772-02 SYSTEM BLOCK DIAGRAM 

ARCHITECTURE 

The primary sections of the Floppy Disk Formatter are 
the parallel processor interface and the Floppy disk 
interface. 

Data Shift Register - This 8-bit register assembles 
serial data from the Read Data input (RD) during 
Read operations and transfers serial data to the Write 
Data output during Write operations. 

Data Register - This 8-bit register is used as a holding 
register during Disk Read and Write operations. In 
disk Read operations, the assembled data byte is 
transferred in parallel to the Data Register from the 
Data Shift Register. In Disk Write operations, infor- 
mation is transferred in parallel from the Data 
Register to the Data Shift Register. 

When executing the Seek Command, the Data 
Register holds the address of the desired Track posi- 
tion. This register is loaded from the DAL and gated 
onto the DAL under processor control. 

Track Register - This 8-bit register holds the track 
number of the current Read/Write head position. It 
is incremented by one every time the head is step- 



ped in and decremented by one when the head is 
stepped out (tov\/ards track 00). The contents of the 
register are compared v/ith the recorded track number 
in the ID field during disk Read, Write, and Verify 
operations. The Track Register can be loaded from 
or transferred to the DAL This Register is not loaded 
when the device is busy. 

Sector Register (SR) - This 8-bit register holds the 
address of the desired sector position. The contents 
of the register are compared with the recorded sec- 
tor number in the ID field during disk Read or Write 
operations. The Sector Register contents can be 
loaded from or transferred to the DAL. This register 
is not loaded when the device is busy. 

Command Register (CR) - This 8-bit register holds the 
command presently being executed. This register is 
not loaded when the device is busy unless the new 
command is a forced interrupt. The Command 
Register is loaded from the DAL, but not read onto 
the DAL. 

Status Register (STR) - This 8-bit register holds device 
Status information. The meaning of the Status bits 
is a function of the type of command previously 
executed. This register is read onto the DAL, but not 
loaded from the DAL. 

CRC Logic - This logic is used to check or to generate 
the 16-bit Cyclic Redundancy Check (CRC). The 
polynomial is: 



_ v16 



+ X^2 + x5 +1. 



G(x) 

The CRC includes all information starting with the 
address mark and up to the CRC characters. The CRC 
Register is preset to ones prior to data being shifted 
through the circuit. 

Arithmetic/Logic Unit (ALU) - The ALU is a serial com- 
parator, incrementer, and decrementer and is used 
for register modification and comparisons with the 
disk recorded ID field. 



Floppy Disk Controller Devices 



1-29 



ro 
■ 

o 

lO 



(DAL) 



DATA OUT 
BUFFERS 



DATA 
REG 



COMMAND 
REG 



DATA 
SHIFT 
REG 



SECTOR 
REG 



to 



AM DETECTOR 



CRC LOGIC 



TRACK 
REG 



to 



rn 



STATUS 
REG 



WRITE 
PRECOMP 



-< RD 



DATA 
SEPARATOR 



DRQ 


COMPUTER 
INTERFACE 
CONTROL 


CONTROL 


PLA 
CONTROL 
(240X19) 


CONTROL 


DISK 
INTERFACE 
CONTROL 




WG 


_ INTRQ 


_ WPRT 




MR ' _ 






C^ 


IP 








R/W 


TROO 








AO 






STEP 


*^ » 


DIRC _ 






(MOTOR ON) 


CLK {8-MHZ) _ 






OOEn 









FIGURE 1. WD1 772-02 BLOCK DIAGRAM 



Timing and Control - All computer and Floppy Disk 
interface controls are generated through this logic. 
The internal device timing is generated from an exter- 
nal crystal clock. The WD1 772-02 has two different 
modes of operation according to the state of 
DDEN. 

When DDEN = 0, double density (MFM) is enabled. 
When DDEN = 1, single density is enabled. 

AM Detector - The address mark detector detects ID, 
data, and index address marks during read and write 
operations. 

Data Separator - A digital phase lock loop (DPLL) of 
type 2, second order performs the data separator 
function. DPLL has a filter transfer function used to 
remove jitter effects thereby achieving adequate win- 
dow margin. The algorithm used gives performance 
equal to second order analog designs. 

DPLL performance specifications are as follows: 



Fc capture range ±6% (min) 

Tl lock response 4 bytes OOH (max) 

Wt window tolerance 50% for 10E-9 error rate 

PROCESSOR INTERFACE 

The interface to the processor is accomplished 
through the eight Data Access Lines (DAL) and 
associated control signals. The DAL are used to 
transfer Data, Status, and Control words out of, or 
into the WD1 772-02. The DAL are three state buffers 
thai are enabled as output drivers when CS and 
JfWJ =J are active or act as input receivers when CS 
and RW = are active. 

When transfer of data with the Floppy Disk Controller 
is required by the Host processor, the device address 
is decoded and CS is made low. The address bits A1 
and AO, combined with the signal RA/V during a 
Read operation or Write operation are interpreted as 
selecting the following registers: 



1-30 



Floppy Disk Controller Devices 



A1 - AO 


READ (R/W = 1) 


WRITE (R/W = 0) 




1 

1 

1 1 


Status Register 
Tracl< Register 
Sector Register 
Data Register 


Command Register 
Tracl< Register 
Sector Register 
Data Register 



After any register is written to, thie same register can- 
not be read from untii 16 fisec in MFM or 32 ^sec in 
FM have elapsed. 

During Direct Memory Access (DMA) types of data 
transfers between the Data Register of the WD1 772-02 
and the processor, the Data Request (DRQ) output 
is used in Data Transfer control. This signal also 
appears as status bit 1 during Read and Write 
operations. 

On Disk Read operations, the Data Request bit is ac- 
tivated (set high) when an assembled serial input byte 
is transferred in parallel to the Data Register. This bit 
is cleared when the Data Register is read by the pro- 
cessor. If the Data Register is read after one or more 
characters are lost, by having new data transferred 
into the register prior to processor readout, the Lost 
Data bit is set in the Status Register. The Read opera- 
tions continue until the end of sector is reached. 

On Disk Write operations, the Data Request bit is ac- 
tivated when the Data Register transfers its contents 
to the Data Shift Register, and requires a new data 
byte. It is reset when the Data Register is loaded with 
new data by the processor. If new data is not loaded 
at the time the next serial byte is required by the Flop- 
py Disk, a byte of zeroes is written on the diskette 
and the Lost Data bit set in the Status Register. 

At the completion of every command, an INTRO is 
generated. INTRO is reset by either reading the Status 
Register or by loading the Command Register with 
a new command. In addition, INTRO is generated if 
a Force Interrupt Command condition is met. 

The WD1 772-02 h as two modes of ope ration accor- 
ding to the state DDEN. When DDEN = 1, single 
density is selected. In either case, the CLK input is 
at 8 MHz. 

GENERAL DISK READ OPERATIONS 

Sector lengths of 128, 256, 512 or 1024 are obt ainable 
in either FM or MFM formats. For F M. DDE N 
is placed to logical 1. For MFM formats, DDEN is 
placed to a logical 0. Sector lengths are determined 
at format time by the fourth byte in the ID field. 



SECTOR LENGTH TABLE 



SECTOR LENGTH 
FIELD (HEX) 



NUMBER OF BYTES 
IN SECTOR (DECIMAL) 



00 
01 
02 
03 



128 
256 
512 
1024 



The number of sectors per track for the WD1 772-02 
are from to 244. The number of tracks for the 
WD1 772-02 are to 244. 

GENERAL DISK WRITE OPERATION 

When writing on the diskette, the WG output is ac- 
tivated, allowing current to flow into the ReadAA/rite 
head. As a precaution to erroneous writing, the first 
data byte is loaded into the Data Register in response 
to a Data Request from the device before the WG is 
activated. 

Writing is inhibited when the WPRT input is asser- 
ted, in which case any Write Command is 
immediately terminated, an intenupt is generated and 
the Write Protect Status bit is set. 

For Write operations, the WD1 772-02 provides WG to 
enable a Write condition, and WD which consists of 
a series of active high pulses. These pulses contain 
both Clock and Data information in FM and MFM. WD 
provides the unique missing clock patterns for recor- 
ding Address Marks. 

On the WD1 772-02, the Precomp Enable bit in Write 
Commands allows automatic Write precompensation 
to take place. The outgoing Write Data stream is 
delayed or advanced from nominal by 187 nsec accor- 
ding to the following table: 



PATTERN 


MFM 


FM 


X 
X 



1 


1 





1 
1 







1 

1 




Early 
Late 
Early 
Late 


N/A 
N/A 
N/A 
N/A 


^ i 






1 


- Next Bit to be sent 














- Previous Bits sent 



Precompensation is typically enabled on the inner- 
most tracks where bit shifts usually occur and bit 
density is at its maximum. 

COMMAND DESCRIPTION 

The WD1 772-02 accepts 11 commands. Command 
words are only loaded in the Command Register when 
the Busy Status bit is off (Status bit 0). The one ex- 
ception is the Force Interrupt Command. Whenever 
a command is being executed, the Busy Status bit 
is set. When a command is completed, an interrupt 
is generated and the Busy status bit is reset. The 
Status Register indicates whether the completed 
command encountered an error or was fault free. 
Commands are divided into four types and are sum- 
marized in the following pages. 



O 
o 



Floppy Disk Controller Devices 



1-31 



COMMAND SUMMARY 











BITS 








TYPE COMMAND 


7 


6 


5 


4 


3 


2 


1 





1 Restore 














h 


V 


r^ 


rn 


1 Seek 











1 


h 


V 


ri 


rn 


1 Step 








1 


u 


h 


V 


ri 


rn 


1 Step-in 





1 





u 


h 


V 


ri 


•"n 


1 Step-out 





1 


1 


u 


h 


V 


r 


rn 


II Read Sector 


1 








m 


h 


E 








II Write Sector 


1 





1 


m 


h 


E 


P 


an 


III Read 


















Address 


1 


1 








h 


E 








III Read Track 


1 


1 


1 





h 


E 








III Write Track 


1 


1 


1 


1 


h 


E 


P 





IV Force 


















Interrupt 


1 


1 





1 


I3 


I2 


I1 


lo 



FLAG SUMMARY 



TYPE I COMMANDS 



h = Motor On Flag (Bit 3) 



h = 0, Enable Spin-up Sequence 
h = 1, Disable Spin-up Sequence 

V = Verify Flag (Bit 2) 

V = 0, No Verify 

V = 1, Verify on Destination Track 

r^, Tq = Stepping Rate (Bits 1,0) 

ri ro WD1 772-02 












1 


1 





1 


1 



6 ms 
12 ms 

2 ms 

3 ms 



u = Update Flag (Bit 4) 



u = 0, No Update 

u = 1, Update Track Register 



TYPE II & 111 COMMANDS 



m = Multiple Sector Flag (Bit 4) 

m = 0, Single Sector 
m = 1, Multiple Sector 

H = Motor On Flag (Bit 3) 

H = 0, Enable Spin Up Sequence 
H = 1, Disable Spin Up Sequence 

ap = Data Address Mark (Bit 0) 

ao = Write Normal Data iVIark 
ao = 1, Write Deleted Data fvlark 

E = 15ms Settling Delay (Bit 2) 

E = 0, No Delay 

E = 1, Add 15ms Delay 

P = Write Precompensation (Bit 1) 

P = O.Enable Write Precomp 
P = 1, Disable Write Precomp 



TYPE IV COMMANDS 


I3-I0 Interrupt Condition (Bits 3-0) 


lo = 1, Not Used 


I1 = 1, Not Used 


I2 = 1, Interrupt on Index Pulse 


I3 = 1, immediate Interrupt 


I3-I0 = 0, Terminate without interrupt 



TYPE I COMMANDS 

The Type I Commands include the Restore, Seek, 
Step, Step-in, and Step-Out Commands. Each of the 
Type I Commands contains a rate field (ro,ri), which 
determines the stepping motor rate. 

A 4 fisec (MFM) or 8 fisec (FM) pulse is provided as 
an output to the drive. For every step pulse issued, 
the drive moves one track location in a direction deter- 
mined by the direction output. The chip steps the drive 
in the same direction it last stepped unless the com- 
mand changes the direction. 

The Direction signal is active high when stepping in 
and low when stepping out. The Direction signal is 
valid 24 psec before the first stepping pulse is 
generated. 

After the last directional step, an additional 15 msec 
of head settling time takes place if the Verify flag is 
set in Type I Commands. There is also a 15 msec 
head settling time if the E flag is set in any Type II 
or III Command. 

When a Seek, Step, or Restore Command is executed, 
an optional verification of Read/Write head position 
can be performed by setting bit 2 (V = 1) in the com- 
mand word to a logic 1, The verification operation 
begins at the end of the 15 msec settling time after 
the head is loaded against the media. The track 
number from the first encountered ID Field is com- 
pared against the contents of the Track Register. If 
the track numbers compare and the ID Field CRC is 
correct, the verify operation is complete and an INTRQ 
is generated with no errors. If there is a match but 
not a valid CRC, the CRC error status bit is set (Status 
Bit 3), and the next encountered ID Field is read from 
the disk for the verification operation. 

The WD1 772-02 finds an ID Field with correct track 
number and correct CRC within 5 revolutions of the 
media, or the seek error is set and an INTRQ is 
generated. If V =: 0, no verification is performed. 

On the WD1 772-02, all commands, except the Force 
Interrupt Command, are programmed via the h Flag 
to delay for spindle motor start up time. If the h Flag 
is not set and the MO signal is low when a command 
is received, the WD1 772-02 forces MO to a logic 1 and 
waits 6 index pulses before executing the command. 
At 300 RPM, this guarantees a one second spindle 
start up time. If after finishing the command, the 
device remains idle for 9 revolutions, the MO 



1-32 



Floppy Disk Controller Devices 



signal goes back to a logic 0. If a command is issued 
while MO is high, the command executes 
immediately, defeating the 5 revolution start up. This 
feature allows consecutive Read or Write commands 
without waiting for motor start up each time; the 
WD1772-02 assumes the spindle motor is up to speed. 



RESTORE (SEEK TRACK 0) 

Upon receipt of this comm and, the Track 00 (TROO) 
input is sampled. If TROO is active low, indicating 
the ReadAA/rite head is positioned over track 0, the 
Track Register i s load ed with zeroes and an interrupt 
is generated. If TROO is not active low, stepping 
pulses at a rate specified by the ri,ro field are issued 
until the TROO input is activated. 



O 
to 

I 

o 

lO 



ENTER 




SET BUSY, RESET ORG, 
SEEK ERROR, DRO, INTRQ 




SET MO 
WAIT 6 INDEX PULSES 



'command^ 


YES 


SET 




A 
s^TEP-IN 


y ^ 


DIRECTION 




^no 




'command'v 








. YES 


RESET 
DIRECTION 




A 
^^TEP-OU^>^ 


P* * 




T^NO 




command^ 


YES 






A ^ 


^ 




^ 


^<^ 








Ino 






' 




FFhTOTR 



T 



OTODR 



^ 



NO 



^ ^ 



^ 




YES 



YES 



RESET DIRECTION 



^ 




SET DIRECTION 
I 




1T0TR 

zn — 



OTOTR 



ISSUE 
ONE STEP PULSE 



DELAY ACCORDING 
TO Ri.Rq FIELD 




NO v^ommandV yes 

A STEP, S 

vOR STEI 



{TjJ 



TYPE I COMMAND FLOW 



TYPE I COMMAND FLOW 



Floppy Disk Controller Devices 



1-33 



D 

_^ 

lO 

o 

lO 



At this time, the Tracl< Register is load ed wit h 
zeroes and an interrupt is generated. If the TROO 
input does not go active low after 255 stepping pulses, 
the WD1772-02 terminates operation, interrupts, and 
sets the Seek Error status bit, providing the V flag 
is set. A verification operation also takes place if the 
V flag is set. The h bit allows the Motor On option 
at the start of a command. 

SEEK 

This command assumes that the Track Register con- 
tains the track number of the current position of the 
Read/Write head and the Data Register contains the 
desired track number. The WD1 772-02 updates the 
Track Register and Issues stepping pulses in the 
appropriate direction until the contents of the Track 
Register are equal to the contents of the Data 
Register (the desired track location). A verification 
operation takes place if the V flag is on. The h bit 



VERIFY 
SEQUENCE 




INTRO RESET BUSY 



^ 



INTRO, RESET BUSY 
SET SEEK ERROR 



) 



RESET 
ORG 



(INTRO ^ 

RESET BUSY J' 



TYPE I COMMAND FLOW 



allows the Motor On option at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. Note: When using multiple drives, the 
Track Register is updated for the drive selected before 
seeks are issued. 

STEP 

Upon receipt of this command, the WD1772-02 issues 
one Stepping Pulse to the disk drive. The stepping 
motor direction is the same as in the previous step 
command. After a delay determined by the r-i.ro field, 
a verification takes place if the V flag is on. If the U 
flag Is on, the Track Register is updated. The h bit 
allows the Motor On option at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. 

STEP-IN 

Upon receipt of this command, the WD1772-02 issues 
one Stepping Pulse in the direction towards the in- 
ner most track. If the U flag is on, the Track Register 
is incremented by one. After a delay determined by 
the r-,,ro field, a verification takes place if the V flag 
is on. The h bit allows the Motor On option at the start 
of the command. An interrupt is generated at the com- 
pletion of the command. 

STEP-OUT 

Upon receipt of this command, the WD1772-02 issues 
one stepping pulse in the direction towards track 0. 
If the U flag is on, the Track Register is decremented 
by one. After delay determined by the r-i.ro field, a 
verification takes place if the V flag is on. The h bit 
allows the Motor On option at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. 

TYPE II COMMANDS 

The Type II Commands are the Read Sector and Write 
Sector commands. Prior to loading the Type II Com- 
mand into the Command Register, the computer 
loads the Sector Register with the desired sector 
number. Upon receipt of the Type II command, the 
Busy Status bit is set. If the E flag = 1, the command 
executes after a 15 msec delay. 

(When an ID field Is located on the disk, the 
WD1 772-02 compares the Track Number on the ID 
field with the Track Register. If there is not a match, 
the next encountered ID field is read and a com- 
parison is again made). If there is a match, the Sec- 
tor Number of the ID field is compared with the Sector 
Register. If there is no Sector match, the next 
encountered ID field is read off the disk and com- 
parisons again made. If the ID field CRC is correct, 
the data field is located and is either written into, or 
read from, depending upon the command. 



1-34 



Floppy Disk Controller Devices 




SET BUSY, RESET DRQ, LOST 

DATA, RECORD NOT FOUND, & 

STATUS BITS5& 6 INTRO 




YES 



SET MO 

WAIT 

6 INDEX PULSES 




TYPE II COMMAND 

The WD1772-02 finds an ID field with a Tracl< number, 
Sector number, and CRC within 5 revolutions of the 
disk, or, the Record Not Found Status bit is set (Status 
Bit 4) and the command is terminated with an INTRQ. 

Each of the Type II Commands contains an m flag 
which determines if multiple records (sectors) are read 
or written, depending upon the command. If m = 0, 
a single sector Is read or written and an interrupt is 



generated at the completion of the command. If m 
= 1, multiple records are read or written with the Sec- 
tor Register internally updated so that an address 
verification occurs on the next record. The WD1772-02 
continues to read or write multiple records and 
updates the Sector Register in numerical ascending 
sequence until the Sector Register exceeds the 
number of sectors on the track or until the Force Inter- 
rupt Command is loaded into the Command Register, 
which terminates the command and generates an 
interrupt. 

For example: If the WD1772-02 is instructed to read 
sector 27 and there are only 26 on the track, the Sec- 
tor Register exceeds the number available. The 
WD1772-02 searches for 5 disk revolutions, interrupts 
out, resets Busy, and sets the Record Not Found 
Status Bit. 

READ SECTOR 

Upon receipt of the Read Sector Command, the Busy 
Status Bit is set, then when an ID field is encountered 
that has the correct track number, correct sector 
number, and correct CRC, the data field is presented 
to the computer. The Data Address Mark of the data 
field is found with 30 bytes in single density and 43 
bytes in double density of the last ID field CRC byte. 
If not, the ID field is searched for and verified again 
followed by the Data Address Mark search. If, after 
five revolutions the DAM is not found, the Record Not 
Found Status Bit is set and the operation is ter- 
minated. When the first character or byte of the data 
field is shifted through the DSR, it is transferred to 
the DR, and DRQ is generated. When the next byte 
is accumulated in the DSR, it is transferred to the DR 
and another DRQ is generated. If the computer has 
not read the previous contents of the DR before a new 
character is transferred, that character is lost and the 
Lost Data Status Bit is set. This sequence continues 
until the complete data field is inputted to the com- 
puter. If there is a CRC error at the end of the data 
field, the CRC Error Status bit is set, and the com- 
mand is terminated (even if it is a multiple record 
command). 

At the end of the Read operation, the type of Data 
Address Mark encountered in the data field is 
recorded in the Status Register (Bit 5) as shown: 



STATUS BIT 5 



Deleted Data Mark 
Data Mark 



WRITE SECTOR 

Upon receipt of the Write Sector Command, the Busy 
Status Bit is set. When an ID field is encountered that 
has the correct track number, correct sector number, 
and correct CRC, a DRQ is generated. The WD1 772-02 
counts off 11 bytes in single density and 22 bytes in 
double density from the CRC field and the WG 



I 

O 
N3 



Floppy Disk Controller Devices 



1-35 



I 

o 



NO 




INTRQ, RESET BUSY 
SET RECORD-NOT FOUND 



JD ) 



BRING IN SECTOR LENGTH FIELD 

STORE LENGTH IN INTERNAL 

REGISTER 



SET CRC 
STATUS ERROR 




RESET 
CRC 



^ 



TYPE II COMMAND 



ouput is made active if the DRQ is serviced (i.e., the 
DR is loaded by the computer). If DRQ is not serviced, 
the command is terminated and the Lost Data Status 
Bit is set. If the DRQ is serviced, the WG is made 
active and six bytes of zeroes in single density and 
12 bytes in double density are written on the disk. The 
Data Address Mark is then written on the disk as de- 
termined by the ao field of the command as shown: 



DATA ADDRESS MARK (BIT 0) 



Deleted Data Mark 
Data Mark 



The WD1 772-02 writes the data field and generates 
DRQ's to the computer. If the DRQ is not serviced 
in time for continuous writing, the Lost Data Status 



1-36 



Floppy Disk Controller Devices 



c 




READ SECTOR 
SEQUENCE 



PUT RECORD TYPE IN 
STATUS REG BIT 5 



INTRQ, RESET BUSY 
SET CRC ERROR 



) 



to 

O 

to 



^ 




+ 1 TO 
SECTOR REG 



k)(^ 



NTRQ RESET BUSY 



5 



TYPE II COMMAND 



Floppy Disk Controller Devices 



1-37 




DELAY 2 BYTES OF GAP 



DELAY 9 BYTES OF GAP 




HAS 
DR BEEN ^s,. NO 
LOADED BY COMPUTER 
(DRQ - 0) 



DELAY 1 BYTE OF GAP 



TURN ON WG & WRITE 
6 BYTES OF ZEROES 



WRITE DATA AM 

ACCORDING TO Aq FIELD 

OF WRITE COMMAND 



DR TO DSR, SET DRQ 



WRITE BYTE TO DISK 




WRITE 
SEQUENCE 



INTRO, RESET BUSY 
SET LOST DATA 




) 



DELAY 11 BYTES 



TURN ON WG & WRITE 
12 BYTES OF ZEROES 



SET DATA LOST 
WRITE BYTE 
OF ZEROES 



YES 



WRITE CRC 



WRITE 1 BYTE OF FF 



TURN OFFWG. 

I 



k) 



TYPE II COMMAND 



1-38 



Floppy Disk Controller Devices 



Bit is set and a byte of zeroes is written on tiie disl<. 
The command is not terminated. After the last data 
byte is written on the disk, the two-byte CRC is com- 
puted Internally and written on the disk followed by 
one byte of logic ones in FM or in MFM. The WG out- 
put is then deactivated. INTRQ sets 24 fisec (MFM) 
after the last CRC byte is written. For partial sector 
writing, the proper method is to write data and fill the 
balance with zeroes. 

TYPE III COMMANDS 

Read Address 

Upon receipt of the Read Address Command, the 
Busy Status Bit is set. The next encountered ID field 
is then read in from the disk, and six data bytes of 
the ID field are assembled and transferred to the DR, 
and a DRQ is generated for each byte. The six bytes 
of the ID field are shown: 



TRACK 
ADDR 


SIDE 
NUMBER 


SECTOR 
ADDR 


SECTOR 
LENGTH 


CRC 

1 


CRC 
2 


1 


2 


3 


4 


5 


6 



Although the CRC characters are transferred to the 
computer, the WD1 772-02 checks for validity and the 
CRC error status bit is set if there is a CRC error. The 
Track Address of the ID field is written into the sec- 
tor register so that a comparison can be made by the 
user. At the end of the operation, an interrupt is 
generated and the Busy Status is reset. 

Read Track 

Upon receipt of the Read Track Command, the head 
is loaded and the Busy Status bit is set. Reading 
starts with the leading edge of the first encountered 
index pulse and continues until the next index pulse. 
All Gap, Header, and data bytes are assembled and 
transferred to the data register and DRQ's are 
generated for each byte. The accumulation of bytes 
is synchronized to each address mark encountered. 
An interrupt is generated at the completion of the 
command. 

This command has several characteristics which 
make it suitable for diagnostic purposes. These 
characteristics are: no CRC checking is performed; 



gap information is included in the data stream; and 
the Address Mark Detector is on for the duration of 
the command. Because the AM detector is always 
on, write splices or noise may cause the chip to look 
for an AM. 

The ID AM, ID field, ID CRC bytes, DAM, Data, and 
Data CRC Bytes for each sector are correct. The Gap 
Bytes may be read incorrectly during write-splice time 
because of synchronization. 

WRITE TRACK FORMATTING THE DISK 

Data and gap information are provided at the com- 
puter interface. Formatting the disk is accomplish- 
ed by positioning the head over the desired track 
number and issuing the Write Track Command. 

Upon receipt of the Write Track Command, the Busy 
Status Bit is set. Writing starts with the leading edge 
of the first encountered Index Pulse and continues 
until the next Index Pulse, at which time the interrupt 
is activated. The Data Request is activated im- 
mediately upon receiving the command, but writing 
does not start until after the first byte is loaded into 
the Data Register. If the DR is not loaded within three 
byte times, the operation is terminated making the 
device Not Busy, the Lost Data Status Bit is set, and 
the interrupt is activated. If a byte is not present in 
the DR when needed, a byte of zeroes is substituted. 

This sequence continues from one Index Pulse to the 
next. Normally, whatever data pattern appears in the 
Data Register is written on the disk with a normal 
clock pattern. However, if the WD1 772-02 detects a 
data pattern of F5 through FE in the Data Register, 
this is interpreted as Data Address Marks with miss- 
ing clocks or CRC generation. 

The CRC generator is initialized when any data byte 
from F8 to FE is transferred from the DR to the DSR 
in FM or by receipt of F5 in MFM. An F7 pattern 
generates two CRC characters in FM or MFM. As a 
consequence, the patterns F5 through FE do not ap- 
pear in the gaps, data field, or ID fields. Also, CRC's 
are generated by an F7 pattern. 

Disks are formatted in IBM 3740 or System 34 formats 
with sector lengths of 128, 256, 512, or 1024 bytes. 



O 

•>! 
I 

o 

N3 



DATA PATTERN 
IN DR (HEX) 






IN FM (DDEN = 1) 


IN MFM (DDEN = 0) 


00 thru F4 


Write 00 thru F4 with CLK = FF 


Write 00 thru F4, in MFM 


F5 


Not Allowed 


Write A1* in MFM, Present CRC 


F6 


Not Allowed 


Write C2** in MFM 


F7 


Generate 2 CRC bytes 


Generate 2 CRC bytes 


F9 thru FB 


Write F8 thru FB, CLK = C7, Preset 






CRC 


Write F8 thru FB, in MFM 


FC 


Write FC with CLK = D7 


Write FC in MFM 


FD 


Write FD with CLK = FF 


Write FD in MFM 


FE 


Write FE, CLK = C7, Preset CRC 


Write FE in MFM 


FF 


Write FF with CLK = FF 


Write FF in MFM 



'Missing clock transition between bits 4 and 5. 
'Missing clock transition between bits 3 and 4. 



Floppy Disk Controller Devices 



1-39 



to 
o 

lO 




SET BUSY, RESET DRQ, 

LOST DATA STATUS 

BITS 4, 5 



SET MO 




DELAY 6 
INDEX PULSES 




/" \ YES y IS 

/ INTRQ RESET W<^ wPRT = 
V BUSY SET WPRT ' 



DELAY 3 BYTE 
TIMES 



SET INTRQ 
LOST DATA 
RESET BUSY 




DR TO DSR 



SET DRQ 



TYPE III COMMAND WRITE TRACK 



1-40 



Floppy Disk Controller Devices 





YES(MFM) 


B 
^ DDEN ^S 














TnO(FM) 




^/^ DOES \^ YES 
^ DSR = F7 > ► 


WRITE 2 ORG 
CHARS. CLK = FF 








\ 


Yno 




v/^DOES^S. YES 
<r DSR = FC > » 


WRITE FC 
CLK = D7 




jCno 




<M3SR = FD, FE/S- 
^«^ OR F8-FB y^ 


YES 


WRITE FD, FE OR 
F8-F9, CLK = C7 
INITIALIZE CRC 








^Cno 








WRITE DSR 
CLK = FF 














X 


i 


/^ INTRO RESET Y 
\^ BUSY )" 


YES >^ PHYs"\v 
^ — C INDEX MARK> 




¥ NO 




./^ HA«^ ^V 

YES/nRRlpM\NO^ 


WRITE 
BYTE OF ZEROES 
SET DATA LOST 


, 1 


\.,^^LOADED v^ "^ 




^0 


^^^ 






x/^ 


JL 


>^ DOES ^^ YES_^ 


WRITE A1 IN MFM 

WITH MISSING 

CLOCK INITIALIZE 

CRC 






S. OSR = f5 V? ^ 




xno 




^/^DOES^\^ 


YES 


WRITE C2 IN MFM 

WITH MISSING 

CLOCK 


V^^ DSR = F6 ^' 






^ngo 




^^DOES^\^ 


YES 


WRITE 2 CRC 
CHARS. 


^^ DSR = FF ^ 








^Cno 








WRITE DSR 
IN MFM 

























■ 

o 
to 



TYPE III COMMAND WRITE TRACK 



Floppy Disk Controller Devices 



1-41 



lO 

o 



TYPE IV COMMANDS 

The Forced Interrupt Command is used to terminate 
a multiple sector read or write command or to ensure 
Type I status in the Status Register. This command 
is loaded into the Command Register at any time. If 
there is a current command under execution, (Busy 
Status Bit set), the command is terminated and the 
Busy Status Bit reset. 

The lower four bits of the command determine the 
conditional interrupt as follows: 



Not used 

Not Used 

Every Index Pulse 

Immediate Interrupt 



'0 = 

li = 

12 = 

13 = 

The conditional interrupt is enabled when the cor- 
responding bit positions of the command (I3-I0) are 
set to a 1. When the condition for interrupt is met, 
the INTRQ line goes high signifying that the condi- 
tion specified has occurred. If I3-I0 are all set to zero 
(Hex DO), no interrupt occurs but any command 
presently under execution is immediately terminated. 
When using the immediate interrupt condition (I3 = 
1), an interrupt is immediately generated and the cur- 
rent command terminated. Reading the status or 
writing to the command register does not 
automatically clear the interrupt. The Hex DO is the 
only command that enables the immediate interrupt 
(Hex D8) to clear on a subsequent load Command 
Register or Read Status Register operation. Follow 
a Hex D8 with DO command. 

Wait 16/isec (double density) or 32 fisec (single den- 
sity) before issuing a new command after issuing a 
forced interrupt. Loading a new command sooner 
than this nullifies the forced interrupt. 

Forced interrupt stops any command at the end of 
an internal micro-instruction and generates INTRQ 
when the specified condition is met. Forced interrupt 
waits until ALU operations in progress are complete 
(CRC calculations, compares, etc.). 

Status Register 

Upon receipt of any command, except the Force Inter- 
rupt Command, the Busy Status Bit is set and the rest 
of the status bits are updated or cleared for the new 
command. If the Force Interrupt Command is received 
when there is a current command under execution, 
the Busy Status Bit is reset, and the rest of the status 
bits are unchanged. If the Force Interrupt Command 
is received when there is not a current command 
under execution, the Busy Status Bit is reset and the 
rest of the status bits are updated or cleared. In this 
case. Status reflects the Type I commands. 

The user has the option of reading the Status Register 
through program control or using the DRQ line with 
DMA or interrupt methods. When the Data Register 
is read, the DRQ bit in the Status Register and the 
DRQ line are automatically reset. A write to the Data 
Register also causes both DRQ's to reset. 

The Busy Bit in the status may be monitored with a 



user program to determine when a command is com- 
plete, in lieu of using the INTRQ line. When using the 
INTRQ, a Busy Status check is not recommended 
because a read of the Status Register to determine 
the condition of busy resets the INTRQ line. 

The format of the Status Register is shown below: 



(BITS) 


7 


6 


5 


4 


3 


2 


1 





S7 


S6 


S5 


S4 


S3 


S2 


SI 


so 



Because of internal sync cycles, certain time delays 
are observed when operating under programmed I/O, 
as shown. 



Operation 


Next Operation 


Delay Req'd. 
FM MFM 


Write to 
Command Reg. 


Read Busy Bit 
(Status Bit 0) 


48/iSec 


24;isec 


Write to 
Command Reg. 


Read Status 
Bits 1-7 


64;iSec 


32;isec 


Write 
Register 


Read Same 
Register 


32/isec 


lOjjsec 



RECOMMENDED - 128 BYTES/SECTOR 

The recommended single-density format with 128 
bytes/sector is shown below. In order to format a 
diskette, the user issues the Write Track Command, 
and loads the Data Register with the following values. 
For every byte to be written, there is one Data 
Request. 



NUMBER 




OF BYTES 


HEX VALUE OF BYTE WRITTEN 




40 
6 


FF (or 00) 
00 




1 
1 


FE (ID Address Mark) 
Track Number 




1 
1 
1 
1 

11 
6 


Side Number (00 or 01) 
Sector Number (1 thru 1A) 
00 (Sector Length) 
F7 (2 CRC's written) 
FF (or 00) 
00 




1 
128 

1 

10 

369** 


FB (Data Address Mark) 
Data (IBM uses E5) 
F7 (2 CRC's written) 
FF (or 00) 
FF (or 00) 



'Write bracketed field 16 times. 
'Continue writing until WD1772-02 interrupts out. 
Approx. 369 bytes. 



1-42 



Floppy Disk Controller Devices 



INDEX 

DIIICC 







































REI 


r-tAlbU 
CHSECT 


DR 




































/ 


40 BYTES 
'FF- 


6 BYTES 
'00' 


ID 
■FE' 


TRACK 

# 


SIDE 
# 


SECTOR 

# 


LENGTH 


CRC 

1 


CRC 
2 


11 BYTES 
'FF' 


6 BYTES 
'00' 


DATA 
ADR 
MARK 


USER DATA 
128 BYTES 


CRC 

1 


CRC 
2 


10 BYTES 
■FF' 


/ 






































WRITE GATE 































SINGLE DENSITY FORMAT 



INDEX 
PULSE. 







-* 




FOR EACH SECTOR 








► 




/ 


60 BYTES 
'4E' 


12 BYTES 
■00' 


3 BYTES 
■A1' 


ID 
■FE' 


TRACK 

# 


SIDE 


SECTOR 


LENGTH 

# 


CRC 

1 


CRC 
2 


22 BYTES 
■4E' 


12 BYTES 
■00' 


3 BYTES 
•AV 


ID 
■FB' 


USER DATA 
256 BYTES 


CRC 

1 


CRC 
2 


24 BYTES 

■4E' 


/ 












ID FIELD ' 










DATA FIELD 









WRITE GATE- 



DOUBLE DENSITY FORMAT 



ZO-ZllVQfA 






256 BYTES/SECTOR 

Sliown above is the recommended dual-density for- 
mat with 256 bytes/sector. In order to format a 
diskette, the user issues the Write Track Command 
and loads the Data Register with the following values. 
For every byte to be written, there is one data request. 



NUMBER 




OF BYTES 


HEX VALUE OF BYTE WRITTEN 


60 


4E 




12 


00 




3 
1 

1 
1 
1 
1 
1 
22 


F5 (Writes A1) 
FE (ID Address Mark) 
Track Number (0 thru 4C) 
Side Number (0 or 1) 
Sector Number (1 thru 1A) 
01 (Sector Length) 
F7 (2 CRC's written) 
4E 




12 


00 




3 

1 

256 


F5 (Writes A1) 

FB (Data Address Mark) 

DATA 




1 
24 


F7 (Data Address Mark) 
4E 


668** 


4E 



1. Non-standard Formats 

Variations in the recommended formats are possible 
to a limited extent if the following requirements are 
met: 

1) Sector size must be 128, 256, 512 of 1024 bytes. 

2) Gap 2 cannot be varied from the recommended 
format. 

3) 3 bytes of A1 must be used in MFM. 

In addition, the Index Address Mark is not required 
for operation by the WD1 772-02. Gap 1, 3 and 4 
lengths are as short as 2 bytes for WD1 772-02 opera- 
tion, however PLL lock up time, motor speed varia- 
tion, write-splice area, etc. adds more bytes to each 
gap to achieve proper operation. For highest system 
reliability, use the recommended format. 





FM 


MFM 


Gap 1 


16 bytes FF 


32 bytes 4E 


Gap II 


11 bytes FF 


22 bytes 4E 


* 


6 bytes 00 


12 bytes 00 


* 




3 bytes A1 


Gap III** 


10 bytes FF 


24 bytes 4E 




4 bytes 00 


8 bytes 00 
3 bytes A1 


Gap IV 


16 bytes FF 


16 bytes 4E 



*Write bracketed field 16 times. 
'*Continue Writing until WD1772-02 interrupts out. 
Approx. 668 bytes. 



'Byte counts must be exact. 
'Byte counts are minimum, except exactly 3 bytes 
of A1 must be written. 



STATUS REGISTER DESCRIPTION 



BIT NAME 


MEANING 


S7 MOTOR ON 


This bit reflects the status of the Motor On output. 


S6 WRITE PROTECT 


On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates 
a Write Protect. This bit is reset when updated. 


S5 RECORD 
TYPE/SPIN-UP 


When set, this bit indicates that the Motor Spin-Up sequence has completed 
(5 revolutions) on Type 1 commands. Type 2 & 3 commands, this bit indicates record 
Type. = Data Mark. 1 = Deleted Data Mark. 


S4 RECORD NOT 
FOUND (RNF) 


When set, it indicates that the desired track, sector, or side were not found. This 
bit is reset when updated. 


S3 CRC ERROR 


If S4 is set, an error is found in one or more ID fields; otherwise it indicates 
error data field. This bit is reset when updated. 


S2 LOST DATA/ 
BYTE 


When set, it indicates the computer did not respond to DRQ in one byte time. 
This bit is reset to zero when updated. On Type 1 commands, this bit reflects the 
status of the TROO signal. 


SI DATA REQUEST 
INDEX 


This bit is a copy of the DRQ output. When set, it indicates the DR is full on a 
Read Operation or the DR is empty on a Write operation. This bit is reset to zero 
when updated. On Type 1 commands, this bit indicates the status of the IP 
signal. 


SO BUSY 


When set, command is under execution. When reset, no command is under 
execution. 



1-44 



Floppy Disk Controller Devices 



DC ELECTRICAL CHARACTERISTICS 

MAXIMUM RATINGS 

Storage Temperature - 55°C(- 67°F) to 

+ 125°C (257°F) 
Operating Temperature 0°C(32°F) to 

70°C (158°F) Ambient 
Maximum Voltage to Any Input 

with Respect to Vss + 7V to - 0.5V 



NOTE 

Maximum limits indicate where permanent device 
damage occurs. Continuous operation at these limits 
is not intended and should be limited to those con- 
ditions specified in the DC Operating Characteristics. 



O 

lO 

o 
ro 



DC OPERATING CHARACTERISTICS 

TA = 0°C(32°f=) to 70°C (158°F), Vss = OV, Vqc = +5V ± .25V 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


UNITS 


CONDITIONS 


l|L 


Input Leakage 




10 


mA 


V,N = Vcc 


loL 


Output Leakage 




10 


mA 


Vqut - Vcc 


V|H 


Input High Voltage 


2.0 




V 




V|H 


Input Low Voltage 




0.8 


V 




Vqh 


Output High Voltage 


2.4 




V 


lo = -100 mA 


Vol 


Output Low Voltage 




0.40 


V 


lo = 1.6 mA 


Pd 


Power Dissipation 




.75 


w 




Rpu 


Internal Pull-Up 


100 


1700 


hA 


V|N = OV 


Ice 


Supply Current 


75(Typ) 


150 


mA 





DPLL SPECIFICATION 

Fc Capture Range ± 6% (min) 

T| Lock Response 4 bytes 00 hex (max) 

WT Window Tolerance 50% for 10E-9 Error Rate (min) 



Floppy Disk Controller Devices 



1-45 



AC TIMING CHARACTERISTICS 

TA = 0°C (32°F) to 70°C (158°F), ^SS = OV, ^CC = +5V ± .25V 



ro 
o 



1 


DALS 
0-7 


X 


VALID 


zyzz 


R/W 




■* — 'DV — •» 




■* 'DC 


H »- 


/ ' 


\ 


cs 


V« 'RE 


—y 


*• 






UHQ 






V_ 













READ ENABLE TIMING 



READ ENABLE TIMING - RE such that: R/W = 1, CS = 0. 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNITS 


CONDITIONS 


tRE 


RE Pulse Width of CS 


200 






nsec 


Cl= 50 pf 


^DRR 


DRQ Reset from RE 




200 


300 


nsec 




^DV 


Data Valid from RE 




100 


200 


nsec 


Cl= 50 pf 


^DOH 


Data Hold from RE 
INTRQ Reset from RE 


20 




150 
8 


nsec 
f/sec 


Cl= 50pf 



Note: Worst case service time for DRQ is 23.5 ^sec for IVIFM and 47.5 /usee for FM. 



7-46 



Floppy Disk Controller Devices 



DALS 
0-7 






Y VALID 


X 












-'DM 






CS 

R/W 

A0,A1 


'SET ► 

\ 

'AS— J 


■^ 

■^ 


'WE / 

/ 

»- ■* 


( — 'hld 


/ 

'AH 1^ 


r 

■* 


X 




< 










DRQ 


•^ 


— 'DRW A^ 



I 

o 

lO 



WRITE ENABLE TIMING 



WRITE ENABLE TIMING - WE such that: R/W = 0, CS = 0. 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNITS 


CONDITIONS 


tAS 


Setup ADDR to CS 


50 






nsec 




^SET 


Setup R/W to CS 









nsec 




tAH 


Hold ADDR from CS 


10 






nsec 




^HLD 


Hold R/W from CS 









nsec 




tyvE 


WE Pulse Width 


200 






nsec 




^DRW 


DRQ Reset from WE 




100 


200 


nsec 




tos 


Data Setup to WE 


150 






nsec 




^DH 


Data Hold from WE 
INTRQ Reset from WE 







8 


nsec 
fisec 





READ DATA TIMING: 



CHARACTERISTIC 


MIN 


TYP 


MAX 


UNITS 


CONDITIONS 




.200 

.400 

3 




3 
3 


fisec 
/isec 


MFM 
FM 


Raw Read Pulse Width 


Raw Read Cycle Time 



Floppy Disk Controller Devices 



1-47 



WRITE DATA TIMING: 



D 

o 
to 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNITS 


CONDITIONS 




Write Gate to Write Data 




4 
2 




fisec 
f^sec 


FM 
MFM 




Write Data Cycle Time 




4,6,8 




fisec 






Write Gate off from WD 




4 
2 




fisec 


FM 
MFM 


twp 


Write Data Pulse Width 




820 
690 
570 
1.38 




nsec 
nsec 
nsec 
fisec 


Early MFM 

Nominal MFM 

Late MFM 

FM 




LATE twp 



WRITE DATA TIMING 



1-48 



Floppy Disk Controller Devices 



w^ 



CLK 



I-*- 'CYC -J 



■*A 'CD 



k 



'CDo 



DIRC 



STEP 



STEP IN 



VIH 



t|P 



• 'MR ■ 



w-'dir— »4 



*— RiRq* - 

'stp m h 'stp i-*- 



U*— 'DIR -♦-I 'SPT I-* 



^^: 



O 
N3 



MISCELLANEOUS TIMING 



MISCELLANEOUS TIMING: 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNITS 


CONDITIONS 


^CDI 


Clock Duty (low) 


50 


67 




nsec 




tcD2 


Clock Duty (high) 


50 


67 




nsec 




tsTP 


Step Pulse Output 




4 
8 




fisec 


MFM 
FM 


^DIR 


Dir Setup to Step 




24 
48 




^sec 


MFM 
FM 


*MR 


Master Reset Pulse Width 


50 






fisec 




t|P 


Index Pulse Width 


20 






fisec 





Floppy Disk Controller Devices 



1-49 



1-50 Floppy Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD1772-02 Floppy Disk Formatter/Controller 
Family Application Notes 



INTRODUCTION 

To meet the demand for a low cost compact LSI 
Floppy Disk Controller device, Western Digital has 
developed the WD1772-02. The WD1772-02 is a NMOS 
Floppy Disk Controller device that incorporates the 
FD179X, a digital data separator and vjrWe 
precompensation circuitry all in a single chip. The 
device offers soft sector formatting, selectable step- 
ping rates, automatic track seek with verify, and 
variable sector lengths. The WD1 772-02 comes in a 
28-pin dual-in-line package or quad pack and operates 
from a single 5 volt only power supply. 

APPLICATIONS 

The Mini-Floppy Controller is targeted for the low cost 
sector of the disk drive market, where digital data 
separation is preferred over analog phase lock loop. 
Included in this market are Personal Computers, Por- 
table Computers and Small Business Computers. 

HOST INTERFACING 

Interfacing to a Host processor is accomplished 
through the eight bit bi-directional Data Access Lines 
(DAL) and associated control lines. The DAL is used 
to transfer data, status and control words out of or 
into WD1772-02. The DAL having three states enabled 
as an output when Chip Select (CS) is active low and 
Read/Write (R/W) is high or as input receiver when CS 
and R/W is low. When transfer of data with the device 
is required by the Host CS is made low. The address 
bits AO and A1 combined with the R/W line select the 
register and the direction of data. 



During Direct Memory Access (DMA) data transfers 
between the WD1 772-02 and Host Memory, the Data 
Request (DRQ) line is used in Data Transfer Control. 
This signal also appears as status bit 1 during 
Read/Write operations. On Disk Read operations the 
DRQ is active when an assembled byte is present in 
the Data Register, then reset when read by the Host. 
If the Host fails to read the Data Register before the 
following byte is assembled in the Data Register, the 
lost data bit is set in Status Register. 

At the completion of every command INTRQ is 
asserted. INTRQ is de-asserted by either reading the 
status or by loading the Command Register. 

DISKETTE DRIVE INTERFACING 

The WD1 772-02 has two modes of operation depen- 
ding on the state of DDEN, regardless of the state 
DDEN the CLK input remains at 8 MHz. Disk Reads 
with sector lengths of 128, 256, 512 and 1024 byte sec- 
tor in both FM or MFM from diskettes is 
accomplished via the internal digital data separator. 
Disk Write operation in MFM on inner tracks may 
require write precompensation. Write precompensa- 
tion is enabled when bit 1 = 0, in the Write command 
and a precompensation value of 187 nsec is 
produced. 

The diskettes spindle motor is controlled by bit 3 of 
any Type I, II or III command, upon receiving a com- 
mand with bit 3 = 0, the spin up sequence is enabled. 



GENERAL INFORMATION 

A -f-5 volt supply ±5% is used as Vqc. and the 
clock input requires a free running 50% duty cycle 
at 8 MHz ±0.1%. 



O 
o 

lO 



Floppy Disk Controller Devices 



1-51 



1-52 Floppy Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 



FD179X-02 Floppy Disk Formatter/Controller Family 






FEATURES 

• TWO VFO CONTROL SIGNALS - RG & VFOE 

• SOFT SECTOR FORMAT COMPATIBILITY 

• AUTOMATIC TRACK SEEK WITH VERIFICATION 

• ACCOMMODATES SINGLE AND DOUBLE 
DENSITY 

• FORMATS 

IBM 3740 Single Density (FM) 

IBM System 34 Double Density (MFM) 

Non IBM Format for Increased Capacity 

• READ MODE 

Single/Multiple Sector Read with Automatic 

Search or Entire Track Read 

Selectable 128, 256, 512 or 1024 Byte Sector 

Lengths 

• WRITE MODE 

Single/Multiple Sector Write with Automatic Sec- 
tor Search 
Entire Track Write for Diskette Formatting 

• SYSTEM COMPATIBILITY 

Double Buffering of Data 8 Bit Bi-Directional Bus 
for Data, Control and Status 
DMA or Programmed Data Transfers 
All Inputs and Outputs are TTL Compatible 
On-Chip Track and Sector Registers/Comprehen- 
sive Status Information 



PROGRAMMABLE CONTROLS 

Selectable Track to Track Stepping Time 

Side Select Compare 

INTERFACES TO WD1691 DATA SEPARATOR 

WINDOW EXTENSION 

INCORPORATES ENCODING/DECODING AND 

ADDRESS MARK CIRCUITRY 

FD1792/4 IS SINGLE DENSITY ONLY 

FD1795/7 HAS A SIDE SELECT OUTPUT 

179X-02 FAMILY CHARACTERISTICS 



O 
to 



FEATURES 


1791 


1792 


1793 


1794 


1795 


1797 


Single Density (FM) 


X 


X 


X 


X 


X 


X 


Double Density (MFM) 


X 




X 




X 


X 


True Data Bus 




X 


X 




X 




Inverted Data Bus 


X 


X 




X 






Write Precomp 


X 


X 


X 


X 


X 


X 


Side Selection Output 








X 


X 





APPLICATIONS 

8" FLOPPY AND 5 1/4" MINI FLOPPY CONTROLLER 
SINGLE OR DOUBLE DENSITY 
CONTROLLER/FORMATTER 



NC 


c 


. -^ .0 


T VODC 12V 


m 


c 


2 39 


~] INTRO 


Cs 


c 


3 38 


-) ono 


RI 


c 


' 37 


1 dBen--- 


'o 




5 36 


1 WPRT 


*1 




6 35 


1 ip 


••DALO 


c 


' 3« 


^ Troo 


OALl 


L 


8 33 


1 WF/VFOE 




L 




J^ 




6*r3 


C 


10 




31 


": WD 


Dl.lt 


C 


11 




30 


1 WG 


6*L5 


C 


12 




29 


T TG43 


CSO 


13 




28 


^ MLD 


0AL7 


L 


1* 27 


-] RAW READ 


STEP 


C 


15 26 


-) RCLK 


DIRC 


C 


16 25 


D • 


EARLY 


C 


1' 24 


1 CLK 


LATE 


C 


18 23 


n HLT 


liiB 


C 


19 22 


-) TEST 


GNDIVss C 


20 21 


JV^^(.6VI 



•1791/3 = RG 1795/7= SSO 
•1793/7 TRUE BUS 
•1792/4 OPEN 

PIN DESIGNATION 



C 



> 



r 



FLOPPY Disk 

CONTROLLER 
fORUATTER 



vss vdd vcc 



FD179X SYSTEM BLOCK DIAGRAM 



Floppy Disk Controller Devices 



1-53 



PIN OUTS 



D 
CO 

X 

o 
ro 



PIN 
NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


1 
19 


NO CONNECTION 


NO 

MR 


Pin 1 is internally connected to a back bias generator 
and must be left open by the user. 

A logic low (50 microseconds min.) on this Input resets 
the device and loads HEX 03 into the command 
register. The Not Ready (Status Bit 7) is reset during 
MR ACTIVE. When MR is brought to a logic high a 
RESTORE Command is executed, regardless of the 
state of the Ready signal from the drive. Also, HEX 
01 is loaded into sector register. 


MASTER RESET 


20 


POWER SUPPLIES 


Vss 


Ground 


21 




Vcc 


+ 5V ±5% 


40 




Vdd 


+ 12V±5% 


COMPUTEF 

2 

3 

4 


^ INTERFACE: 


WE 
CS 
RE 


A logic low on this input gates data on the DAL into 
the selected register when CS is low. 
A logic low on this input selects the chip and enables 
computer communication with the device. 

A logic low on this input controls the placement of 
data from a selected register on the DAL when CS 
is low. 


WRITE ENABLE 


CHIP SELECT 


READ ENABLE 


5,6 


REGISTER SELECT LINES 


AO.AI 


These inputs select the register to receive/transfer 
data on the DAL lines under RE and WE control: 


7-14 






CS A1 AO RE WE 
status Reg Command Reg 
1 Track Reg Track Reg 
1 Sector Reg Sector Reg 
1 1 Data Reg Data Reg 

Eight bit bi-directional bus used for transfer of data, 
control, and status. This bus is receiver enabled by 
WE or transmitter enabled by RE. Each line will 
drive 1 standard TTL load. 


DATA ACCESS LINES 


DAL0-DAL7 


24 


CLOCK 


CLK 


This input requires a free-running 50% duty cycle 
square wave clock for internal timing reference, 2 MHz 
±1% for 8" drives, 1 MHz ±1% for mini-floppies. 


38 


DATA REQUEST 


DRQ 


This open drain output indicates that the DR contains 
assembled data in Read operations, or the DR is 
empty in Write operations. This signal is reset when 
serviced by the computer through reading or loading 
the DR in Read or Write operations, respectively. Use 
10K pull-up resistor to +5. 


39 


INTERRUPT REQUEST 


INTRO 


This open drain output is set at the completion of any 
command and is reset when the STATUS register is 
read or the command register is written to. Use 10K 
pull-up resistor to +5. 



1-54 



Floppy Disk Controller Devices 



PIN 








NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


FLOPPY DISK INTERFACE: 






15 


STEP 


STEP 


The step output contains a pulse for each step. 


16 


DIRECTION 


DIRC 


Direction Output is active high when stepping in, 
active low when stepping out. 


17 


EARLY 


EARLY 


Indicates that the WRITE DATA pulse occuring while 
Early is active (high) should be shifted early for write 
precompensation. 


18 


LATE 


LATE 


Indicates that the write data pulse occurring while 
Late is active (high) should be shifted late for write 
precompensation. 


22 


TEST 


TEST 


This input is used for testing purposes only and should 
be tied to +5V or left open by the user unless inter- 
facing to voice coil actuated steppers. 


23 


HEAD LOAD TIMING 


HLT 


When a logic high is found on the HLT input the head 
is assumed to be engaged. It is typically derived from 
a 1 shot triggered by HLD. 


25 


READ GATE 


RG 






(1791,1792,1793,1794) 




This output is used for synchronization of external 
data separators. The output goes high after two Bytes 
of zeroes in single density, or 4 Bytes of either zeroes 
or ones in double density operation. 


25 


SIDE SELECT OUTPUT 


SSO 






(1794,1797) 




The logic level of the Side Select Output is directly 
controlled by the 'S' flag in Type 11 or III commands. 
When U = 1, SSO is set to a logic 1. When U = 0, 
SSO is set to a logic 0. The SSO is compared with 
the side information in the Sector ID Field. If they do 
not compare Status Bit 4 (RNF) is set. The Side Select 
Output is only updated at the beginning of a Type II 
or III command. It is forced to a logic upon a 
MASTER RESET condition. 


26 


READ CLOCK 


RCLK 


A nominal square-wave clock signal derived from the 
data stream must be provided to this input. Phasing 
(i.e., RCLK transitions) relative to RAW READ is impor- 


27 






tant but polarity (RCLK high or low) is not. 

The data input signal directly from the drive. This input 


RAW READ 


RAW READ 








shall be a negative pulse for each recorded flux 








transition. 


28 


HEAD LOAD 


HLD 


The HLD output controls the loading of the Read-Write 
head against the media. 


29 


TRACK GREATER 








THAN 43 


TG43 


This output informs the drive that the Read /Write 
head is positioned between tracks 44-76. This output 
is valid only during Read and Write Commands. 


30 


WRITE GATE 


WG 


This output is made valid before writing is to be per- 
formed on the diskette. 


31 


WRITE DATA 


WD 


A 50ns (MFM) or 500 ns (FM) output pulse per flux tran- 
sition. WD contains the unique Address marks as well 
as data and clock in both FM and MFM formats. 



Floppy Disk Controller Devices 



1-55 



D 

-A 

(O 

X 

■ 

o 
ro 



PIN 
NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


32 
33 

34 
35 
36 

37 


READY 


READY 


This input indicates disk readiness and is sampled 
for a logic high before Read or Write commands are 
performed. If Ready is low the Read or Write opera- 
tion is not performed and an interrupt is generated. 
Type 1 operations are performed regardless of the 
state of Ready. The Ready input appears in inverted 
format as Status Register bit 7. 

This is a bi-directional signal used to signify writing 
faults at the drive, and to enable the external PLO 
data separator. When WG = 1, Pin 33 functions as 
a WF input. If WF = 0, any write command will im- 
mediately be terminated. When WG = 0, Pin 33 func- 
tion as a VFOE output. VFOE will go low during a read 
operation after the head has loaded and settled (HLT 
= 1). On the 1795/7, it will remain low until the last 
bit of the second CRC byte in the ID field. VFOE will 
then go high until 8 bytes (MFM) or 4 bytes (FM) 
before the Address Mark. It will then go active until 
the last bit of the second CRC byte of the Data Field. 
On the 1791/3, VFOE will remain low until the end 
of the Data Field. This pin has an internal 100K Ohm 
pull-up resister. 

This input informs the FD179X that the Read / Write 
head is positioned over Track 00. 
This input informs the FD179X when the index hole 
is encountered on the diskette. 
This input is sampled whenever a Write Command 
is received. A logic low terminates the command and 
sets the Write Protect Status bit. 

This input pin selects either single or double density 


WRITE FAULT 


WFA/FOE 
VFO ENABLE 

TROO 
IP 


TRACK 00 


INDEX PULSE 


WRITE PROTECT 


WPRT 


DOUBLE DENSITY 


DDEN 


operation. When DDEN = 0, double density is 
selected. When DDEN = 1, single density is selec- 
ted. This line must be left open on the 1792/4. 



GENERAL DESCRIPTION 

The FD179X are N-Channel Silicon Gate MOS LSI 
devices which perform the functions of a Floppy Disk 
Formatter/Controller in a single chip implementation. 
The FD179X, which can be considered the end result 
of both the FD1771 and FD1781 designs, is IBM 3740 
compatible in single density mode (FM) and System 
34 compatible in Double Density Mode (MFM). The 
FD179X contains all the features of its predecessor 
the FD1771, plus the added features necessary to 
Read/Write and format a double density diskette. 
These include address mark detection, FM and MFM 
encode and decode logic, window extension, and 
write precompensation. In order to maintain com- 
patibility, the FD1771, FD1781, and FD179X designs 
were made as close as possible with the computer 
interface, instruction set, and I/O registers being iden- 
tical. Also, head load control is identical. In each case, 
the actual pin assignments vary by only a few pins 
from any one to another. 

The processor interface consists of an 8-bit bit direc- 
tional bus for data, status, and control word transfers. 



The FD179X is set up to operate on a multiplexed bus 
with other bus-oriented devices. 

The FD179X is TTL compatible on all inputs and out- 
puts. The outputs will drive ONE TTL load or three 
LS loads. The 1793 is identical to the 1791 except the 
DAL lines are TRUE for systems that utilize true data 
busses. 

The 1795/7 has a side select output for controlling 
double sided drives, and the 1792 and 1794 are "Single 
Density Only" versions of the 17 91 and 1793 respec- 
tively. On these devices, DDEN must be left open. 

ORGANIZATION 

The Floppy Disk Formatter is illustrated in the block 
diagram. The primary sections include the parallel 
processor interface and the Floppy Disk Interface. 

Data Shift Register - This 8-bit regist er assembles 
serial data from the Read Data input (RAW READ) 
during Read operations and transfers serial data to 
the Write Data output during Write operations. 



1-56 



Floppy Disk Controller Devices 



Data Register - This 8-bit register is used as a holding 
register during Disk Read and Write operations. In 
Disl< Read operations the assembled data byte is 
transferred in parallel to the Data Register from the 
Data Shift Register. In Disk Write operations informa- 
tion is transferred in parallel from the Data Register 
to the Data Shift Register. 

When executing the Seek command the Data Register 
holds the address of the desired Track position. This 
register is loaded from the DAL and gated onto the 
DAL under processor control. 

Track Register - This 8-bit register holds the track 
number of the current Read/Write head position. It 
is incremented by one every time the head is step- 
ped in (towards track 76) and decremented by one 
when the head is stepped out (towards track 00). The 
contents of the register are compared with the 
recorded track number in the ID field during disk 
Read, Write, and Verify operations. The Track Register 
can be loaded from or transferred to the DAL. This 
Register should not be loaded when the device is 
busy. 

Sector Register (SR) - This 8-bit register holds the 
address of the desired sector position. The contents 
of the register are compared with the recorded sec- 
tor number in the ID field during disk Read or Write 
operations. The Sector Register contents can be 
loaded from or transferred to the DAL. This register 
should not be loaded when the device is busy. 

Command Register (CR) - This 8-bit register holds the 
command presently being executed. This register 



should not be loaded when the device is busy unless 
the new command is a force interrupt. The command 
register can be loaded from the DAL, but not read 
onto the DAL. 

Status Register (STR) - This 8-bit register holds device 
Status information. The meaning of the Status bits 
is a function of the type of command previously 
executed. This register can be read onto the DAL, but 
not loaded from the DAL. 



■ This logic is used to check or to generate 
Cyclic Redundancy Check (CRC). The 



CRC Logic 

the 16-bit 

polynomial is:G(x) = x^*^ + x^^ + x** -f 1 . 

The CRC includes all information starting with the 
address mark and up to the CRC characters. The CRC 
register is preset to ones prior to data being shifted 
through the circuit. 

Arithmetic/Logic Unit (ALU) - The ALU is a serial com- 
parator, incrementer, and decrementer and is used 
for register modification and comparisons with the 
disk recorded ID field. 

Timing and Control - All computer and Floppy Disk 
interface controls are generated through this logic. 
The internal device timing is generated from an exter- 
nal crystal clock. 

The FD179X has two diff erent m odes of oper ation 
according to the state of DDEN. When DDE N = 
double density (MFM) is assumed. When DDEN 
= 1, single density (FM) Is assumed. 1792 & 1794 are 
single density only. 



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FD179X BLOCK DIAGRAM 



Floppy Disk Controller Devices 



1-57 



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AM Detector - The address mark detector detects ID, 
data and Index address marks during read and write 
operations. 

PROCESSOR INTERFACE 

The interface to the processor is a ccom plished 
through the eight Data Access Lines (DAL) and 
associated control signals. The DAL are used to 
transfer Data, Status, and Control words out of, or 
into the FD179X. The DAL are three state buffers 
that are enabled as outpjLJt_drivers when Chip Select 
(CS) and Read Enable (RE) are active (low logic 
state) or act as input receivers when CS and Write 
Enable (WE) are active. 

When transfer of data with the Floppy Disk Controller 
is required by the host processor, the device address 
is decoded and CS is made low. The address bits A1 
and AO, combined with the signals RE during a 
Read operation or WE during a Write operation are 
interpreted as selecting the following registers: 



A1 - AO READ (RE) 



WRITE (WE) 



Status Regiser 

1 Track Register 

1 Sector Register 
1 1 Data Register 



Command Register 
Track Register 
Sector Register 
Data Register 



During Direct Memory Access (DMA) types of data 
transfers between the Data Register of the DF179X 
and the processor, the Data Request (DRQ) output 
is used in Data Transfer control. This signal also 
appears as status bit 1 during Read and Write 
operations. 

On Disk Read operations the Data Request is 
activated (set high) when an assembled serial input 
byte is transferred in parallel to the Data Register. This 
bit is cleared when the Data Register is read by the 
processor. If the Data Register is read after one or 
more characters are lost, by having new data transfer- 
red into the register prior to processor readout, the 
Lost Data bit is set in the Status Register. The Read 
operation continues until the end of sector is reached. 

On Disk Write operations the data Request is 
activated when the Data Register transfers its con- 
tents to the Data Shift Register, and requires a new 
data byte. It is reset when the Data Register is loaded 
with new data by the processor. If new data is not 
loaded at the time the next serial byte is required by 
the Floppy Disk, a byte of zeroes is written on the 
diskette and the Lost Data bit is set in the Status 
Register. 



At the completion of every command an INTRO is 
generated. INTRO is reset by either reading the status 
register or by loading the command register with a 
new command. In addition, INTRO is generated if a 
Force Interrupt command condition is met. 

The 179X ha s two m odes of opera tion ac cording to 
the state of DDEN (Pin 37). When DDEN = 1, 
single density is selected. In either case, the CLK 
Input (Pin 24) Is at 2 MHz. However, when interfac- 
ing with the mini-floppy, the CLK input is set at 1 MHz 
for both single density and double density. 

GENERAL DISK READ OPERATIONS 

Sector lengths of 128, 256, 512 or 1024 are obt ainable 
in either FM or MFM formats. For FM, DDEN 
should be placed to logical "1." For MFM formats, 
DDEN should be placed to a logical "0." Sector 
lengths are determined at format time by the fourth 
byte in the "ID" field. 



Sector Length Table* 



Sector Length 
Field (hex) 



Number of Bytes 
in Sector (decimal) 



GO 
01 
02 
03 



128 
256 
512 
1024 



* 1795/97 may vary - see command summary. 

The number of sectors per track as far as the FD179X 
is concerned can be from 1 to 255 sectors. The 
number of tracks as far as the FD179X is concerned 
is from to 255 tracks. For IBM 3740 compatibility, 
sector lengths are 128 bytes with 26 sectors per track. 
For System 34 compatibility (MFM), sector lengths are 
256 bytes/sector with 26 sectors/track; or lengths of 
1024 bytes/sector with 8 sectors/track. (See Sector 
Length Table.) 

For read operations in 8" double density the FD179X 
requires RAW READ Data (Pin 27) signal which is a 
200 ns pulse per flux transition and a Read clock 
(RCLK) signal to indicate flux transition spacings. THE 
RCLK (Pin 26) signal is provided by some drives but 
if not it may be derived externally by Phase lock loops, 
one shots, or counter techniques. In addition, a Read 
Gate Signal is provided as an output (Pin 25) on 
1791/92/93/94 which can be used to inform phase lock 
loops when to acquire synchronization. When reading 
from the media in FM. RG is made true when 



1-58 



Floppy Disk Controller Devices 



2 bytes of zeroes are detected. The FD179X must find 
an address mark within the next 10 bytes; otherwise 
RG is reset and the search for 2 bytes of zeroes 
begins all over again. If an address mark is found 
within 10 bytes, RG remains true as long as the 
FD179X is deriving any useful information from the 
data stream. Similarly for MFM, RG is made active 
when 4 bytes of "00" or "FF" are detected. The 
FD179X must find an address mark within the next 
16 bytes, otherwise RG is reset and search resumes. 



During read operations (WG = 0), the VFOE (Pin 
33) is provided for phase lock loop synchronization. 
VFOE will go active low when: 

a) Both HLT and HLD are True 

b) Settling Time, if programmed, has expired 

c) The 179X is inspecting data off the disk 



If WFVFOE is not used, leave open or tie to a 10K 
resistor to + 5. 

GENERAL DISK WRITE OPERATION 

When writing is to take place on the diskette the Write 
Gate (WG) output is activated, allowing current to flow 
into the Read /Write head. As a precaution to 
erroneous writing the first data byte must be loaded 
into the Data Register in response to a Data Request 
from the FD179X before the Write Gate signal can be 
activated. 



Writing is inhibited when the Write Protect input is 
a logic low, in which case any Write command is 
immediately terminated, an interrupt is generated and 
the Write Protect status bit is set. The Write Fault 
Input, when activated, signifies a writing fault condi- 
tion detected in disk drive electronics such as failure 
to detect write current flow when the Write Gate is 
activated. On detection of this fault the FD179X ter- 
minates the current command, and sets the Write 
Fault bit (bit 5) in the Status Word. The Write Fault 
Input should be made inactive when the Write Gate 
output becomes inactive. 



For write operations, the FD179X provides Write Gate 
(Pin 30) and Write Data (Pin 31) outputs. Writ e data 
consists of a series of 500 ns pul ses in FM (DDEN 
= 1) and 200 ns pulses in MFM (DDEN = 0). 
Write Data provides the unique address marks in both 
formats. 

Also during write, two additional signals are provided 
for write precompensation. These are EARLY (Pin 17) 
and LATE (Pin 18). EARLY is active true when the WD 
pulse appearing on (Pin 30) is to be written EARLY. 
LATE is active true when the WD pulse is to be writ- 
ten LATE. If both EARLY and LATE are low when the 
WD pulse is present, the WD pulse is to be written 
at nominal. Since write precompensation values vary 
from disk manufacturer to disk manufacturer, the 
actual value is determined by several one shots or 
delay lines which are located external to the FD 179X. 
The write precompensation signals EARLY and LATE 
are valid for the duration of WD in both FM and MFM 
formats. 

READY 

Whenever a Read or Write command (Type II or ill) 
is received the FD179X samples the Ready input. If 
this input is logic low the command is not executed 
and an interrupt is generated. All Type I commands 
are performed regardless of the state of the Ready 
input. Also, whenever a Type II or III command is 
received, the TG43 signal output is updated. 

COMMAND DESCRIPTION 

The FD179X will accept eleven commands. Command 
words should only be loaded in the Command 
Register when the Busy status bit is off (Status bit 
0). The one exception is the Force Interrupt command. 
Whenever a command is being executed, the Busy 
status bit is set. When a command is completed, an 
interrupt is generated and the Busy status bit is reset. 
The Status Register indicates whether the completed 
command encountered an error or was fault free. For 
ease of discussion, commands are divided into four 
types. Commands and types are summarized in 
Table 1. 



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TABLE 1. COMMAND SUMMARY 



A. Commands for Models 


: 1791, 1792, " 


1793, 1794 








B. Commands for Models 


1795 


, 1797 










Bits 










Bits 






Type Command 


7 


6 


5 


4 3 


2 


1 





7 


6 5 4 3 


2 


1 


1 Restore 











h 


V 


ri 


rn 





h 


V 


ri ro 


1 Seek 











1 h 


V 


ri 


rn 





1 h 


V 


ri ro 


1 Seek 











1 h 


V 


ri 


rn 





1 T h 


V 


ri ro 


1 Step-in 





1 





T h 


V 


ri 


rn 





1 T h 


V 


ri ro 


1 Step-out 





1 


1 


T h 


V 


ri 


rn 





1 1 T h 


V 


ri ro 


II Read Sector 










m S 


E 


C 







m L 


E 


U 


II Write Sector 







1 


m S 


E 


C 


an 




1 m L 


E 


U ao 


III Read Address 




1 








E 










10 


E 


U 


III Read Track 




1 


1 





E 










110 


E 


U 


III Write Track 




1 


1 


1 


E 










1110 


E 


U 


IV Force Interrupt 




1 





1 I3 


I2 


I1 


lo 




1 1 I3 


I2 


I1 lo 



Floppy Disk Controller Devices 



1-59 



TABLE 2. FLAG SUMMARY 



FLAG SUMMARY 



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Command 


Bit 






Type 


No(s) 




Description 


1 


0, 1 


r^ro = Stepping Motor Rate 
See Table 3 for Rate Summary 




1 


2 


V = Track Number Verify Flag 


V = 0,No verify 

V = 1, Verify on destination track 


1 


3 


h = Head Load Flag 


h = 1,Load head at beginning 
h =: Unload head at beginning 


1 


4 


T = Track Update Flag 


T = 0,No update 

T = 1, Update track register 


II 





ag = Data Address Mark 


ao = 0,FB(DAM) 

ao = 1,F8(deleted DAM) 


II 


1 


C = Side Compare Flag 


C =: 0,Disable side compare 
C = 1, Enable side compare 


II & III 


1 


U = Update SSO 


U = 0,Update SSO to 
U = 1, Update SSO to 1 


II & III 


2 


E = 15 MS Delay 


E =: 0,No 15 MS delay 
E = 1,15 MS delay 


II 
II 

II 


3 
3 

4 


S = Side Compare Flag 
L = Sector Length Flag 




S = 0,Compare for side 
S = 1, Compare for side 1 






LSB's Sector Length in ID Field 
00 01 10 11 




L= 256 512 1024 128 


L= 1 128 256 512 1024 


m = Multiple Record Flag 


m = 0,Single record 
m = 1, Multiple records 




IV 


0-3 


Ix = Interrupt Condition Flags 

Iq = 1 Not Ready To Ready Transition 

li =1 Ready To Not Ready Transition 

12 = 1 Index Pulse 

13 =1 Immediate Interrupt, Requires A Reset 
I3-I0 = Terminate With No Interrupt (INTRQ) 



NOTE: See Type IV Command Description for further information. 



1-60 



Floppy Disk Controller Devices 



TYPE I COMMANDS 

The Type I Commands include the Restore, Seek, 
Step, Step-in, and Step-Out commands. Each of the 
Type I Commands contains a rate field {Tq r■^), which 
determines the stepping motor rate as defined in 
Table 3. 

A 2/xs (MFM) or 4/iS (FM) pulse is provided as an out- 
put to the drive. For every step pulse issued, the drive 
moves one track location in a direction determined 
by the direction output. The chip v^ill step the drive 
in the same direction it last stepped unless the com- 
mand changes the direction. 

The Direction signal is active high when stepping in 
and low when stepping out. The Direction signal is 
valid 12/iS before the first stepping pulse is generated. 

The rates (shown in Table 3) can be applied to a Step- 
Direction Motor through the device interface. 

TABLE 3. STEPPING RATES 



CLK 


2 MHz 


2 MHz 


1 MHz 


1 MHz 


2 MHz 


1 MHz 


DDEN 





1 





1 


X 


X 


R1 RO 


TEST = 1 TEST = 1 TEST = 1 TEST = 1 TEST = TEST = 





3 ms 


3 ms 


6 ms 


6 ms 


185/iS 


368^3 


1 


6 ms 


6 ms 


12 ms 


12 ms 


190^S 


38C,iS 


1 


10 ms 


10 ms 


20 ms 


20 ms 


^98|xS 


396/iS 


1 1 


15 ms 


15 ms 


30 ms 


30 ms 


208/iS 


416;iS 



After the last directional step an additional 15 
milliseconds of head settling time takes place if the 
Verify flag is set in Type I commands. Note th at this 
time doubles to 30 ms for a 1 MHz clock. If TEST 
= 0, there is zero settling time. There is also a 15 
ms head settling time if the E flag is set in any Type 
II or III command. 

When a Seek, Step or Restore command is executed 
an optional verification of Read-Write head position 
can be performed by setting bit 2 (V = 1) in the com- 
mand word to a logic 1. The verification operation 
begins at the end of the 15 millisecond settling time 
after the head is loaded against the media. The track 
number from the first encountered ID Field is com- 
pared against the contents of the Track Register. If 
the track numbers compare and the ID Field Cyclic 
Redundancy Check (CRC) is correct, the verify opera- 
tion is complete and an INTRO is generated with no 
errors. If there is a match but not a valid CRC, the 
CRC error status bit is set (Status bit 3), and the next 
encountered ID field is read from the disk for the 
verification operation. 

The FD179X must find an ID field with correct track 
number and correct CRC within 5 revolutions of the 
media; otherwise the seek error is set and an INTRO 
is generated. If V = 0, no verification is performed. 

The Head Load (HLD) output controls the movement 
of the read /write head against the media. HLD is 
activated at the beginning of a Type I command if 
the h flag is set (h = 1), at the end of the Type I com- 
mand if the verify flag (V = 1), or upon receipt of any 



Type II or III command. Once HLD is active it remains 
active until either a Type I command is received with 
(h = and V = 0); or if the FD179X is in an idle state 
(non-busy) and 15 index pulses have occurred. 

Head Load Timing (HLT) is an input to the FD179X 
which is used for the head engage time. When HLT 
= 1, the FD179X assumes the head is completely 
engaged. The head engage time is typically 30 to 100 
ms depending on drive. The low to high transition on 
HLD is typically used to fire a one shot. The output 
of the one shot is then used for HLT and supplied 
as an input to the FD179X. 



HLD J- 



f- 



HLT (FROM ONE SHOT) 



HEAD LOAD TIMING 

When both HLD and HLT are true, the FD179X will 
then read from or write to the media. The "and" of 
HLD and HLT appears as status Bit 5 in Type 1 status. 

In summary for the Type I commands: if h = and 
V = 0, HLD is reset. If h := 1 and V = 0, HLD is set 
at the beginning of the command and HLT is not 
sampled nor is there an internal 15 ms delay. If h = 
and V = 1, HLD is set near the end of the com- 
mand, an internal 15 ms occurs, and the FD179X waits 
for HLT to be true. If h = 1 and V = 1, HLD is set 
at the beginning of the command. Near the end of 
the command, after all the steps have been issued, 
an internal 15 ms delay occurs and the FD 179X then 
waits for HLT to occur. 

For Type II and III commands with E flag off, HLD 
is made active and HLT is sampled until true. With 
E flag on, HLD is made active, an internal 15 ms delay 
occurs and then HLT is sampled until true. 

RESTORE (SEEK TRACK 0) 

Upon receipt of this c oman d the Track 00 
(TROO) input is sampled. If TROO is active low indi- 
cating the ReadAA/rite head is positioned over track 
0, the Track Register is l oaded with zeroes and an 
interrupt is generated. If TROO is not active low, 
stepping pulses (pins 15 to 16) at a rate specified by 
the r-jro field are issued until the TROO input is acti- 
vated. At this time the Track Register is load ed wit h 
zeroes and an interrupt is generated. If the TROO 
input does not go active low after 255 stepping pulses, 
the FD179X terminates operation, interrupts, and sets 
the Seek error status bit, providing the V flag is set. 
A verification operation also takes place if the V flag 
is set. The h bit allows the head to be loaded at the 
start of command. Note that the Restore command 
is executed when MR goes from an active to an 
inactive state and that the DRQ pin stays low. 



CO 

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Floppy Disk Controller Devices 



1-61 



CO 

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^ VES 




SET 
DIRECTION 














VES 


RESET 
DIRECTION 








YES 




> 






^ 



NO .-.RESTORE 




U k) 



TYPE I COMMAND FLOW 

SEEK 

This command assumes that the Track Register con- 
tains the tracl< number of the current position of the 
Read/Write head and the Data Register contains 
the desired tracl< number. The FD179X will update the 
Track register and issue stepping pulses in the 
appropriate direction until the contents of the Track 
register are equal to the contents of the Data Register 
(the desired track location). A verification operation 
takes place if the V flag is on. The h bit allows the 
head to be loaded at the start of the command. An 
interrupt is generated at the completion of the com- 
mand. An interrupt is generated at the completion of 
the command. Note: When using multiple drives, the 
register must be updated for the drive selected before 
seeks are issued. 




RESET DIRECTION 




SET DIRECTION 









TYPE I COMMAND FLOW 
STEP 

Upon receipt of this command, the FD179X issues 
one stepping pulse to the disk drive. The stepping 
motor direction is the same as in the previous step 
command. After a delay determined by the r-iro field, 
a verification takes place if the V flag is on. If the U 
flag is on, the Track Register is updated. The h bit 
allows the head to be loaded at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. 

STEP-IN 

Upon receipt of this command, the FD179X issues 
one stepping pulse in the direction towards track 76. 
If the U flag is on, the Track Register is incremented 
by one. After a delay determined by the r-iro field, a 
verification takes place if the V flag is on. The h bit 
allows the head to be loaded at the start of the 



1-62 



Floppy Disk Controller Devices 



command. An interrupt is generated at the comple- 
tion of the command. 

STEP-OUT 

Upon receipt of this command, the FD179X issues 
one stepping pulse in the direction towards track 0. 
If the U flag is on, the Track Register is decremented 
by one. After a delay determined by the r-iTo field, a 
verification takes place if the V flag is on. The h bit 
allows the head to be loaded at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. 

EXCEPTIONS 

On the 1795/7 devices, the SSO output is not 
affected during Type I commands, and an internal 
side compare does not take place when the (V) Verify 
Flag is on. 



VERIFY 
SEQUENCE 




NTRO BESET BUSY 



9 








y 



TYPE I COMMAND FLOW 

TYPE II COMMANDS 

The Type II Commands are the Read Sector and Write 
Sector commands. Prior to loading the Type II Com- 
mand into the Command Register, the computer must 



load the Sector Register with the desired sector 
number. Upon receipt of the Type II command, the 
busy status Bit is set. If the E flag = 1 (this is the 
normal case) HLD is made active and HLT is sampled 
after a 15 msec delay. If the E flag is 0, the head is 
loaded and HLT sampled with no 15 msec delay. 

When an ID field is located on the disk, the FD179X 
compares the Track Number on the ID field with the 
Track Register. If there is not a match, the next 
encountered ID field is ready and a comparison is 
again made. If there was a match, the Sector Number 
of the ID field is compared with the Sector Register. 
If there is not a Sector match, the next encountered 
ID field is read off the disk and comparisons again 
made. If the ID field CRC is correct, the data field is 
then located and will be either written into, or read 
from depending upon the command. The FD179X 
must find an ID field with a Track number. Sector 
number, side number, and CRC within four revolutions 
of the disk; otherwise, the Record Not Found status 
bit is set (Status bit 3) and the command is terminated 
with an interrupt. 




(O 

X 

I 

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TYPE II COMMAND 



Floppy Disk Controller Devices 



1-63 



■>4 
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Each of the Type II Commands contains an (m) flag 
which determines if multiple records (sectors) are to 
be read or written, depending upon the command. If 
m = 0, a single sector is read or written and an inter- 
rupt is generated at the completion of the command. 
If m = 1, multiple records are read or written with 
sector register internally updated so that an address 
verification can occur on the next record. The WD179X 
will continue to read or write multiple records and 
update the sector register in numerical ascending 
sequence until the sector register exceeds the 
number of sectors on the track or until the Force Inter- 
rupt command is loaded into the Command Register, 
which terminates the command and generates an 
interrupt. 

For example: If the FD 179X is instructed to read sec- 
tor 27 and there are only 26 on the track, the sector 
register exceeds the number available. The FD179X 
will search for 5 disk revolutions, interrupt out, reset 
busy, and set the Record Not Found status bit. 

The Type II commands for 1791-94 also contain side 
select compare flags. When C = (Bit 1) no side 
comparison is made. When C = 1, the LSB of the 
side number is read off the ID field of the disk and 
compared with the contents of the (S) flag (Bit 3). If 
the S flag compares with the side number recorded 
in the ID field, the FD179X continues with the ID 
search. If a comparison is not made within 5 index 
pulses, the interrupt line is made active and the 
Record Not Found status bit is set. 




The Type II and III commands contain a side select 
flag (Bit 1). When U = 0, SSO is updated to 0. Similar- 
ly, U = 1 updates SSO to 1. The chip compares the 
SSO to the ID field. If they do not compare within 5 
revolutions the interrupt line is made active and the 
RNF status bit is set. 

The 1795/7 READ SECTOR and WRITE SECTOR 
commands include a 'L' flag. The 'L' flag, in conjunc- 
tion with the sector length byte of the ID Field, allows 
different byte lengths to be implemented in each sec- 
tor. For IBf\/l compatability. the 'U flag should be set 
to a one. 

READ SECTOR 

Upon receipt of the Read Sector command, the head 
is loaded, the Busy status bit set, and when an ID 
field is encountered that has the correct track number, 
correct sector number, correct side number, and cor- 
rect CRC, the data field is presented to the computer. 
The Data Address Mark of the data field must be 
found within 30 bytes in single density and 43 bytes 
in double density of the last ID field CRC byte; if not, 
the ID filed is searched for and verified again followed 
by the Data Address Mark search. If after 5 revolu- 
tions the DAM cannot be found, the Record Not 
Found status bit is set and the operation is ter- 
minated. When the first character or byte of the 



READ SECTOR 
SEQUENCE 




CiSuSD 



SECTOR REG 



^^ 



TYPE II COMMAND 



TYPE II COMMAND 



1-64 



Floppy Disk Controller Devices 



WRITE SECTOR 
SEQUENCE 



DELAY 2 BYTES OF GAP 

T 




(NTHQ RESET BUSY J 
sei LOST DATA / 



DELAY 1 BYTE OF GAP 



DELAY 11 BYTES 



WRITE DATA AM 
ACCORDING TO AO FIELD 
OF WRITE COMMAND 



DR TO DSH. SET DRQ 




STATUS 
BITS 



TYPE II COMMAND 

data field has been shifted through the DSR, it is 
transferred to the DR, and DRQ is generated. When 
the next byte is accumulated in the DSR, it is transfer- 
red to the DR and another DRQ is generated. If the 
computer has not read the previous contents of the 
DR before a new character is transferred that 
character is lost and the Lost Data Status bit is set. 
This sequence continues until the complete data field 
has been input to the computer. If there is a CRC error 
at the end of the data field, the CRC error status bit 
is set, and the command is terminated (even if it is 
a multiple record command). 

At the end of the Read operation, the type of Data 
Address Mark encountered in the data field is 
recorded in the Status Register (Bit 5) as shown: 



1 Deleted Data Mark 

Data Mark 

WRITE SECTOR 

Upon receipt of the Write Sector command, the head 
is loaded (HLD active) and the Busy status bit is set. 
When an ID field is encountered that has the correct 
track number, correct sector number, correct side 
number, and correct CRC, a DRQ is generated. The 
FD179X counts off 11 bytes in single density and 22 
bytes in double density from the CRC field and the 
Write Gate (WG) output is made active if the DRQ is 
serviced (i.e., the DR has been loaded by the com- 
puter). If DRQ has not been serviced, the command 
is terminated and the Lost Data status bit is set. If 
the DRQ has been serviced, the WG is made active 
and six bytes of zeroes in single density and 12 bytes 
in double density are then written on the disk. At this 
time the Data Address Mark is then written on the 
disk as determined by the aO field of the command 
as shown below: 

ao Data Address Mark (Bit 0) 

1 Deleted Data Mark 
Data Mark 

The FD179X then writes the data field and generates 
DRQ's to the computer. If the DRQ is not serviced 
in time for continuous writing the Lost Status Data 
Bit is set and a byte of zeroes is written on the disk. 
The command is not terminated. After the last data 
byte has been written on the disk, the two-byte CRC 
is computed internally and written on the disk 
followed by one byte of logic ones in FM or in MFM. 
The WG output is then deactivated. For a 2 MHz clock 
the INTRQ will set 8 to 12^sec after the last CRC byte 
is written. For partial sector writing, the proper 
method is to write the data and fill the balance with 
zeroes. By letting the chip fill the zeroes, errors may 
be masked by the lost data status and improper CRC 
Bytes. 

TYPE III COMMANDS 

READ ADDRESS 

Upon receipt of the Read Address command, the head 
is loaded and the Busy Status Bit is set. The next 
encountered ID field is then read in from the disk, and 
the six data bytes of the ID field are assembled and 
transferred to the DR, and a DRQ is generated for 
each byte. The six bytes of the ID field are shown 
below: 



TRACK 
ADDR 


SIDE 
NUMBER 


SECTOR 
ADDRESS 


SECTOR 
LENGTH 


CRC 

1 


CRC 
2 


1 


2 


3 


4 


5 


6 



Although the CRC characters are transferred to the 
computer, the FD179X checks for validity and the CRC 
error status bit is set if there is a CRC error. The Track 
Address of the ID field is written into the sector 



>< 

o 

N3 



Floppy Disk Controller Devices 



1-65 



X 

I 

o 
to 



register so that a comparison can be made by the 
user. At the end of the operation an interrupt is 
generated and the Busy Status is reset. 

READ TRACK 

Upon receipt of the READ track command, the head 
is loaded, and the Busy Status bit is set. Reading 
starts with the leading edge of the first encountered 
index pulse and continues until the next index pulse. 
All Gap, Header, and data bytes are assembled and 
transferred to the data register and DRQ's are 
generated for each byte. The accumulation of bytes 
is synchronized to each address mark encountered. 
An interrupt is generated at the completion of the 
command. 



This command has several characteristics which 
make it suitable for diagnostic purposes. They are: 
the Read Gate is not activated during the command; 
no CRC checking is performed; gap information is 
included in the data stream; the internal side com- 
pare is not performed; and the address mark detec- 
tor is on for the duration of the command. Because 
the A.M. detector is always on, write splices or noise 
may cause the chip to look for an A.M. If an address 
mark does not appear on schedule the Lost Data 
status flag is set. 

The ID A.M., ID field, ID CRC bytes, DAM, Data, and 
Data CRC Bytes for each sector will be correct. The 
Gap Bytes may be read incorrectly during write-splice 
time because of synchronization. 




SET BUSY RESET DRO 
LOST OAT* STATUS 
BITS 4 5 




_^ INTRO ^ 

^^ RESET BUSY J 





I 



TYPE III COMMAND WRITE TRACK 



TYPE III COMMAND WIRTE TRACK 



1-66 



Floppy Disk Controller Devices 



CONTROL BYTES FOR INITIALIZATION 



DATA PATTERN 


FD179X INTERPRETATION 


FD1791 /3 INTERPRETATION 


IN DR (HEX) 


IN FM (DDEN = 1) 


IN MFM (DDEN = 0) 


00 thru F4 


Write 00 thru F4 with CLK = FF 


Write 00 thru F4,in MFM 


F5 


Not Allowed 


Write A^* in MFM, Present CRC 


F6 


Not Allowed 


Write C2** in MFM 


F7 


Generate 2 CRC bytes 


Generate 2 CRC bytes 


F8 thru FB 


Write F8 thru FB, CLK = C7, Preset CRC 


Write F8 thru FB, in MFM 


FC 


Write FC with CLK = D7 


Write FC in MFM 


FD 


Write FD with CLK = FF 


Write FD in MFM 


FE 


Write FE, CLK = C7, Preset CRC 


Write FE in MFM 


FF 


Write FF with CLK = FF 


Write FF in MFM 



X 
O 
N) 



* Missing clock transition between bits 4 and 5. 
WRITE TRACK FORMATTING THE DISK 

(Refer to section on Type III commands for flow 
diagrams.) 

Formatting the disk is a relatively simple task when 
operating programmed I / O or when operating under 
DMA with a large amount of memory. Data and gap 
information must be provided at the computer inter- 
face. Formatting the disk is accomplished by posi- 
tioning the R / W head over the desired track number 
and issuing the Write Track command. 

Upon receipt of the Write Track command, the head 
is loaded and the Busy Status bit is set. Writing starts 
with the leading edge of the first encountered index 
pulse and continues until the next index pulse, at 
which time the interrupt is activated. The Data 
Request is activated immediately upon receiving the 
command, but writing will not start until after the first 
byte has been loaded into the Data Register. If the 
DR has not been loaded by the time the index pulse 
is encountered the operation is terminated making 
the device Not Busy, the Lost Data Status Bit is set, 
and the interrupt is activated. If a byte is not present 
in the DR when needed, a byte of zeroes is 
substituted. 

This sequence continued from one index mark to the 
next index mark. Normally, whatever data pattern 
appears in the data register is written on the disk with 
a normal clock pattern. However, if the FD179X 
detects a data pattern of F5 through FE in the data 
register, this is interpreted as data address marks with 
missing clocks or CRC generation. 

The CRC generator is initialized when any data byte 
from F8 to FE is about to be transferred from the DR 
to the DSR in FM or by receipt of F5 in MFM. An F7 
pattern will generate two CRC characters in FM or 
MFM. As a consequence, the patterns F5 through FE 
must not appear in the gaps, data fields, of ID fields. 
Also, CRC's must be generated by an F7 pattern. 
Disks may be formatted in IBM 3740 or System 34 
formats with sector lengths of 128, 256, 512, or 1024 
bytes. 

TYPE IV COMMANDS 

The Forced Interrupt command is generally used to 
terminate a multiple sector read or write command 



**Missing clock transition between bits 3 and 4. 

or to insure Type I status in the status register. This 
command can be loaded into the command register 
at any time. If there is a current command under 
execution (busy status bit set) the command will be 
terminated and the busy status bit reset. 

The lower four bits of the command determine the 
conditional interrupt as follows: 

Iq = Not-Ready to Ready Transition 
1-1 = Ready to Not-Read Transition 

12 = Every Index Pulse 

13 = Immediate Interrupt 

The conditional interrupt is enabled when the cor- 
responding bit positions of the command I3-I0) are 
set to a 1. Then, when the condition for interrupt is 
met, the INTRO line will go high signifying that the 
condition specified has occurred. If Is-Iq are all set to 
zero (HEX DO), no interrupt will occur but any com- 
mand presently under execution will be immediately 
terminated. When using the immediate interrupt con- 
dition (I3 = 1) an interrupt will be immediately 
generated and the current command terminated. 
Reading the status or writing to the command register 
will not automatically clear the interrupt. The HEX DO 
is the only command that will enable the immediate 
interrupt (HEX D8) to clear on a subsequent load com- 
mand register or read status register operation. Follow 
a HEX D8 with DO command. 

Wait 8 micro sec (double density) or 16 micro sec 
(single density) before issuing a new command after 
issuing a forced interrupt (times double when clock 
= 1 MHz). Loading a new command sooner than this 
will nullify the forced interrupt. 

Forced interrupt stops any command at the end of 
an internal micro-instruction and generates INTRO 
when the specified condition is met. Forced interrupt 
will wait until ALU operations in progress are com- 
plete (CRC calculations, compares, etc.). 

More than one condition may be set at a time. If for 
example, the READY TO NOT-READY condition (h = 
1) and the Every Index Pulse (I2 = 1) are both set, the 
resultant command would be HEX "DA". The "OR" 
function is performed so that either a READY TO 
NOT-READY or the next Index Pulse will cause an in- 
terrupt condition. 



Floppy Disk Controller Devices 



1-67 



( 


ENTER 


1 








SET BUSY 

RESET STATUS 

BITS 2, 4, 5 





INTRQ 
RESET BUSY 



3 





[YES 

1 ■ 






DELAY 15MS- 












f^ HLT=1 ^\, 


NO 



•|fTEST=^.NODELAY 
If TEST=1 and CLK=1 MHZ, 30 MS DELAY 



READ TRACK 
SEQUENCE 




INDEX 
PULSE 



SHIFT ONE BIT 
INTO DSR 



TRANSFER 
DSR TO DR 




J SET INTRQ ^ 

"^ RESET BUSY J 



SET LOST 
DATA BIT 



TYPE III COMMAND 

Read Track / Address 



1-68 



Floppy Disk Controller Devices 




READ ADDRESS 
SEQUENCE 



RESET BUSY 
SET INTRO 
SET RNF 



) 



SHIFT 1 BYTE 
INTO DSR 



TRANSFER 
BYTE TO DR 




TRANSFER TRACK 

NUMBER TO SECTOR 

REGISTOR 




SETCRC 
ERROR BIT 



c 



SET INTRO 
RESET BUSY 



:) 



TYPE III COMMAND 

Read Track / Address 



STATUS REGISTER 

Upon receipt of any command, except the Force Inter- 
rupt command, the Busy Status bit is set and the rest 
of the status bits are updated or cleared for the new 
command. If the Force Interrupt Command is received 
when there is a current command under execution, 
the Busy status bit is reset, and the rest of that status 
bits are unchanged. If the Force Interrupt command 
is received when there is not a current command 
under execution, the Busy Status bit is reset and the 
rest of the status bits are updated or cleared. In this 
case. Status reflects the Type I commands. 

The user has the option of reading the status register 
through program control or using the DRQ line with 
DMA or interrupt methods. When the Data register 
is read the DRQ bit in the status register and the DRQ 
line are automatically reset. A write to the Data 
register also causes both DRQ's to reset. 

The busy bit in the status may be monitored with a 
user program to determine when a command is com- 
plete, in lieu of using the INTRQ line. When using the 
INTRQ, a busy status check is not recommended 
because a read of the status register to determine 
the condition of busy will reset the INTRQ line. 

The format of the Status Register is shown below: 



BITS 


7 


6 


5 


4 


3 


2 


1 





S7 


S6 


S5 


S4 


S3 


S2 


SI 


so 



Status varies according to the type of command 
executed as shown in Table 4. 

Because of internal sync cycles, certain time delays 
must be observed when operating under programmed 
I / O. They are: (times double when clock = 1 MHz) 



Operation 


Next Operation 


Delay 
FM 


Req'd. 
MFM 


Write to 
Command Reg. 


Read Busy Bit 
(Status Bit 0) 


12,iS 


6/xS 


Write to 
Command Reg. 


Read Status 
Bits 1-7 


28/iS 


Uns 


Write Any 
Register 


Read From Diff. 
Register 









IBM 3740 FORMAT ■ 128 BYTES /SECTOR 

Shown below is the IBM single-density format with 
128 bytes / sector. In order to format a diskette, the 
user must issue the Write Track command, and load 
the data register with the following values. For every 
byte to be written, there is one Data Request. 



->4 
CO 

X 

■ 

o 

N3 



Floppy Disk Controller Devices 



1-69 



■Tl 
O 

X 
o 

N3 



IBM 3740 FORMAT • 128 BYTES / SECTOR 

Shown below is the IBM single-density format with 
128 bytes / sector. In order to format a diskette, the 
user must issue the Write Track command, and load 
the data register with the following values. For every 
byte to be written, there is one Data Request. 



Shown below is the IBM dual-density format with 256 
bytes / sector. In order to format a diskette the user 
must issue the Write Track command and load the 
data register with the following values. For every byte 
to be written, there is one data request. 



NUMBER 


HEX VALUE OF 


OF BYTES 


BYTE WRITTEN 


40 
6 


FF (or 00)^ 
00 


1 
* 26 
6 


FC (Index Mark) 
FF (or 00)^ 
00 




FE (ID Address Mark) 
Track Number 


11 
6 


Side Number (00 or 01) 
Sector Number (1 thru 1A) 
00 (Sector Length) 
F7 (2 CRC's written) 
FF (or 00)ses E5)1 
00 


128 

27 
247** 


FB (Data Address Mark) 
Data (IBM uses E5) 
F7 (2 CRC's written) 
FF (or 00)^ 
FF (or 00) • 



*Write bracketed field 26 times. 

**Continue writing until FD179X interrupts out. 

Approx. 247 bytes. 

1 -Optional '00' on 1795/7 only. 



NUMBER 


HEX VALUE OF 


OF BYTES 


BYTE WRITTEN 


80 


4E 


12 


00 


3 
1 
* 50 


F6 (Writes C2) 
FC (Index Mark) 
4E 


12 


00 


3 

1 
1 
1 
1 
1 
1 
22 


F5 (Writes A1) 
FE (ID Address Mark) 
Track Number (0 thru 4C) 
Side Number (0 or 1) 
Sector Number (1 thru 1A) 
01 (Sector Length) 
F7 (2 CRC's written) 
4E 


12 


00 


3 

1 
256 


F5 (Writes A1) 

FB (Data Address Mark) 

DATA 


1 
54 


F7 (2 CRC's written) 
4E 


598** 


4E 



*Write bracketed field 26 times. 

**Continue writing until FD179X interrupts out. 

Approx. 598 bytes. 



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IBM TRACK FORMAT 



1-70 



Floppy Disk Controller Devices 



1. NON-IBM FORMATS 

Variations in the IBM formats are possible to a limited 
extent if the following requirements are met: 

1) Sector size must be 128, 256, 512, 1024 bytes. 

2) Gap 2 cannot be vaired from the IBM format. 

3) 3 bytes of A1 must be used in MFM. 

In addition, the Index Address Mark is not required 
for operation by the FD179X. Gap 1, 3, and 4 lengths 
can be as short as 2 bytes for FD179X operation, 
however PLL lock up time, motor speed variation, 
write-splice area, etc. will add more bytes to each gap 
to achieve proper operation. It is recommended that 
the IBM format be used for highest system reliability. 





FM 


MFM 


Gap 1 


16 bytes FF 


32 bytes 4E 


Gap II 


11 bytes FF 


22 bytes 4E 


* 


6 bytes 00 


12 bytes 00 
3 bytes A1 


Gap III** 


10 bytes FF 
4 bytes 00 


24 bytes 4E 
8 bytes 00 
3 bytes A1 


Gap IV 


16 bytes FF 


16 bytes 4E 



*Byte counts must be exact. 

**Byte counts are minimum, except exactly 3 bytes 

of A1 must be written. 











. 16- OH 32- 




1 




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1 VON 








1 






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— 








Thld ■■■ '""■- 1 


AO Al CS 












^ 






— — Tre —m~ 














— 


TSET 


^DACC 


1- 










DATA 




' 












-m- 'DON -•- 




NOTE 1 CSM*y BE PERMANENTLV TIED LOW IF DESIRED 




•TIME DOUBLES WHEN CLOCK . \UHl 




1 SERVICE (WORST CASE! 
•FM 27 5uS 
•MFM 13 5uS 




DRQ RISING EDGE: INDICATES THAT THE DATA REGISTER HAS ASSEMBLED 
DATA. 




DRQ FAL' ING EDGE: INDICATES THAT THE DATA REGISTER WAS READ 




INTRO RISING EDGE: OCCURS AT END OF COMMAND 




INTRO FALLING EDGE: INDICATES THAT THE STATUS REGISTER WAS READ. 



CO 

X 

I 

o 
to 



READ ENABLE TIMING 



TIMING CHARACTERISTICS 

Ta = 0°C to 70°C, Vdd = +12V±.6V, Vgs = OV, Vcc 
READ ENABLE TIMING 



+ 5V ± .25V 



SYMBOL 


CHARACTERISTIC 


MIN. 


TYP. 


MAX. 


UNITS 


CONDITIONS 


TSET 


Setup ADDR & CS to RE 


50 






nsec 




THLD 


Hold ADDR & CS from RE 


10 






nsec 




TRE 


RE Pulse Width 


400 






nsec 


Cl = 50 pf 


TDRR 


DRQ Reset from RE 




400 


500 


nsec 




TIRR 


INTRO Reset from RE 




500 


3000 


nsec 


See Note 5 


TDACO 


Data Access from RE 






350 


nsec 


Cl = 50 pf 


TDOH 


Data Hold From RE 


50 




150 


nsec 


Cl = 50 pf 



WRITE ENABLE TIMING (See Note 6, Page 21) 



SYMBOL 


CHARACTERISTIC 


MIN. 


TYP. 


MAX. 


UNITS 


CONDITIONS 


TSET 


Setup ADDRS & CS TO WE 


50 






nsec 




THLD 


Hold ADDR & CS from WE 


10 






nsec 




TWE 


WE Pulse Width 


350 






nsec 




TDRR 


DRO Reset from WE 




400 


500 


nsec 




TIRR 


INTRO Reset from WE 




500 


3000 


nsec 


See Note 5 


TDS 


Data Setup to WE 


250 






nsec 




TDH 


Data Hold from WE 




70 




nsec 





Floppy Disk Controller Devices 



1-71 




NOTE 1 CS WAY BE PERMANENTLY TIED LOW IF DESIRED 

2 WHEN WRITING DATA INTO SECTOR TRACK OR DATA 
REGISTER USER CANNOT READ THIS REGISTER UNTIL 
AT LEAST 4 ^SEC IN MFM AFTER THE RISING EDGE OF WE 
WHEN WRITING INTO THE COMMAND REGISTER STATUS 
IS NOT VALID UNTIL SOME 28 ,iSEC IN FM, 14 mSEC IN MFM 
LATER THESE TIMES ARE DOUBLED WHEN CLK 1 MHz 

•TIME DOUBLES WHEN CLOCK 1MHz 

DRQ RISING EDGE INDICATES THAT THE DATA REGISTER IS EMPTY 
DRQ FALLING EDGE INDICATES THAT THE DATA REGISTER IS LOADED 
INTRO RISING EDGE INDICATE THE END OF A COMMAND 
INTRO FALLING EDGE INDICATES THAT THE COMMAND REGISTER 
IS WRITTEN TO 





1 










--H h- 




r- 












^ 


'" p-'« 


— ^ 






















Urn T. _ 

1- 


— i— 


H 








NOMINAL 


DISKETTE 


MODE 


DDEN 


CLK 


T. 


Tb 


Tc 


8" 


MFM 





2 MHz 


1 MS 


1 MS 


2 MS 


8" 


FM 


1 


2 MHz 


2 MS 


2mS 


4 MS 


5" 


MFM 





1 MHz 


2mS 


2ms 


4 MS 


5" 


FM 


1 


1 MHz 


4 ms 


4 MS 


8 mS 



INPUT DATA TIMING 



WRITE ENABLE TIMING 



INPUT DATA TIMING: 



SYMBOL 


CHARACTERISTIC 


MIN. 


TYP. 


MAX. 


UNITS 


CONDITIONS 


"•"pw 




100 


200 




nsec 


See Note 1 


Raw Read Pulse Width 


Tbc 


Raw Read Cycle Time 


1500 


2000 




nsec 


1800 ns @ 70°C 


TcK 


RCLK Cycle Time 


1500 


2000 




nsec 


1800 ns @ 70°C 


Txi 


RCLK hold to Raw Read 


40 






nsec 


See Note 1 


Tx? 


Raw Read hold to RCLK 


40 






nsec 


See Note 1 



WRITE DATA TIMING:(ALL TIMES DOUBLE WHEN CLK = 1 MHz) 



SYMBOL 


CHARACTERISTICS 


MIN. 


TYP. 


MAX. 


UNITS 


CONDITIONS 


Twp 


Write Data Pulse Width 




500 


650 


nsec 


FM 








200 


350 


nsec 


MFM 


Twg 


Write Gate to Write DATA 




2 
1 




/tsec 
/isec 


FM 
MFM 


Tbc 


Write Data Cycle Time 




2,3,or 4 




/isec 


± CLK Error 


Ts 


Early (Late) to Write Data 


125 






nsec 


MFM 


Th 


Early (Late) From 
Write Data 


125 






nsec 


MFM 


Twf 


Write Gate off from WD 




2 
1 




^sec 
iisec 


FM 
MFM 


Twdl 


WD Valid Clk 


100 
50 






nsec 
nsec 


CLK = 1 MHz 
CLK = 2 MHz 


Twd2 


WD Valid after CLK 


100 
30 






nsec 
nsec 


CLK = 1 MHZ 
CLK = 2 MHz 



1-72 



Floppy Disk Controller Devices 



CLK 

(2MHZ) 



.~L 



250 NS- 



"L 



V//////A I V/////A 



Twdl ^ 



CLK 
(2MHZ) 
(DDEN = 0) 



n 



> \ < 



V/////A \ V/////A 



A I V- 



WD MUST HAVE RISING EDGE IN FIRST SHADED AREA AND TRAILING 
EDGE IN SECOND SHADED AREA. 



WRITE DATA/CLOCK RELATIONSHIP 



■n 
o 

X 

o 
to 



WRITE DATA TIMING 



MISCELLANEOUS TIMING: (Times Double When Clock = 1MHz) 



SYMBOL 


CHARACTERISTIC 


MIN. 


TYP. 


MAX. 


UNITS 


CONDITIONS 


TCDi 


Clock Duty (low) 


230 


250 


20000 


nsec 




TCD2 


Clock Duty (high) 


200 


250 


20000 


nsec 




TSTP 


Step Pulse Output 


2 or 4 






/isec 


See Note 5 


TDIR 


Dir Setup to Step 




12 




/zsec 


± CLK ERROR 


TMR 


Master Reset Pulse Width 


50 






/isec 




TIP 


Index Pulse Width 


10 






/xsec 


See Note 5 


TWF 


Write Fault Pulse Width 


10 






/isec 





Floppy Disk Controller Devices 



1-73 



I- — .-H 



|-V,vcH 







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n 






NOTES: 

1. Pulse width on RAW READ (Pin 27) is normally 
100-300 ns. However, pulse may be any width if 
pulse is entirely within window. If pulse occurs in 
both windows, then pulse width must be less than 
300 ns for MFM at CLK = 2 MHz and 600 ns for 
FM at 2 MHz. Times double for 1 MHz. 

2. A PPL Data Separator is recommended for 8" 
MFM. , 

3. tbc should be 2/iS, nominal in MFM and 4/xs 
nominal in FM. Times double when CLK =: 1 MH z. 

4. RCLK may be high or low during RAW READ 
(Polarity is unimportant). 

5. Times double when clock = 1 MHz. 

6. Output timing readings are at Vql = 0.8v and 
VoH = 2.0v. 



MISCELLANEOUS TIMING 

•FROM STEP RATE TABLE 

Table 4. STATUS REGISTER SUMMARY 





ALL TYPE 1 


READ 


READ 


READ 


WRITE 


WRITE 


BIT 


COMMANDS 


ADDRESS 


SECTOR 


TRACK 


SECTOR 


TRACK 


87 


NOT READY 


NOT READY 


NOT READY 


NOT READY 


NOT READY 


NOT READY 


86 


WRITE 
PROTECT 











WRITE 
PROTECT 


WRITE 
PROTECT 


85 


HEAD LOADED 





RECORD TYPE 





WRITE FAULT 


WRITE FAULT 


84 


SEEK ERROR 


RNF 


RNF 





RNF 





S3 


CRC ERROR 


CRC ERROR 


CRC ERROR 





CRC ERROR 





82 


TRACK 


LOST DATA 


LOST DATA 


LOST DATA 


LOST DATA 


LOST DATA 


81 


INDEX PULSE 


DRQ 


DRQ 


DRQ 


DRQ 


DRQ 


80 


BUSY 


BUSY 


BUSY 


BUSY 


BUSY 


BUSY 



STATUS FOR TYPE I COMMANDS 



BIT NAME 


MEANING 


87 NOT READY 


This bit when set indicates the drive is not ready. When reset it indicates that the drive 
is ready. This bit is an inverted copy of the Ready input and logically "ored" with MR. 


86 PROTECTED 


When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT 
input. 


85 HEAD LOADED 


When set, it indicates the head is loaded and engaged. This bit is a logical "and" of HLD 
and HLT signals. 


84 SEEK ERROR 


When set, the desired tracl< was not verified. This bit is reset to when updated. 


S3 CRC ERROR 


CRC encountered in ID field. 


82 TRACK 00 


When set, indicates Read /Write head is positioned to Traci< 0. This bit is an inverted 
copy of the TROO input. 


81 INDEX 


When set, indicates index marl< detected from drive. This bit is an inverted copy of the IP 
input. 


SO BUSY 


When set, command is in progress. When reset no command is in progress. 



1-74 



Floppy Disk Controller Devices 



STATUS FOR TYPE II AND III COMMANDS 


BIT NAME 


MEANING 


87 NOT READY 


This bit when set indicates the dnve is not ready. When reset, it indicates that the 
drive is ready. This bit is an inverted copy of the Ready input and "ORed" with MR. 
The Type II and III Commands will not execute unless the drive is ready. 


36 WRITE PROTECT 


On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a 
Write Protect. This bit is reset when updated. 


85 RECORD TYPE 
WRITE FAULT 


On Read Record: It indicates the record-type code from data field address mark. 1 
= Deleted Data Mark. = Data Mark. On any Write: it indicates a Write Fault. This 
bit is reset when updated. 


84 RECORD NOT 
FOUND (RNF) 


When set, it indicates that the desire track, sector, or side were not found. This bit 
is reset when updated. 


83 CRC ERROR 


If 84 is set, an error is found in one or more ID fields; otherwise it indicates error in 
data field. This bit is reset when updated. 


82 LOST DATA 


When set, it indicates the computer did not respond to DRQ in one byte time. This 
bit is reset to zero when updated. 


81 DATA REQUEST 


This bit is a copy of the DRQ output. When set, it indicates the DR is full on a Read 
Operation or the DR is empty on a Write operation. This bit is reset to zero when 
updated. 


80 BUSY 


When set, command is under execution. When reset, no command is under execution. 



ELECTRICAL CHARACTERISTICS 

Absolute Maximum Ratings 

Vdq with respect to Vss(ground): + 15 to -0.3V 
Voltage to any input with respect to Vgs = +^5 

to -0.3V 
Ice = 60 MA (35 MA nominal) 
Idd = 15 MA (10 MA nominal) 

OPERATING CHARACTERISTICS (DC) 

TA = 0°C to 70°C, Vdd r: + 12V ± .6V, Vgs = OV, Vqc = -+-5V ± .25V 



C|N & Cqut - 15 pF max with all pins grounded 

except one under test. 
Operating temperature = 0°C to 70°C 
Storate temperature = -55°C to +125°C 



SYMBOL 


CHARACTERISTIC 


MIN. 


MAX. 


UNITS 


CONDITIONS 


IlL 


Input Leakage 




10 


^A 


V|N = Vdd** 


Iql 


Output Leakage 




10 


/.A 


Vqut = Vpo 


V,H 


Input High Voltage 


2.6 




V 




V|L 


Input Low Voltage 




0.8 


V 




VoH 


Output High Voltage 


2.8 




V 


lo = -lOO/iA 


Vol 


Output Low Voltage 




0.45 


V 


Iq = 1.6mA 


Pd 


Power Dissipation 




0.6 


w 





M792 and 1794 Iq = 1.0 mA 

'* Leakage conditions are for input pins without internal pull-up resistors. Pins 22, 23, 33, 36, and 37 have pul 
up resistors. 



"n 
o 

-"J 
X 

I 

o 

N) 



Floppy Disk Controller Devices 



1-75 



7-76 Floppy Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 



FD179X Application Notes 



CO 
X 



INTRODUCTION 

Over the past several years, the Floppy Disk Drive has 
become the most popular on-line storage device for 
mini and microcomputer systems. Its fast access 
time, reliability and \o\n cost-per-bit ratio enables the 
Floppy Disk Drive to be the solution in mass storage 
for microprocessor systems. The drive interface to the 
Host system is standardized, allowing the OEM to 
substitute one drive for another with minimum hard- 
ware/software modifications. 

Since Floppy Disk Data is stored and retrieved as a 
self-clocking serial data stream, some means of 
separating the clock from the data and assembling 
this data in parallel form must be accomplished. Data 
is stored on individual Tracks of the media, requir- 
ing control of a stepper motor to move the Read/Write 
head to a predetermined Track. Byte synchronization 
must also be accomplished to ensure that the parallel 
data is properly assembled. After all the design con- 
siderations are met, the final controller can consist 
of 40 or more TTL packages. 

To alleviate the burden of Floppy Disk Controller 
design, Western Digital has developed a Family of 
LSI Floppy Disk controller devices. Through its own 
set of macro commands, the FD179X Controller 
Family will perform all the functions necessary to read 
and write data to the drive. Both the 8" standard and 
5 Va" mini-floppy are supported with single or dou- 
ble density recording techniques. The FD179X is com- 
patible with the IBM 3740 (FM) data format, or the 
System 34 (MFM) standards. Provisions for non- 
standard formats and variable sector lengths have 
been included to provide more storage capability per 
track. Requiring standard +5, + 12 power supplies, 
the FD179X is available in a standard 40-pin dual-in- 
line package. 

The FD179X Family consists of 6 devices. The dif- 
ferences between these devices is summarized in 
Figure 1. The 1792 and 1794 are "single density only" 
devices , with the Double Density Enable pin 
(DDEN) left open by the user. Both True and inverted 
Data Bus devices are available. Since the 179X can 
only drive one TTL Load, a true data bus system may 
use the 1791 with external inverting buffers to arrive 
at a true bus scheme. The 1795 and 1797 are iden- 
tical to the 1791 and 1793, except a side select out- 
put has been added that is controlled through the 
Command Register. 



SYSTEM DESIGN 

The first consideration in Floppy Disk Design is to 
determine which type of drive to use. The choice 
ranges from single-density single sided mini-floppy 
to the 8" double-density double-sided drive. Figure 2 
illustrates the various drive and data capacities 
associated with each type. Although the 8" double- 
density drive offers twice as much storage, a more 
complex data separator and the addition of Write 
Precompensation circuits are mandatory for reliable 
data transfers. Whether to go with 8" double-density 
or not is dependent upon PC board space and the 
additional circuitry needed to accurately recover data 
with extreme bit shifts. The byte transfer time defines 
the nominal time required to transfer one byte of data 
from the drive. If the CPU used cannot service a byte 
in this time, then a DMA scheme will probably be 
required. The 179X also needs a few microseconds 
for overhead, which is subtracted from the transfer 
time. Figure 3 shows the actual sen/ice times that the 
CPU must provide on a byte-by-byte basis. If these 
times are not met, bytes of data will be lost during 
a read or write operation. For each byte transferred, 
the 179X generates a DRQ (Data Request) signal on 
Pin 38. A bit is provided in the Status Register which 
is also set upon receipt of a byte from the Disk. The 
user has the option of reading the status register 
through program control or using the DRQ Line with 
DMA or interrupt schemes. When the data register 
is read, both the Status Register DRQ bit and the DRQ 
Line are automatically reset. The next full byte will 
again set the DRQ and the process continues until 
the sector(s) are read. The Write operation works 
exactly the same way, except a WRITE to the Data 
Register causes a reset of both DRQ's. 

RECORDING FORMATS 

The FD179X accepts data from the disk in a 
Frequency- Modulated (FM) or Modified-Frequency- 
Modulated (MFM) Format. Shown in Figures 4A and 
4B are both these Formats when writing a hex- 
idecimal byte of 'D2.' In the FM mode, the 8 bits of 
data are broken up into "bit cells." Each bit cell begins 
with a clock pulse and the center of the bit cell 
defines the data. If the data bit = 0, no pulse is writ- 
ten; if the data = 1, a pulse is written in the center 
of the cell. For the 8" drive, each clock is written 4 
microseconds apart. 



Floppy Disk Controller Devices 



1-77 



(O 

X 



In the MFM mode, clocks are decoded into the data 
streann. The byte is again broken up into bit cells, with 
the data bit written in the center of the bit cell if data 
= 1. Clocks are only written if both surrounding data 
bits are zero. Figure 4B shows that this occurs only 
once between bit cell 4 and 5. Using this encoding 
schenne, pulses can occur 2, 3 or 4 nnicroseconds 
apart. The bit cell tinne is now 2 microseconds; twice 
as much data can be recorded without increasing the 
Frequency rate due to the encoding scheme. 

The 179X was designed to be compatible with the IBM 
3740 (FM) and System 34 (MFM) Formats. Although 
most users do not have a need for data exchange with 
IBM mainframes, taking advantage of these well 
studied formats will ensure a high degree of system 
performance. The 179X will allow a change in gap 
fields and sector lengths to increase usable storage 
capacity, but variations away from these standards 
is not recommended. Both IBM standards are soft- 
sector format. Because of the wide variation in 
address marks, the 179X can only support soft- 
sectored media. Hard sectored diskettes have con- 
tinued to lose popularity, mainly due to the 
unavailability of a standard and the limitation of sec- 
tor lengths imposed by the physical sector holes in 
the diskette. 

PROCESSOR INTERFACE 

The Interface of the 179X to the CPU consists of an 
8-bit Bi-directional bus, read/write controls and 
optional interrupt lines. By selecting the device via 
the CHIP SELECT Line, each of the five internal 
registers can be accessed. 

Shown below are the registers and their addresses: 



PIN 3 


PIN 6 


PIN 5 


PIN 4 


PIN 2 


CS 


Ai 


Ao 


RE = 


WE=0 











STATUS REG 


COMMAND 








1 


TRACK REG 


REG 





1 





SECTOR REG 


TRACK REG 





1 


1 


DATA REG 


SECTOR REG 


1 


X 


X 


H1-Z 


DATA REG 
H1-Z 



Each time a command is issued to the 179X, the Busy 
Bit is set and the INTRO (Interrupt Request) Line is 
reset. The user has the option of checking the Busy 
Bit or use the INTRO Line to denote command com- 
pletion. The Busy Bit will be reset whenever the 179X 
is idle and awaiting a new command. The INTRO Line, 
once set, can only be reset by a READ of the Status 
Register or issuing a new command. The MR (Master 
Reset) Line does not affect INTRO. 



The Aq, Ai, Lines used for register selections can be 
configured at the CPU in a variety of ways. These lines 
may actually tie to CPU address lines, in which case 
the 179X will be memory-mapped and addressed like 
RAM. They may also be used under Program Control 
by tying to a port device such as the 8255, 6820, etc. 
As a diagnostic tool when checking out the CPU inter- 
face, the Track and Sector registers should respond 
like "RAM" when the 179X is Idle (Busy = INTRO = 
0). 

Because of internal synchronization cycles, certain 
time delays must be introduced when operating under 
Programmed I/O. The worst case delays are: 



OPERATION 


NEXT 
OPERATION 


DELAY REQ'D 


WRITE TO 
COMMAND REG 


READ STATUS 
REGISTER 


MFM = 14fi s* 
FM = 28m s 


WRITE TO 
ANY REGISTER 


READ FROM A 
DIFFERENTREG 


NO DELAY 



*NOTE: Times Double when CLK = 1MHz {5Va" 
drive). 



Other CPU interface lines are CLK, MR and DDEN. 
The CLK line should be 2 MHz (8" drive) or 1 MHz 
(5 Va" drive) with a 50% duty cycle. Accuracy should 
be +1% (crystal source) since all internal timing, 
including stepping rates, are based upon this clock. 

The MR or Master Reset Line should be strobed a 
minimum of 50 microseconds upon each power-on 
condition. This line clears and initializes all internal 
registers and issues a Restore Command (Hex '03') 
on the rising edge. A quicker stepping rate can be 
written to the Command Register after a MR, in 
which case the remaining steps will occur at the 
faster programmed rate. The 179X will issue a max- 
imu m of 2 55 stepping pulses in an attempt to expect 
the TROO line to go activ e low . This line should be 
connected to the drive's TROO sensor. 



The DD EN line causes selection of either single 
densit y (DDEN = 1) or double density operation. 
DDEN should not be switched during a read or 
write operation. 



1-78 



Floppy Disk Controller Devices 



FLOPPY DISK INTERFACE 

The Floppy Disk Interface can be divided into three 
sections: Motor Control, Write Signals and Read 
Signals. All of these lines are capable of driving one 
TTL load and not compatible for direct connection 
to the drive. Most drives require an open-collector TTL 
interface with high current drive capability. This must 
be done on ail outputs from the 179X. Inputs to the 
179X may be buffered or tied to the drive's outputs, 
providing the appropriate resistor termination net- 
works are used. Undershoot should not exceed -0.3 
volts, while integrity of V|h and Vqh levels should be 
kept within spec. 

MOTOR CONTROL 

Motor Control is accomplished by the STEP and DIRC 
Lines. The STEP Line issues stepping pulses with a 
period defined by the rate field in all Type I com- 
mands. The DIRC Line defines the direction of steps 
(DIRC = 1 STEP IN/DIRC = STEP OUT). 

Other Control Lines include the IP or Index Pulse. 
This Line is tied to the drives Index LE.D. sensor and 
•makes an acti ve tra nsition for each revolution of the 
diskette. The TROO Line is another LE.D. sensor 
that informs the 179X that the stepper motor is at its 
furthest position, over Track 00. The READY Line can 
be used for a number of functions, such as sensing 
"door open," Drive motor on, etc. Most drives provide 
a programmable READY Signal selected by option 
jumpers on the drive. The 179X will look at the ready 
signal prior to executing READAA/RITE commands. 
READY is not inspected during any Type I commands. 
All Type I commands will execute regardless of the 
Logic Level on this Line. 

WRITE SIGNALS 

Writing of data is accomplished by the use of the WD, 
WG, WF, TG43, EARLY and LATE Lines. The WG or 
Write Gate Line is used to enable write current at the 
drive's R/W head. It is made active prior to writing data 
on the disk. The WF or WRITE FAULT Line is used 
to inform the 179X of a failure in drive electronics. 
This signal is multiplexed with the VFOE Line and 
must be logically separated if required. Figure 5 
illustrates three methods of demultiplexing. 

The TG43 or "TRACK GREATER than 43" Line is used 
to decrease the Write Current on the inner tracks, 
where bit densities are the highest. If not required on 
the drive, TG43 may be left open. 

WRITE PRECOMPENSATION 

The 179X provides three signals for double density 
Write Precompensation use. These signals are WRITE 
DATA, EARLY and LATE. When using single density 
drives (eighter 8" or 5 1/4"), Write Precompensation 
is not necessary and the WRITE DATA line is 
generally TTL Buffered and sent directly to the drive. 
In this mode, EARLY and LATE are left open. 

For double density use, Write Precompensation is a 
function of the drive. Some manufacturers recom- 
mend Precompensating the 5 1/4" drive, while others 
do not. 



With the 8" drive, Precompensation may be specified 
from TRACK 43 on, or in most cases, all TRACKS. 
If the recommended Precompensation is not 
specified, check with the manufacturer for the pro- 
per configuration required. 

The amount of Precompensation time also varies. A 
typical value will usually be specified from 100-300ns. 
Regardless of the parameters used, Write Precompen- 
sation must be done external to the 179X. When 
DDEN is tied low, EARLY or LATE will be activated 
at least 125ns. before and after the Write Data pulse. 
An Algorithm internal to the 179X decides whether 
to raise EARLY or LATE, depending upon the previous 
bit pattern sent. As an example, suppose the recom- 
mended Precomp value has been specified at 150ns. 
The following action should be taken: 



EARLY LATE 



ACTION TAKEN 



delay WD by 150 ns (nominal) 
1 delay WD by 300ns (2X value) 
1 do not delay WD 

There are two methods of performing Write 
Precompensation: 

1) External Delay elements 

2) Digitally 

Shown in Figure 6 is a Precomp circuit using the 
Western Digital 2143 clock generator as the delay ele- 
ment. The WD pulse from the 179X creates a strobe 
to the 2143, causing subsequent output pulses on the 
01, 02 and 03 signals. The 5K Precomp adjust sets 
the desired Precomp value. Depending upon the con- 
dition of EARLY and LATE, 01 will be used for EARLY, 
02 for nominal (EARLY = LATE = 0), and 03 for LATE. 
The use of "one-shots" or delay line in a Write 
Precompensation scheme offers the user the ability 
to vary the Precomp value. The 04 output resets the 
74LS175 Latch in anticipation of the next WD pulse. 
Figure 7 shows the WD-EARLY/LATE relationship, 
while Figure 8 shows the timing of this write Precomp 
scheme. 

Another method of Precomp is to perform the func- 
tion digitally. Figure 9 illustrates a relationship bet- 
ween the WD pulse and the CLK pin, allowing a digital 
Precomp scheme. Figure 10 shows such a scheme 
with a preset Write Precompensation value of 250ns. 
The synchronous counter is used to generate 2 MHz 
and 4 MHz clock signals. The 2MHz clock is sent to 
the CLK input of the 179X and the 4 MHz is used by 
the 4-bit shift register. When a WD pulse is not pre- 
sent, the 4 MHz clock is shifting "ones" through the 
shift register and maintaining Qp at a zero level. 
When a WD pulse is present, a zero is loaded at either 
A, B, or C depending upon the states of LATE, EN 
PRECOMP and EARLY. The zero is then shifted by 
the 4 MHz clock until it reaches the Qq output. The 
number of shift operations determines whether the 
WRITE DATA pulse is written early, nominal or late. 
If both FM and MFM operations is a system require- 
ment, the output of this circuit should be disabled 
and the WD pulse should be sent directly to the drive. 



CO 

X 



Floppy Disk Controller Devices 



1-79 



CO 

X 



DATA SEPARATION 

The 179X has two inputs (RAW READ & RCLK) and 
one output (VFOE) for use by an external data 
separator. The RAW READ input must present clock 
and data pulses to the 179X, while the RCLK input 
provides a "window" or strobe signal to clock each 
RAW READ pulse into the device. An ideal Data 
Separator would have the leading edge of the RAW 
READ pulse occur in the exact center of the RCLK 
strobe. 

Motor Speed Variation, Bit shifts and read amplifier 
recovery circuits all cause the RAW READ pulses to 
drift away from their nominal positions. As this 
occurs, the RAW READ pulses will shift left or right 
with respect to RCLK. Eventually, a pulse will make 
its transition outside of its RCLK window, causing 
either a CRC error or a Record-Not-Found error at the 
179X. 

A Phase-Lock-Loop circuit is one method of achiev- 
ing synchronization between the RCLK and RAW 
READ signals. As RAW READ pulses are fed to the 
PLL, minor adjustments of the free-running RCLK fre- 
quency can be made. If pulses are occurring too far 
apart, the RCLK frequency is decreased to keep syn- 
chronization. If pulses begin to occur closer together, 
RCLK is increased until this new higher frequency is 
achieved. In normal read operations, RCLK will be 
constantly adjusted in an attempt to match the 
incoming RAW READ frequency. 

Another method of Data Separation is the Counter- 
Separator technique. The RCLK signal is again free- 
running at a nominal rate, until a RAW READ pulse 
occurs. The Separator then denotes the position of 
the pulse with respect to RCLK (by the counter value), 
and counts down to increase or decrease the current 
RCLK window. The next RCLK window will occur at 
a nominal rate and will continue to run at this fre- 
quency until another RAW READ pulse adjusts RCLK, 
but only the present window is adjusted. 

Both PPL and Counter/Separator are acceptable 
methods of Data Separation. The PPL has the highest 
reliability because of its "tracking" capability and is 
recommended for 8" double density designs. 

As a final note, the term "Data Separator" may be 
misleading, since the physical separation of clock and 
data bits are not actually performed. This term is used 
throughout the industry, and can better be described 
as a "Data Recovery Circuit" rather than a Data 
Separator. 

The VFOE signal is an output from the 179X that 
signifies the head has been loaded and valid data 
pulses are appearing on the RAW READ line. It can 
be used to enable the Data Separator and to insure 
clean RCLK transitions to the 179X. Since some drives 
will output random pulses when the head is 
disengaged, VFOE can prevent an erratic RCLK signal 
during this time. If the Data Separator requires syn- 
chronization during a known pattern of one's or zero's, 
then RG (READ GATE) can be used. The RG signal 
will go active when the 179X is currently over a field 



of zero's or ones. RG is not available on the 1795/1797 
devices, since this signal was replaced with the SSO 
(Side Select Output) Line. 

Shown in Figure 11 is a 2V2 10 Counter/Separator. 
The 74LS193 free runs at a frequency determined by 
the CRYCLK input. When a RAW READ pulse occurs, 
the counter is loaded with a starting count of '5.' 
When the RAW READ Line returns to a Logic 1, the 
counter counts down to zero and again free runs. The 
74LS74 insures a 50% duty cycle to the 179X and per- 
forms a divide-by-two of the Qooutput. 

Figure 12 illustrates another Counter/Separator utiliz- 
ing a PROM as the count generator. Depending upon 
the RAW READ phase relationship to RCLK, the 
PROM is addressed and its data output is used as 
the counter value. A 16 MHz clock is required for 8" 
double density, while an 8 MHz clock can be used 
for single density. 

Figure 13 shows a Phase-Lock-Loop data recovery cir- 
cuit. The phase detector (U2, Figure 2) compares the 
phase of the SHAPED DATA pulse to the phase of 
VFO CLK 2. If VFO CLK 2 is lagging the SHAPED 
DATA pulse an output pulse on #9, U2 is generated. 
The filter/amplifier converts this pulse into a DC 
signal which increases the frequency of the VCO. 

If, correspondingly, CLK 2 is leading the SHAPED 
DATA pulse, an output pulse on #5, U2 is generated. 
This pulse is converted into a DC signal which 
decreases the frequency of the VCO. These two 
actions cause the VCO to track the frequency of the 
incoming READ DATA pulses. This correction process 
to keep the two signals in phase is constantly occur- 
ring because of spindle speed variation and circuit 
parameter variations. 

The operating specifications for this circuit are as 
follows: 



Free Running Frequency 


2 MHz 


Capture Range 


+ 15% 


Lock Up Time 


50 microsec. "1111" or 




"0000" Pattern 




100 Microsec "1010" 




Pattern 



The RAW READ pulses are generated from the fall- 
ing edge of the SHAPED DATA pulses. The pulses 
are also reshaped to meet the 179X requirements. 
VFO CLK 2 OR 4 is divided by 2 once again to obtain 
VFO CLK OUT whose frequency is that required by 
the 179X RCLK input. RCLK must be controlled by 
VFOE so VFOE is sampled on each rising edge of 
VFO CLK OUT. When VFOE goes active EN RCLK 
goes active in synchronization with VFO CLK OUT 
preventing any glitches on the RCLK output. When 
VFOE goes inactive EN RCLK goes inactive in syn- 
chronization with VFO CLK OUT, again preventing any 
glitches on the RCLK output. 

Figure 14 illustrates a PPL data recovery circuit using 
the Western Digital 1691 Floppy Support device. Both 
data recovery and Write Precomp Logic is contained 
within the 1691, allowing low chip count and PLL 



1-80 



Floppy Disk Controller Devices 



reliability. The 74S124 supplies the free-running VCO 
output. The PUMP UP and PUMP DOWN signals from 
the 1691 are used to control the 74S124's frequency. 

COMMAND USAGE 

Whenever a command is successfully or unsuc- 
cessfully completed, the busy bit of the Status 
Register is reset and the INTRQ line is forced high. 
Command termination may be detected either way. 
The INTRQ can be tied to the host processor's inter- 
rupt with an appropriate service routine to terminate 
commands. The busy bit may be monitored with a 
user program and will achieve the same results 
through software. Performing both an INTRQ and a 
busy bit check is not recommended because a read 
of the Status Register to determine the condition of 
the busy bit will reset the INTRQ line. This can cause 
an INTRQ from not occurring. 

RESTORE COMMAND 

On some disk drives, it is possible to position the R/W 
head outward past Track 00 and prevent the TROO line 
from going low unless a STEP IN is first performed. 
If this condition exists in the drive used, the RESTORE 
command will never detect a TROO. Issuing several 
STEP IN pulses before a RESTORE command will 
remedy this situation. The RESTORE and all other 
Type I commands will execute even though the 
READY bit Indicates the drive is not ready (NOT 
READY = 1). 

READ TRACK COMMAND 

The READ TRACK command can be used to manually 
inspect data on a hard copy printout. Gaps, address 
marks and all data are brought in to the Data Register 
during this command. The READ TRACK command 
may be used to inspect diskettes for valid formatting 
and data fields as well as address marks. Since the 
179X does not synchronize clock and data until the 
Index Address Mark is detected, data previous to this 
ID mark will not be valid. READ GATE (RG) is not 
actuated during this command. 

READ ADDRESS COMMAND 

In systems that use either multiple drives or sides, 
the read address command can be used to tell the 
host processor which drive or side is selected. The 
current position of the RAA/ head is also denoted in 
the six bytes of data that are sent to the computer. 



Type I status in the Status Register. The lower four 
bits of the command determine the conditional inter- 
rupt as follows: 



TRACK SIDE 


SECTOR 


CRS 
LENGTH 


CRC 

1 


CRC 
2 



The READ ADDRESS command as well as all other 
Type II and Type III commands will not execute if the 
READY line is inactive (READY = 0). Instead, an inter- 
rupt will be generated and the NOT READY status bit 
will be set to a 1. 

FORCED INTERRUPT COMMAND 

The Forced Interrupt command is generally used to 
terminate a multiple sector command or to insure 



1o = NOT-READY TO READY TRANSITION 
1i = READY TO NOT-READY TRANSITION 
^2 = EVERY INDEX PULSE 
I3 = IMMEDIATE INTERRUPT 



Regardless of the conditional interrupt set, any com- 
mand that is currently being executed when the 
Forced Interrupt command is loaded will immediately 
be terminated and the Busy Bit will be reset indicating 
an idle condition. 

Then, when the condition for interrupt is met, the 
INTRQ line will go high signifying that the condition 
specified has occured. 

The conditional interrupt is enabled when the cor- 
responding bit positions of the command (13 - 10) are 
set to a 1. If I3 - Iq are all set to zero, no interrupt will 
occur, but any command presently under execution 
will be immediately terminated upon receipt of the 
Force Interrupt command (HEX DO). 

As usual, to clear the interrupt a read of the Status 
Register or a write to the command register is 
required. The exception is when using the immediate 
interrupt condition (I3 = 1). If this command is 
loaded into the command register, an interrupt will 
be immediately generated and the current command 
terminated. Reading the status or writing to the com- 
mand register will not automatically clear the inter- 
rupt; another forced interrupt command with I3 - Iq = 
must be loaded into the command register in order 
to reset the INTRQ from this condition. 

More than one condition may be set at a time. If for 
example, the READY TO NOT-READY condition 
I1 = 1 and the Every Index Pulse I2 = 1 are both set, 
the resultant command would be HEX "DA." The 
"OR" function is performed so that either a READY 
TO NOT-READY or the next Index Pulse will cause 
an interrupt condition. 

DATA RECOVERY 

Occasionally, the RA/V head of the disk drive may get 
"off track", and dust and dirt may get trapped on the 
media. Both of these conditions will cause a RECORD 
NOT FOUND and/or a CRC error to occur. This "soft 
error" can usually be recovered by the following 
procedure: 

1. Issue the command again 

2. Unload and load the head and repeat step 

3. Issue a restore, seek the track, and repeat 
step 1 

If RNF or CRC errors are still occurring after trying 
these methods, a "hard error" may exist. This is 
usually caused by improper disk handling, exposure 
to high magnetic fields, etc. and generally results in 
destroying portions or tracks of the diskette. 



CO 

X 



Floppy Disk Controller Devices 



1-81 



FIGURE 1. DEVICE CHARACTERISTICS 



CO 
X 



DEVICE 


SNGL DENSITY 


DBLE DENSITY 


INVERTED BUS 


TRUE BUS 


DOUBLE-SIDED 


1791 


X 


X 


X 






1792 


X 




X 






1793 


X 


X 




X 




1794 


X 






X 




1795 


X 


X 


X 




X 


1797 


X 


X 




X 


X 



FIGURE 2. STORAGE CAPACITIES 









UNFORMATTED 


BYTE 


FORMATTED 


SIZE 


DENSITY 


SIDES 


CAPACITY (NOMINAL) 


TRANSFER 
TIME 


CAPACITY 


PER TRACK 


PER DISK 


PER TRACK 


PER DISK 


5 1/4" 


SINGLE 


1 


3125 


' 109,375* 


64ps 


2304** 


80,640 


5 1/4" 


DOUBLE 


1 


6250 


218,750 


32ius 


4608*** 


161,280 


5 1/4" 


SINGLE 


2 


3125 


218,750 


64jL/s 


2304 


161,280 


5 1/4" 


DOUBLE 


2 


6250 


437,500 


32^3 


4608 


322,560 


8" 


SINGLE 


1 


5208 


401.016 


32^5 


3328 


256,256 


8" 


DOUBLE 


1 


10,416 


802,032 


16ms 


6656 


512,512 


8" 


SINGLE 


2 


5208 


802,032 


32^5 


3328 


512,512 


8" 


DOUBLE 


2 


10,416 


1,604,064 


16ms 


6656 


1,025,024 



'Based on 35 Tracks/Side. 

'* Based on 18 Sectors/Track (128 byte/sec). 

'**Based on 18 Sectors/Track (256 bytes/sec). 



1-82 



Floppy Disk Controller Devices 



FIGURE 3. NOMINAL VS. WORST CASE SERVICE TIME 



SIZE 


DENSITY 


NOMINAL TRANSFER 
TIME 


WORST-CASE 179X SERVICE TIME 


READ 


WRITE 


5 1/4" 
5 1/4" 
8" 
8" 


SINGLE 
DOUBLE 
SINGLE 
DOUBLE 


64^3 
32^3 
32^3 

16^3 


55.0mS 
27.5m3 
27.5^3 
13.5^3 


47.0^3 
23.5^(3 
23.5^(3 
11.5m3 



-n 
o 

CO 

X 



FIGURE 4A. FM RECORDING 



BITO 


BIT1 


BIT 2 


BIT 3 


BIT 4 


BITS 


BIT 6 


BIT 7 



f^I^RFll ^ F IFII ^ R R F1R 



RULE: 

1) WRITE DATA BITS AT CENTER 
OF BIT CELL IF A ■I" 

2) WRITE CLOCK BITS AT LEADING 
EDGE OF THE BIT CELL 



FIGURE 4B. MFM RECORDING 





2mS 

1 1 
















BITO 


BIT1 


BIT 2 


BIT 3 


BIT 4 




BITS 


BIT 6 


BIT 7 




1 1 


1 










1 





HEX 
■02' 


RULE; 


R 




J^ 




R 








1 


) WRITE DATA BITS AT CENTER 
OF BIT CELL IF A •V 
















) WRITE CLCX;K BITS AT LEADING 
EDGE OF BIT CELL IF: 
















k) NO DATA BIT HAS BEEN WRITTEN LAST 

— AND— 
i) NO DATA BIT WILL BE WRITTEN NEXT 















Floppy Disk Controller Devices 



1-83 



FIGURE 5. WF/VFOE DEMULTIPLEXING CIRCUITRY 



•n 

D 

(O 

X 








+ 5 

^ ""< 74LS01 
1 /' / ,.,.,,„«..„„.,„ 


179X 


33 
30 


1 ff 




.' \_^ 


* 33 USED AS A WF SIGNAL ONLY 




• PI 



EARLY 
LATE 



J \3-ll 4DCL 



7 C-LATE 



15 C-NOMINAL 



7=0 



H2 > *— WAr- 



PRECOMP. 
ADJUST 



IN jn 

^4 



WD TO 
DRIVE 



FIGURE 6. 179X WRITE PRE-COMP 



1-84 



Floppy Disk Controller Devices 



_n 



2, 3. 4m». ± CLK TOL 



r- 



EARLY 
ORUTE 



DOUBLE TIMES FOR 5" (MINI-FLOPPY) 




125 NS MIN. VALID 
FOR DURATION OF 
WD PULSE 



WRITE PRE-COMP TIMING FOR MFM 



■^ 2, 4/iS ± CLK TOL 

U*— 500 NS :r so 



n 



EARLY 
OR LATE 



DOUBLE TIMES FOR 5" (MINI-FLOPPY) 



U>UJ 



VALID BEFORE LEADING EDGE OF WD 



WRITE PRE-COMP TIMING FOR FM 



FIGURE 7. WRITE PRECOMP TIMING 



BIT CELL C I BIT CELL 1 I BIT CELL 2 I BIT CELL 3 I BIT CELL 4 I BIT CELL 5 I BIT CELL 6 I BIT CELL 7 I BIT CELL S I BIT CELL 9 

I |-*- 200 NS 

]J3 lllIxSu 13 n n p 






n 



K- n n ji 




J~L 



n. 



n fi 



ji n 



^ 



K. 



U IT 



J~L 



n. 



JI 



JL 



n ri 



JL 



ji 



D — u 



Id — br 



R. 



JL 



ji_ 



¥ 



FIGURE 8. PRE-COMP TIMING FOR CIRCUIT IN FIGURE 6 



Floppy Disk Controller Devices 



1-85 



X 



CLK 
@1MHz 



WD 
(DOEN - 0) 





ly 1 \ 
/ \ 

slOOns alOOns 



CLK 
@2MHz 



WD 
(DDEN - 0) 




7^ 




350ns a30ns 



FIGURE 9. WD/CLK RELATIONSHIP FOR WRITE PRECOMP USE 




(FROM t791) 
TG43 {EN PBECOMP) 




WRITE 
DATE 
aO DRIVE) 



FIGURE 10. DIGITAL WRITE PRECOMP CIRCUIT 

(PROVIDED COURTESY OF MPI, OKLAHOMA CITY, OK 73112) 



1-86 



Floppy Disk Controller Devices 



R, C = 150 NS ± 50 



ni 



e-' 



RAW READ 
FROM DRIVE 




H5 >- 




B Qo 
C 



CD c -11 



A 
CRYCLK 



TYPE 


DDEN 


CRYCLK 1 


1 


8"FM 


1 


8 MHz 


5" MFM 





8 MHz 


5"FM 


1 


4 MHz 



27 
-C 



RG 
DDEN 



CO 

X 



FIGURE 11. COUNTER /SEPARATOR 



Floppy Disk Controller Devices 



1-87 



xezi-Qd 



J3 
O 
< 

D 
m 
o 

O 
O 

c 
ja 

H 

m 

CO 

> DO 

z m 

a -X 

o _, 

> o 

CO > 

2 m 



> 

Z 

o 

> 
> 

o 



745288 PROGRAMMING TABLE 



ADDRESS 


DATA 


ACTION TAKEN 


00 


01 


NONE 


01 


01 


RETARD BY 1 COUNT 


02 


02 




03 


03 




04 


03 


RETARD BY 2 COUNTS 


05 


04 




06 


05 




07 


06 




08 


OB 


ADVANCE BY 2 COUNTS 


09 


00 




OA 


OC 




OB 


OE 




OC 


OF 




OO 


OF 


ADVANCE BY 1 COUNT 


OE 


00 




OF 


01 




10 


01 


FREE RUN 


11 


02 




12 


03 




13 


04 




14 


05 




15 


06 




16 


07 




17 


08 




18 


09 




19 


OA 




1A 


OB 




IB 


OC 




1C 


OD 




ID 


OE 




IE 


OF 




IF 


00 





READ DATA 
FROM >- 
DRIVE 



^^ 



1, 

D O 
C S 



Hi 



<^ 






D, O, 
D. Q. 
D, Q, 
D, Q, 
O, 



-q- 



VR5BWF 



RAW READ 



CS 
A. 

A, D, 
A, D, 
A, D, 
A, D, 



T. 



5 



■T 



■u 

O 
< 

O 



2 > 



o 

7s 



■Xv » 



R18 
270n 
1/2 W 



yvv 1 

J- C71 



i 



C71 
47(iF 



C70 
ISO/iF 



<D- 



t 7400 Jp I, 



L 



o- 



26S02 

clr" 

i U1 



SHAPED DATA 



R29 
IKn 



I. 

26S02 
clS S J 
I, Ut 

14 [is 

-HH 

C89 
82mF 



® 74S112 

J 

CIX 



C3H 



S 74S112 



.(^ 



VFOCLK 
STEERING 1 



C73 
047mF 

^l — 



C74 
1300jiF 



VFOCLX 
STEERING 2 



C82 1 

laoo^Fzi 

2% -[_ 



C83 
.047/iF 



J. C84 

VF 



R23 

1.2Kn 

-'VVV — 




R24 

IKn 



6 2MHZ 
VCO 



VFOCLK ■i-2 0R4 



"" 74S112 
J 

CLK Q 



in ] 7400^ 3-^ 




VFO CLK OUT 



L^-^ 



EN PRE-COMP 



-© 



■<D 



^ 



X6zi.ad 



xezi-Qd 




NOTE 3 



+ 12V 



1) ALL RESISTORS '/«W ± 5% 

2. SPECIFICATIONS = 
CAPTURE RANGE: ±20% 
LOCK-UP TIME: 25^560 

(ALL QNE'S PATTERN, MFM) 

3) FOR 5 1/4" 8 



04 03 02 01 
STB IN 

WD21 43-03 
;^PW 



<:> 



<:^ 



<o- 



DDEN 

RCLK 

WG 

WD 

EARLY 

LATE 

TG43 

VFOE/WF 




TROO 



PRECOMPADJ 



.68/if .33/Ltf 
68n 33n 



■<J 



<Z1 



<3 



FROM 
DRIVE 



■<3 



WESTERN DIGITAL 

CORPORATION 



WD279X-02 Floppy Disk Formatter/Controller Family 



FEATURES 

• ON-CHIP PLL DATA SEPARATOR 

• ON-CHIP WRITE PRECOMPENSATION LOGIC 

• SINGLE +5V SUPPLY 

• ACCOMMODATES SINGLE AND DOUBLE 
DENSITY FORMATS 

IBM 3740 (FM) 
IBM 34 (MFM) 

• AUTOMATIC SEEK WITH VERIFY 

• MULTILE SECTOR READ/WRITE 

• TTL COMPATIBLE 

• PROGRAMMABLE CONTROL 

SELECTABLE TRACK-TO-TRACK ACCESS 
HEAD LOAD TIMING 

• SOFTWARE COMPATIBLE WITH THE FD179X 
SERIES 

• SOFT SECTOR FORMAT COMPATIBILITY 



DESCRIPTION 

The WD279X are N-Channel Silicon Gate MOS LSI 
devices which perform the functions of a Floppy Disk 
Formatter/Controller in a single chip implementation. 
The WD279X, which can be considered the end result 
of both the FD1771 and FD179X designs, is IBM 3740 
compatible in single density mode (FM) and System 
34 compatible in Double Density Mode (MFM). The 
WD279X contains all the features of its predecessor 
the FD179X plus a high performance Phase-Lock- 
Loop Data Separator as well as Write Precompensa- 
tion Logic. In Double Density mode, Write Precompen- 
sation is automatically engaged to a value 
programmed via an external potentiometer. In order 
to maintain compatibility, the FD1771, FD179X and 
WD279X designs were made as close as possible with 
the computer interface, instruction set, and I/O 
registers being identical. 

Also, head load control is identical. In each case, the 
actual pin assignments vary by only a few pins from 
any one to another. 

The processor interface consists of an 8-bit bi- 
directional bus for data, status, and control word 
transfers. The WD279X is set up to operate on a 
multiplexed bus with other bus-oriented devices. 



O 
lo 

o 



1 ^ 40=3 


HLT 


2 


39 


=D 


INTRO 


3 


38 


Z] 


DRQ 


4 


37 


Z3 


OOEN 


5 


36 


ZD 


WPRT 


6 


35 


=1 


IP 


7 


34 


=D 


TROO 


8 


33 


ID 


WPW 


9 


32 


=1 


READY 


10 


31 


=D 


WD 


11 


30 


ZD 


WG 


12 


29 


=1 


TG43 


13 
14 


28 
27 


Z3 


HLD 


_l 


RAWRD 


15 


26 


ZD 


VCO 


16 


25 


ZD 


SSO/ENMF 


17 


24 


zn 


CLK 


18 


23 


=1 


PUMP 


19 


22 


ZDTIST 


20 


21 


ZDvcc 



ENP [ 

WE [ 

CS [ 

REl 

A0[ 

A1I 

DAI.O[ 

DAL1 [ 

DAL2[ 

DAL3[ 

OAU[ 

DAL5[ 

oalbI 

DAL7I 
STEP[ 
DIRC[ 
5/8 [ 
RPWl 

mr[ 

GND[ 



PIN DESIGNATION 

The WD279X is TTL compatible on all inputs and out- 
puts. The outputs will drive one TTL load or three LS 
loads. The WD2793 is identical to the WD2791 except 
the DAL lines are TRUE for systems that utilize true 
data busses. 

The WD2795/7 has a side select output for controll- 
ing double-sided drives. 



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AOC 5 

A1C 6 



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R 
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R N 
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39 38 37 36 35 34 33 32 31 30 29 



^7 8 9 10 11 12 13 14 15 16 17 

uuuuuuuuuuu 

NDDDDDDDDSN 

CAAAAAAAATC 

LLLLLLLLE 

01 234567P 



Hvco 


_] SSO/ENMF 


Z]CLK 


13 PUMP 


ZlTEST 


HVcc 


IDgnd 


Dmr 


ZlRPW 


D5/8 


ZJdirc 



Floppy Disk Controller Devices 



1-91 



nj-ijji»-ji.mj.^-.~jM™-»<->^^»-» 



PIN DESCRIPTION 



a 
ro 

x 

o 
ro 



PIN NUMBER 


SIGNAL NAME 


MNEMONIC 


FUNCTION 


1 


ENABLE PRECOMP 


ENP 


A Logic high on this input enables write 
precompensation to be performed on double 


19 




MR 


density Write Data output only. 

A logic low (50 microseconds min.) on this 


MASTER RESET 








input resets the device and loads HEX 03 into 








the command register. The Not Ready 








(Status Bit 7) is reset during MR ACTIVE. 








When MR is brought to a logic high a 








RESTORE Command is executed, regardless 








of the state of the Ready signal from the 








drive. Also, HEX 01 is loaded into sector 








register. 


20 


POWER SUPPLIES 


Vss 


Ground 


21 




Vcc 


+ 5V2^ 


COMPUTER INTE 
2 


RFACE: 


WE 


A logic low on this input gates data on the 


WRITE ENABLE 








DAL into the selected register when CS is 








low. 


3 


CHIP SELECT 


CS 


A logic low on this input selects the chip and 
enables computer communication with the 


4 




RE 


device. 

A logic low on this input controls the place- 


READ ENABLE 








ment of data from a selected register on the 








DAL when CS is low. 


, 5,6 


REGISTER SELECT 








LINES 


A0,A1 


These inputs select the register to 
receive/transfer data on the DAL lines under 
RE and WE control: 

CS A1 AO RE WE 

status Reg Command Reg 
1 Track Reg Track Reg 
1 Sector Reg Sector Reg 
1 1 Data Reg Data Reg 


7-14 


DATA ACCESS LINES 


DAL0-DAL7 


Eight bit bi-directional bus used for transfer 
of commands, status, and data. These lines 
are inverted (active low) on WD2791 and 
WD2795. 


24 


CLOCK 


CLK 


This input requires a free-running 50% duty 
cycle square wave clock for internal timing 
reference, 2 MHz ± 1 % for 8" drives, 1 MHz 
± 1 % for mini-floppies. 


38 


DATA REQUEST 


DRQ 


This output indicates that the Data Register 
contains assembled data in Read operations, 
or the DR is empty in Write operations. This 
signal is reset when serviced by the com- 
puter through reading or loading the DR. 



wMMumm ' iiammmM 



1-92 



Floppy Disk Controller Devices 



PIN DESCRIPTION (Continued) 



PIN NUMBER 


SIGNAL NAME 


MNEMONIC 


FUNCTION 


39 


INTERRUPT REQUEST 


INTRO 


This output is set at the completion of any 
command and is reset when the Status 
register is read or the command register is 
written to. 


FLOPPY DISK IN 


TERFACE: 






15 


STEP 


STEP 


The step output contains a pulse for each 
step. 


16 


DIRECTION 


DIRC 


Direction Output is active high when stepp- 
ing in, active low when stepping out. 


17 


5 1/4," 8" SELECT 


5/8 


This input selects the internal VCO fre- 
quency for use with 5 1/4" drives or 8" drives. 


18 


READ PULSE WIDTH 


RPW 


An external potentiometer tied to this input 
controls the phase comparator within the 
data separator. 


22 


TEST 


TEST 


A logic low on this input allows adjustment 
of external resistors by enabling internal 
signals to appear on selected pins. 


23 


PUMP 


PUMP 


High-Impedance output signal which is 
forced high or low to increase or decrease 


25 






the VCO frequency. 

A logic low on this input enables an inter- 


ENABLE MINI-FLOPPY 


ENMF 




(2791, 2793) 




nal -^ 2 of the Master Clock. This allows both 
5 1/4" and 8" drive operation with a single 
2 MHz clock. For a 1 MHz clock on Pin 24, 
this line must be left open or tied to a 
Logic 1. 


25 


SIDE SELECT OUTPUT 


SSO 


The logic level of the Side Select Output is 




(2795, 2797) 




directly controlled by the 'S' flag in Type II 
or III commands. When U =i 1, SSO is set 
to a logic 1. When U = 0, SSO is set to a 
logic 0. The SSO is compared with the side 
information in the Sector ID Field. If they do 
not compare Status Bit 4 (RNF) is set. The 
Side Select Output is only updated at the 
beginning of a Type II or III command. It is 
forced to a logic upon a MASTER RESET 
condition. 


26 


VOLTAGE- 


VCO 


An external capacitor tied to this pin adjusts 




CONTROLLED 




the VCO center frequency. 


27 


OSCILLATOR 




The data input signal directly from the drive. 


RAW READ 


RAW READ 








This input shall be a negative pulse for each 








recorded flux transition. 


28 


HEAD LOAD 


HLD 


The HLD output controls the loading of the 
Read-Write head against the media. 


29 


TRACK GREATER 


TG43 


This output informs the drive that the 




THAN 43 




Read/Write head is positioned between track 
44 and the inside track. This output is valid 
only during Read and Write Commands. 



Floppy Disk Controller Devices 



1-93 



PIN DESCRIPTION (Continued) 



O 
CO 

X 
o 



PIN NUMBER 


SIGNAL NAME 


MNEMONIC 


FUNCTION 


30 


WRITE GATE 


WG 


This output Is made valid before writing is 
to be performed on the diskette. 


31 


WRITE DATA 


WD 


MFM or FN/1 output pulse per flux transition. 
WD contains the unique Address marks as 
well as data and clock in both FM and MFM 
formats. 


32 


READY 


READY 


This input indicates disk readiness and is 
sampled for a logic high before Read or 
Write commands are performed. If Ready is 
low the Read or Write operation is not per- 
formed and an interrupt is generated. Type 
1 operations are performed regardless of the 
state of Ready. The Ready input appears in 
inverted format as Status Register bit 7. 


33 


WRITE PRECOMP 


WPW 


An external potentiometer tied to this input 




WIDTH 




controls the amount of delay in Write 


34 




TROO 


precompensation mode. 

This input informs the WD279X that the 


TRACK 00 


35 




IP 


Read/Write head is positioned over Track 00. 
This input informs the WD279X when the 


INDEX PULSE 


36 






index hole is encountered on the diskette. 
This input is sampled whenever a Write Com- 


WRITE PROTECT 


WPRT 








mand is received. A logic low terminates the 


37 






command and sets the Write Protect Status 
bit. 

This input pin selects either single or dou- 


DOUBLE DENSITY 


DDEN 








ble density operation. When DDEN = 0, 








double density is selected. When DDEN 








= 1, single density is selected. 


40 


HEAD LOAD TIMING 


HLT 


When a logic high is found on the HLT input 
the head is assumed to be engaged. It is 
typically derived from a 1 shot triggered by 
HLD. 



1-94 



Floppy Disk Controller Devices 




Figure 1. 



APPLICATIONS 

8" FLOPPY AND 5 1/4" MINI-FLOPPY CONTROLLER 
SINGLE OR DOUBLE DENSITY CONTROLLER/- 
FORMATTER 

The WD279X Family are MOS/LSI devices which per- 
form the functions of a Floppy Disl< Controller/For- 
matter. Software compatible with its predecessor, the 
FD179X, the device also contains a high performance 
Phase-Lock-Loop Data Separator as well as Write 
Precompensation Logic. 

When operating in Double Density mode, Write 
Precompensation may be enabled, its value predeter- 
mined by an external potentiometer. An on-chip VCO 
and phase comparator allows adjustable frequency 
range for 5 1/4" or 8" Floppy Disk interfacing. 

The WD279X is fabricated in NMOS silicon gate 
technology and available in a 40-pin dual-in-line 
package, as well as 44-pin quad packs. 



FEATURES 


2791 


2793 


2795 


2797 


Single Density (FM) 


X 


X 


X 


X 


Double Density (MFM) 


X 


X 


X 


X 


True Data Bus 




X 




X 


Inverted Data Bus 


X 




X 




Side Select Out 






X 


X 


Internal CLK Divide 


X 


X 







ORGANIZATION 

Refer to the Floppy Disk Formatter block diagram in 



Figure 2. The primary sections include the parallel pro- 
cessor interface and the Floppy Disk Interface. 

Data Shift Register - This 8-bit regist er assembles 
serial data from the Read Data input (RAW READ) 
during Read operations and transfers serial data to 
the Write Data output during Write operations. 

Data Register-This 8-bit register is used as a holding 
register during Disk Read and Write operations. In 
Disk Read operations the assembled data byte is 
transferred in parallel to the Data Register from the 
Data Shift Register. In Disk Write operations infomna- 
tion is transferred in parallel from the Data Register 
to the Data Shift Register. 

When executing the Seek command the Data Register 
holds the address of the desired Track position. This 
register is loaded from the DAL and gated onto the 
DAL under processor control. 

Track Register - This 8-bit register holds the track 
number of the current Read/Write head position. It is 
incremented by one every time the head is stepped 
in (towards track 76) and decremented by one when 
the head is stepped out (towards track 00). The con- 
tents of the register are compared with the recorded 
track number in the ID field during disk Read, Write, 
and Verify operations. The Track Register can be 
loaded from or transferred to the DAL. This Register 
should not be loaded when the device is busy. 
Sector Register (SR) - This 8-bit register holds the 
address of the sector position. The contents of the 
register are compared with the recorded sector 
number in the ID field during disk Read or Write opera- 
tions. The Sector Register contents can be loaded 
from or transferred to the DAL. This register should 
not be loaded when the device is busy. 

Command Register (CR)-This 8-bit register holds the 
command presently being executed. This register 
should not be loaded when the device is busy unless 
the new command is a force interrupt. The command 
register can be loaded from the DAL, but not read 
onto the DAL 

Status Register (STR)-This 8-bit register holds device 
Status information. The meaning of the Status bits 
is a function of the type of command previously 
executed. This register can be read onto the DAL, but 
not loaded from the DAL. 

CRC lj>glc^-This logic is used to check or to generate 
the 16-bit Cyclic Redundancy Check (CRC). The 
polynomial is: G(x) = x""^ + x''^ -f x^ -f- 1. 

The CRC includes all information starting with the 
address mark and up to the CRC characters. The CRC 
register is preset to ones prior to data being shifted 
through the circuit. 

Arithmetic/Logic Unit (ALU)- The ALU is a serial com- 
parator, incrementer, and decrementer and is used 
for register modification and comparisons with the 
disk recorded ID field. 

Timing and Control -All computer and Floppy Disk 
interface controls are generated through this logic. 



O 
CO 

X 

■ 

o 

N3 



Floppy Disk Controller Devices 



1-95 



The internal device timing is generated from an exter- 
nal crystal clock. 



O 
ro 

CO 

X 

I 

o 
to 



AM Detector - The address mark detector detects ID, 
data and Index address marks during read and write 
operations. 

Write Precompensation - enables write precompensa- 
tion to be performed on the Write Data ouput. 



-a 



v 



PHASE 
LOCK 
LOOP 



-VCO 
PUMP 



DATA SEPARATOR 





DBQ 
























WG 






INTRO 
























IG.3 




• 














SB 






































cs 


' 






















iP 






BE 




CONT 


mx 


CON 


TflOL 


1230 X 16) 




CONTROL 




'coE'o' 


" 


TflOO 






m 




RE*D» 


AO 












* 


STEP 




«1 






















DiRC 


* 








m^- 


_^ 




















HLD 




MLT * 


























•^ 







Figure 2. WD279X BLOCK DIAGRAM 



Data Separator - a high performance Phase-Lock-Loop 
Data Separator with on-chip VCO and phase com- 
parator allows adjustable frequency range for 5V4" 
or 8" Floppy Disk interfacing. 
PROCESSOR INTERFACE 

The Interface to the processor is accomplished 
through the eight Data Access Lines (DAL) and 
associated control signals. The DAL are used to 
transfer Data, Status, and Control words out of, or 
into the WD279X. The DAL are three state buffers that 
are enabled as output drivers when Chip Select 
(CS) and Read Enable (RE) are active (low logic 
state) or act as input receivers when CS and Write 
Enable (WE) are active. 

When transfer of data with the Floppy Disk Controller 
is required by the host processor, the device address 
is decoded and CS is made low. The address bits A1 



and AO. combined with the signals RE during a 
Read operation or WE during a Write operation are 
Interpreted as selecting the following registers: 



A1 AO 



READ (RE) 



WRITE (WE) 



Status Regiser 

1 Track Register 

1 Sector Register 
1 1 Data Register 



Command Register 
Track Register 
Sector Register 
Data Register 



During Direct Memory Access (DMA) types of data 
transfers between the Data Register of the WD279X 
and the processor, the Data Request (DRQ) output 
is used in Data Transfer control. This signal also 
appears as status bit 1 during Read and Write 
operations. 



1-96 



Floppy Disk Controller Devices 



On Disk Read operations the Data Request is 
activated (set higii) when an assembled serial input 
byte is transferred in parallel to the Data Register. This 
bit is cleared when the Data Register is read by the 
processor. If the Data Register is read after one or 
more characters are lost, by having new data transfer- 
red into the register prior to processor readout, the 
Lost Data bit is set in the Status Register. The Read 
operation continues until the end of sector is reached. 

On Disk Write operations the Data Request is 
activated when the Data Register transfers its con- 
tents to the Data Shift Register, and requires a new 
data byte. It is reset when the Data Register is loaded 
with new data by the processor. If new data is not 
loaded at the time the next serial byte is required by 
the Floppy Disk, a byte of zeroes is written on the 
diskette and the Lost Data bit is set in the Status 
Register. 

At the completion of every command an INTRO is 
generated. INTRO Is reset by either reading the status 
register or by loading the command register with a 
new command. In addition, INTRO is generated if a 
Force Interrupt command condition is met. 

The WD279X h as two modes of operat ion ac cording 
to the state of DDEN (Pin 37). When D DEN = 1, 
Single Density (FM) is selected. When DDEN = 0, 
Double Density (MFM) is selected. In either case, the 
GLK input (Pin 24) is set at 2 MHz for 8" drives or 1 
MHz for 5 1/4" drives. 



On the WD2791/WD2793, the ENMF input (Pin 25) 
can be used for controlling both 5 1/4" an d 8" drives 
with a single 2 MHz clock. When ENMF = 0, an 
internal -^2 of the GLK is performed. When ENMF 
= 1, no divide takes place. This allows the use of 
a 2 MHz clock for both 5 1/4" and 8" configurations. 

The internal VCO frequency must also be set to the 
proper value. The 5/8 input (Pin 17) is used to select 
data separator operation by internally dividing the 
Read Clock. When_5/8 = 0, 5 1/4" data separation 
is selected; when 5/8 = 1, 8" drive data separation 
is selected. 



CLOCK (24) 




5/8(17) 


DRIVE 


ENMF (25) 


2 MHz 
2 MHz 
1 MHz 


1 


1 


1 




8" 

5Va 
5V4 



FUNCTIONAL DESCRIPTION 

The WD279X-02 is software compatible with the 
FD179X-02 series of Floppy Disk Controllers. Com- 
mands, status, and data transfers are performed in 
the same way. Software generated for the 179X can 
be transferred to a 279X system without modification. 



In addition to the WD179X, the WD279X contains an 
internal Dat a Sepa rator and Write precompensation 
circuit. The TEST (Pin 22) line is used to adjust both 
data separator and precompensation. When 
TEST = 0, the WD (Pin 31) line is internally connected 
to the output of the write precomp one-shot. Adjust- 
ment of the WPW (Pin 33) line can then be 
accomplished. 

A second one-shot tracks the precomp setting at 
approximately 3:1 to insure adequate Write Data pulse 
widths. 



Similarly, Data separation is also adjusted with TEST 
= 0. The TG43 (Pin 29) line is internally connected 
to the output of the read data one-shot, which is 
adjusted via the RPW (Pin 18) line. The DIRG (Pin 16) 
line contains the Read Clock output (.5 MHz for 8" 
drives). The VCO Trimming capacitor (Pin 26) is 
adjusted for center frequency. 

Internal timing signals are used to generate pulses 
during the adjustment mode so that these 
adjustment s can be made while the device is in- 
circuit. The TEST line also contains a pull-up resistor, 
so adjus tments can be performed simply by groun- 
ding the TEST pin, overriding the pull-up. The TEST 
pin cannot be used to disable stepping rates during 
operation as its function is quite different from the 
WD179X. 

Other pins on the device also Include pull-up resistors 
and may be left open to satisfy a Logic 1 co ndition. 
These are: ENP, 5/8, ENMF, WPRT, DDEN, HLT, 
TEST, and MR. 

GENERAL DISK READ OPERATIONS 

Sector lengths of 128, 256, 512 or 1024 are obtain- 
able in either FM or MFM formats. For FM, DDEN 
should be placed to logical "1." For MFM formats, 
DDEN should be placed to a logical "0". Sector 
lengths are determined at format time by the fourth 
byte in the "ID" field. 



Sector Length Table* 



Sector Length 
Field (hex) 



Number of Bytes 
in Sector (decimal) 



00 
01 
02 
03 



128 
256 
512 
1024 



"2795/97 may vary - see command summary. 

The WD279X recognizes tracks and sectors numbered 
00-FF Hex. However, due to programming restrictions, 
only tracks and sectors GO through F4 can be 
formatted. 



O 

<o 
X 

■ 

o 



Floppy Disk Controller Devices 



1-97 



o 

ro 

CD 

X 

o 
ro 



GENERAL DISK WRITE OPERATION 

When writing is to take place on the diskette the Write 
Gate (WG) output is activated, allowing cun-ent to flow 
Into the Read/Write head. As a precaution to 
erroneous writing the first data byte must be loaded 
into the Data Register in response to a Data Request 
from the WD279X before the Write Gate signal can 
be activated. 



Writing is inhibited when the Write Protect input is 
a logic low, in which case any Write command is 
immediately terminated, an interrupt is generated and 
the Write Protect status bit is set. 

For write operations, the WD279X provides Write Gate 
(Pin 30) and Write Data (Pin 31) outputs. Write data 
consists of a series of pulses set to a width approx- 
imately three times greater then the precomp adjust- 
ment. Write Data provides the unique address marks 
in both formats. 



READY 

Whenever a Read or Write command (Type II or III) 
is received the WD279X samples the Ready input, if 
this input is logic low, the command is not executed 
and an interrupt is generated. All Type I commands 
are performed regardless of the state of the Ready 
input. Also, whenever a Type II or Hi command is 
received, the TG43 signal output is updated. TG43 
may be tied to ENP to enable write precompensation 
on tracks 44-76. 

COMMAND DESCRIPTION 

The WD279X will accept eleven commands. Com- 
mand words should only be loaded in the Command 
Register when the Busy status bit is off (Status bit 
0). The one exception is the Force Intenupt command. 
Whenever a command is being executed, the Busy 
status bit is set. When a command is completed, an 
interrupt is generated and the Busy status bit is reset. 
The Status Register indicates whether the completed 
command encountered an error or was fault free. For 
ease of discussion, commands are divided into four 
types. Commands and types are summarized in 
Table 1. 



1-98 



Floppy Disk Controller Devices 



TABLE 1. COMMAND SUMMARY 



A. Commands for Models: WD2791 


WD2793 














B. Commands for Models: WD2795, WD2797 








Bits 
















Bits 






Type Command 


7 6 


5 


4 


3 


2 







7 


6 


5 


4 3 


2 


1 


1 Restore 











h 


V 




^0 











h 


V 


'^ '0 


1 Seek 








1 


h 


V 




^0 











1 h 


V 


'^ '0 


1 Step 





1 


T 


h 


V 


^0 


^0 








1 


T h 


V 


M ^0 


1 Step-in 


1 





T 


h 


V 




^0 





1 





T h 


V 


n ^0 


1 Step-out 


1 


1 


T 


h 


V 




^0 





1 


1 


T h 


V 


M ^0 


II Read Sector 


1 





m 


S 


E 


C 













m L 


E 


U 


II Write Sector 


1 


1 


m 


S 


E 


c 


^0 







1 


m L 


E 


U ^0 


III Read Address 


1 1 











E 










1 








E 


U 


III Read Track 


1 1 


1 








E 










1 


1 





E 


U 


III Write Track 


1 1 


1 


1 





E 










1 


1 


1 


E 


U 


IV Force Interrupt 


1 1 





1 


'3 


'2 


'1 


'0 




1 





1 '3 


'2 


'1 '0 



TABLE 2. FLAG SUMMARY 



Connmand 
Type 


Bit 
No(s) 




Description 


1 


0, 1 


n "^0= Stepping Motor Rate See 
Table 3 for Rate Summary 




1 


2 


V = Track Number Verify Flag 


V = 0,No verify 

V = 1, Verify on destination track 


1 


3 


hi = Head Load Flag 


h = O.Unioad head at beginning 
h = 1,Load head at beginning 


1 


4 


T = Track Update Flag 


T = 0,No update 

T = 1, Update track register 


II & III 





^0 = Data Address Mark 


«0 = 0,FB(DAM) 

^0 = 1,F8(deleted DAM) 


II 


1 


C = Side Compare Flag 


C = O.DIsabie side compare 
C = 1, Enable side compare 


II & ill 


1 


U = Update SSO 


U = O.Update SSO to 
U = 1, Update SSO to 1 


II & ill 


2 


E = 15 MS Delay 


E = 0,No. 15 MS delay 

E = 1,15 MS delay (30 MS for 1 Mhz) 


11 
II 

li 


3 
3 

4 


S = Side Compare Flag 
L = Sector Length Flag 


S = 0,Compare for side 
S = 1, Compare for side 1 


LSB's Sector Length in ID Field 
GO 01 10 11 


L = 256 512 1024 128 


L = 1 128 256 512 1024 


m = Multiple Record Flag 


m = 0,Single record 
m = 1,Multiple records 


iV 


0-3 


'x = Interrupt Condition Flags 

'0 = 1 Not Ready To Ready Transition 

h = 1 Ready To Not Ready Transition 

'2 = 1 Index Pulse 

'3 = 1 Immediate Interrupt, Requires A Reset* 

'3-'0 = Terminate With No Interrupt (INTRQ) 



NOTE: See Type IV Command Description for further information. 



Floppy Disk Controller Devices 



1-99 



a 

•>! 

o 



WRITE PRECOMPENSATION 

When operating in Doubie Density mode (DDEN = 0), 
the WD279X has the capability of providing a user- 
defined precompensation value for Write Data. An 
external potentiometer (10K) tied to the WPW signal 
(Pin 33) allows a setting of 100 to 300 ns from nominal. 

Setting the Write precomp value is accomplished by 
forcing the TEST line (Pin 22) to a Logic 0. A stream 
of pulses can then be seen on the Write Data (Pin 
31) line. Adjust the WPW Potentiometer for the desired 
pulse width. This adjustment may be perform ed in- 
circuit since Write Gate (Pin 30) is Inactive while TEST 
= 0. 

DATA SEPARATION 

The WD279X can operate with either an external data 
separator or its ownJntemal recovery circuits. The 
condilion of the TEST line (Pin 22) In conjunction 
with MR (Pin 19) will select internal or external mode. 

To program the 279X for extfimal VCO, a MR 
pulse must be applied while TEST = 0. A clock 
equivalent to eight times the data rate (e.g., 4.0 MHz 
for 8" Double Density) is applied to the VCO input 
(Pin 26). The feedback reference voltage is available 
on the Pump output (EiD_23) for external Integration 
to control the VCO. TEST is returned to a Logic 1 
for normal operation. 

Note: To malntaiD this mode, TEST must be held 
low whenever MR Is applied. 

For internal VCCLoperatlon, the TEST line must be 
high during the MR pulse, then set to a Logic for 
the adjustment procedure. 

A 50K Potentiometer tied to the RPW input (Pin 18) 
is used to set the internal Read Data pulse for pro- 
per phasing. With a scope on Pin 29 (TG 43), adjust 
the RPW pulse (250 ns for 8" Double Density). An ex- 
ternal variable capacitor of C-60 pf is tied to the VCO 
input (Pin 26). It Is highly recommended to use at least 
a negative 3500 PPM Temperature coefficient trim- 
mer capacitor. With a frequency counter on Pin 16 
(DIRC) adjust the trimmer cap to yield the appropriate 
Data_Bal£ (500 KHz for 8" Double .Density). 
The DDEN line must be low while the 5/8 line is 
held high or the adjustment times above will be 

doubled. 

After adjustments have been made, the TEST pin 
is returned to a Logic 1 and the device is ready for 
operation. Adjustments may be made In-circult since 
the DIRC and TG43 lines may toggle without affec- 
ting the drive. 

The PUMP output (Pin 23) consists of positive and 
negative pulses, which their duration is equivalent to 
the phase difference of Incoming Data vs. VCO fre- 
quency. This signal is internally connected to the VCO 
input, but a filter is needed to connect these pulses 
to a slow moving DC voltage. 

The internal phase-detector is unsymmetrical for a 
random distribution of data pulses by a factor of two. 
In favor of a PUMP UP condition. Therefore, it Is 
desirable to have a PUMP DOWN twice as respon- 
sive to prevent run-away during a lock attempt. 

A first order lag-lead filter can be used at the PUMP 
output (Pin 23). This filter controls the Instantaneous 



response of the VCP to bit-shlfted data (jitter) as well 
as the response to normal frequency shift, i.e., the 
lock-up time. A balance niust be accomplished bet- 
ween the two conditions to Inhibit over- 
responsiveness to jitter and to prevent an extremely 
wide lock-up response, leading to PUMP runaway. The 
filter affects these two reactions in mutually opposite 
directions. 

The following Filter Circuit is recommended for 8" 
FM/MFM: 



PUMP 
(PIN 23) 




IN914 



Since 5V4" Drives operate at exactly one-half the data 
rate (250 Kb/sec) the above capacitor should be 
doubled to .2 or .22 fii. 

NOTE 1: A Diode with the lowest on resistance will 
enhance PUMP response. 

NOTE 2: It is recommended to replace the 1 K resistor 
with a IK (nominal at 25°c) thermlster (approximating 
400 ohms at 50°c and approximatley 2.8K ohms at 
0°c) to improve capture range. 

TYPE I COMMANDS 

The Type I Commands Include the Restore, Seek, 
Step, Step-in, and Step-Out commands. Each of the 
Type I Commands contains a rate field (ro r^), which 
determines the stepping motor rate as defined In 
Table 3. 

A 2^s (MFM) or 4;iS (FM) pulse is provided as an out- 
put to the drive. For every step pulse Issued, the drive 
moves one track location In a direction determined 
by the direction output. The chip will step the drive 
in the same direction it last stepped unless the com- 
mand changes the direction. 

The direction signal Is active high when stepping in 
and low when stepping out. The direction signal Is 
valid before the first stepping pulse is generated. The 
rates (shown in Table 3) can be applied to a Step- 
Direction Motor through the device interface. 

TABLE 3. STEPPING RATES 



CLK 


2 MHz 


1 MHz 


R1 RO 


TEST= 1 


TEST = 1 





3 ms 


6 ms 


1 


6 ms 


12 ms 


1 


10 ms 


20 ms 


1 1 


15 ms 


30 ms 



After the last directional step, an additional 15 
milliseconds of head settling time takes place if the 
Verify flag is set in Type I commands. Note that this 
time doubles to 30 ms for a 1 MHz clock. There Is 
also a 15 ms head settling time If the E flag is set 
In any Type II or III command. 



1-100 



Floppy Disk Controller Devices 



When a Seek, Step, or Restore command is executed 
an optional verification of Read-Write head position 
can be performed by setting bit 2 (V = 1) in the com- 
mand word to a logic 1. The verification operation 
begins at the end of the 15 millisecond settling time 
after the head is loaded against the media. The track 
number from the first encountered ID Field is com- 
pared against the contents of the Track Register. If 
the track numbers compare and the ID Field Cyclic 
Redundancy Check (CRC) is correct, the verify opera- 
tion is complete and an INTRQ is generated with no 
errors. If there is a match but not a valid CRC, the 
CRC error status bit is set (Status bit 3), and the next 
encountered ID field is read from the disk for the 
verification operation. 

The WD279X must find an ID field with correct track 
number and correct CRC within 5 revolutions of the 
media; otherwise the seek error is set and an INTRQ 
is generated. If V = 0, no verification is performed. 

The Head Load (HLD) output controls the movement 
of the read/write head against the media. HLD is 
activated at the beginning of a Type I command if 
the h flag is set (h = 1), at the end of the Type I com- 
mand if the verify flag (V = 1), or upon receipt of any 
Type II or III command. Once HLD is active it remains 
active until either a Type I command is received with 
(h = and V = 0); or if the WD279X is in an idle state 
(non-busy) and 15 index pulses have occurred. 

Head Load timing (HLT) is an input to the WD279X 
which is used for the head engage time. When HLT 
= 1, the WD279X assumes the head is completely 
engaged. The head engage time is typically 30 to 100 
ms depending on drive. The low to high transition on 
HLD is typically used to fire a one shot. The output 
of the one shot is then used for HLT and supplied 
as an input to the WD279X. 




HEAD LOAD TIMING 

When both HLD and HLT are true, the WD279X will 
then read from or write to the media. The "and" of 
HLD and HLT appears as status Bit 5 in Type I status. 

In summary for the Type I commands: if h = and 
V = 0, HLD is reset. If h = 1 and V = 0, HLD is set 
at the beginning of the command and HLT is not 
sampled nor is there an internal 15 ms delay. If h = 
and V = 1, HLD is set near the end of the com- 
mand, an internal 15 ms occurs, and the WD279X 
waits for HLT to be true. If h = 1 and V = 1, HLD 
is set at the beginning of the command. Near the end 
of the command, after all the steps have been issued, 
an internal 15 ms delay occurs and the WD279X then 
waits for HLT to occur. 

For Type II and III commands with E flag off, HLD 
is made active and HLT is sampled until true. With 
E flag on, HLD is made active, an internal 15 ms delay 
occurs and then HLT is sampled until true. 



RESTORE (SEEK TRACK 0) 

Upon receipt of this com mand the Track 00(TR00) 
input is sampled. If TROO is active low indicating the 
Read- Write head is positioned over track 0, the Track 
Register is l oaded with zeroes and an interrupt is 
generated. If TROO is not active low, stepping pulses 
at a rate specified by the ''I'^Q field are issued until 
the TROO input is activated. At this time the Track 
Register is loade d wit h zeroes and an interrupt is 
generated. If the TROO input does not go active low 
after 255 stepping pulses, the WD279X terminates 
operation, interrupts, and sets the Seek error status 
bit. A verification operation also takes place if the V 
flag is set. The h bit allows the head to be loaded 
at the start of command. Note that the Restore com- 
mand is executed when MR goes from an active to 
an inactive state. 

SEEK 

This command assumes that the Track Register con- 
tains the track number of the current position of the 
Read/Write head and the Data Register contains 
the desired track number. The WD279X will update 
the Track register and issue stepping pulses in the 



GED 





STEPIN^-^ 


»ES 




SET 

DIRECTION 










yc 




COMMAND V^ 


YES 




BESET 
DMECTION 




STEP-OUT/^ 








|no 




COMMAND >v 


YES 








STEP ^^ 








* 


jTnO 





















NO ;. RESTORE 








o 

N> 
CO 

X 

I 

o 



TYPE I COMMAND FLOW 



Floppy Disk Controller Devices 



1-101 



a 

o 

lO 




SET OrRECTION 








TYPE I COMMAND FLOW 

appropriate direction until the contents of the Tracl< 
register are equal to the contents of the Data Register 
(the desired track location). A verification operation 
takes place if the V flag is on. The h bit allows the 
head to be loaded at the start of the command. An 
interrupt is generated at the completion of the com- 
mand. Note: When using multiple drives, the track 
register must be updated for the drive selected before 
seeks are issued. 

STEP 

Upon receipt of this command, the WD279X issues 
one stepping pulse to the disk drive. The stepping 
motor direction is the same as in the previous step 
command. After a delay determined by the '^VO field, 
a verification takes place If the V flag is on. If the T 
flag is on, the Track Register is updated. The h bit 
allows the head to be loaded at the start of the 
command. 




INTRO RESET BUSY 



ISY J 






(INTRO ^ 

RESET BUSY J ' 



TYPE I COMMAND FLOW 

An interrupt is generated at the completion of the 
command. 

STEP-IN 

Upon receipt of this command, the WD279X issues 
one stepping pulse in the direction away from track 
zero. If the T flag is on, the Track Register is 
incremented by one. After a delay determined by the 
'VO field, a verification takes place if the V flag is on. 
The h bit allows the head to be loaded at the start 
of the command. An interrupt is generated at the com- 
pletion of the command. 

STEP-OUT 

Upon receipt of this command, the WD279X issues 
one stepping pulse in the direction towards track 0. 
If the T flag is on, the Track Register is decremented 
by one. After a delay determined by the ^1''0 field, a 



1-102 



Floppy Disk Controller Devices 



verification takes place if the V flag is on. The h bit 
allows the head to be loaded at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. 

EXCEPTIONS 

On the WD2795/7 devices, the SSO output is not 
affected during Type I commands, and an internal 
side compare does not take place when the (V) Verify 
Flag is on. 

TYPE II COMMANDS 

The Type II Commands are the Read Sector and Write 
Sector commands. Prior to ioadng the Type II Com- 
mand into the Command Register, the computer must 
load the Sector Register with the desired sector 
number. Upon receipt of the Type II command, the 
busy status Bit is set. If the E flag = 1 (this is the 
normal case) HLD is made active and HLT is sampled 
after a 15 msec delay. If the E flag is 0, the head is 
loaded and HLT sampled with no 15 msec delay. 




/iNTBO BESET BUsA 
ISET WRITE PROTECT J 




UNO/ 



BRING IN SECTOR LENGTH FIELD 

STORE LENGTH IN INTERNAL 

REGISTER 








TYPE II COMMAND 



TYPE II COMMAND 



When an ID field is located on the disk, the WD279X 
compares the Track Number on the ID field with the 
Track Register. If there is not a match, the next en- 
countered ID field is ready and a comparison is again 
made. If there was a match, the Sector Number of 
the ID field is compared with the Sector Register. If 
there is not a Sector match, the next encountered ID 
field is read off the disk and comparisons again made. 
If the ID field CRC is correct, the data field is then 
located and will be either written into, or read from 
depending upon the command. The WD279X must 
find an ID field with a Track number. Sector number, 
side number, and CRC within 5 revolutions of the disk; 
otherwise, the Record Not Found status bit is set 
(Status bit 4) and the command is terminated with 
an interrupt. 

Each of the Type II Commands contains an (m) flag 
which determines if multiple records (sectors) are to 
be read or written, depending upon the command. If 
m = 0, a single sector is read or written and an in- 
terrupt is generated at the completion of the 
command. 



O 

CO 

X 

I 

o 



Floppy Disk Controller Devices 



1-103 



o 

lo 

o 



READ SECTOR 
SEQUENCE 




c 



3 



W 



INTRO RESET BUSV 



9 



TYPE II COMMAND 

If m = 1, multiple records are read or written with 
sector register Internally updated so that an address 
verification can occur on the next record. The WD279X 
will continue to read or write multiple records and 
update the sector register in numerical ascending 
sequence until the sector register exceeds the 
number of sectors on the track or until the Force Inter- 
rupt command Is loaded into the Command Register, 
which terminates the command and generates an 
interrupt. 

For example: If the WD279X is Instructed to read sec- 
tor 27 and there are only 26 on the track, the sector 
register exceeds the number available. The WD279X 
will search for 5 disk revolutions, interrupt out, reset 
busy, and set the Record Not Found status bit. 

The Type II commands for WD2791-93 also contain side 
select compare flags. When C = (Bit 1) no side com- 
parison Is made. When C = 1, the LSB of the side 
number is read off the ID field of the disk and compared 
with the contents of the (S) flag (Bit 3). If the S flag com- 
pares with the side number recorded in the ID field. 



WRITE SECTOR 
SEQUENCE 




^y^lNTHO RESET BUSV^ 
^\ SETIOST OAIA j 



DELAV 1 BYTE OF GAP 



OEIAT 11 BYTES 



WRITE DATA AM 
ACCORDING TO AO FIELD 
Of WRITE COMMAND 



OR TO OSR. SET DRO 



WRITE BYTE TO DISK 




SET DATA 

LOST 

WRITE BYTE 

OF 2ER0S 



Q 



WRITE CRC 

— r~ 



WRITE 1 BYTE OF FF 



TURN OFF WG 







TYPE II COMMAND 

the WD279X continues with the ID search. If a com- 
parison is not made within 5 index pulses, the inter- 
rupt line is made active and the Record-Not-Found 
status bit Is set. 

The Type 11 and III for the WD2795-97 contain a side 
select flag (Bit 1). When U = 0, SSO Is updated to 
0. Similarly, U = 1 updates SSO to 1. The chip com- 
pares the SSO to the ID field. If they do not compare 
within 5 revolutions the interrupt line is made active 
and the RNF status bit is set. 

The WD2795/7 READ SECTOR and WRITE SECTOR 
commands include a 'L' flag. The 'L' flag. In conjunc- 
tion with the sector length byte of the ID field, allows 
different byte lengths to be implemented in each sec- 
tor. For IBM compatibility, the 'L' flag should be set 
to one. 

READ SECTOR 

Upon receipt of the Read Sector command, the head 
is loaded, the Busy status bit set, and when an ID 



1-104 



Floppy Disk Controller Devices 



field is encountered that has the correct track number, 
correct sector number, correct side number, and cor- 
rect CRC, the data field Is presented to the computer. 
The Data Address Mark of the data field must be 
found within 30 bytes in single density and 43 bytes 
in double density of the last ID field CRC byte; if not, 
the ID field search is repeated. 

When the first character or byte of the data field has 
been shifted through the DSR, It is transferred to the 
DR, and DRQ Is generated. When the next byte is ac- 
cumulated in the DSR, It Is transferred to the DR and 
another DRQ Is generated. If the computer has not 
read the previous contents of the DR before a new 
character Is transferred that character is lost and the 
Lost Data Status Bit Is set. This sequence continues 
until the complete data field has been Inputted to the 
computer. If there is a CRC error at the end of the 
data field, the CRC error status bit Is set, and the com- 
mand Is terminated (even If It Is a multiple sector 
command). 

At the end of the Read operation, the type of Data 
Address Mark encountered in the data field is 
recorded in the Status Register (Bit 5) as shown: 

STATUS 
BITS 



Deleted Data Mark 
Data Mark 



1 


WRITE SECTOR 

Upon receipt of the Write Sector command, the head 
Is loaded (HLD active) and the Busy status bit is set. 
When an ID field is encountered that has the correct 
track number, correct sector number, correct side 
number, and correct CRC, a DRQ Is generated. The 
WD279X counts off 11 bytes In single density and 22 
bytes in double density from the CRC field and the 
Write Gate (WG) output is made active If the DRQ is 
serviced (i.e., the DR has been loaded by the com- 
puter). If DRQ has not been serviced, the command 
is terminated and the Lost Data status bit is set. If 
the DRQ has been sen/Iced, the WG is made active 
and six bytes of zeroes in single density and 12 bytes 
in double density are then written on the disk. At this 
time the Data Address Mark Is then written on the 
disk as determined by the ^0 field of the command 
as shown below: 



Data Address Mark (Bit 0) 



The WD279X then writes the data field and generates 
DRQ's to the computer. If the DRQ Is not serviced 
in time for continuous writing the Lost Data Status 
Bit is set and a byte of zeroes Is written on the disk. 
The command is not terminated. After the last data 
byte has been written on the disk, the two-byte CRC 
Is computed Internally and written on the disk 
followed by one byte of FE in FM or in MFM. The WG 
output is then deactivated. For a 2 MHz clock the 
INTRQ will set 8 to 12f/sec after the last CRC byte 
is written. For partial sector writing, the proper 
method is to write the data and fill the balance with 
zeroes. By letting the chip fill the zeroes, errors may 
be masked by the lost data status and Improper CRC 
Bytes. 

TYPE III COMMANDS 
READ ADDRESS 

Upon receipt of the Read Address command, the head 
is loaded and the Busy Status Bit Is set. The next 
encountered ID field is then read in from the disk, and 
the six data bytes of the ID field are assembled and 
transferred to the DR, and a DRQ is generated for 
each byte. The six bytes of the ID field are shown 
below: 



TRACK 
ADDR 


SIDE 
NUMBER 


SECTOR 
ADDR 


SECTOR 
LENGTH 


CRC 

1 


CRC 
2 


1 


2 


3 


4 


5 


6 



1 Deleted Data Mark 

Data Mark 



Although the CRC characters are transferred to the 
computer, the WD279X checks for validity and the 
CRC error status bit is set if there is a CRC error. The 
Track Address of the ID field Is written into the sec- 
tor register so that a comparison can be made by the 
host. At the end of the operation an interrupt is 
generated and the Busy Status Is reset. 

READ TRACK 

Upon receipt of the READ track command, the head 
is loaded, and the Busy Status bit Is set. Reading 
starts with the leading edge of the first encountered 
index pulse and continues until the next Index pulse. 
All Gap, Header, and data bytes are assembled and 
transferred to the data register and DRQ's are 
generated for each byte. The accumulation of bytes 
Is synchronized to each address mark encountered. 
An Interrupt is generated at the completion of the 
command. 

This command has several characteristics which 
make It suitable for diagnostic purposes. They are: 
no CRC checking is performed; gap information Is 



O 
to 

o 

lO 



Floppy Disk Controller Devices 



1-105 



o 

CO 

>< 

o 
ro 



included in the data stream; the internal side com- 
pare is not performed; and the address marl< detec- 
tor is on for the duration of the command. Because 
the A.M. detector is always on, write splices or noise 
may cause the chip to look for an A.M. If an address 
mark does not appear on schedule the Lost Data 
status flag will be set. 

The ID A.M., ID field, ID CRC bytes, DAM, Data and 
Data CRC Bytes for each sector will be correct. The 
Gap Bytes may be read incorrectly during write-splice 
time because of synchronization. 

Because these synchronization problems almost 
always occur in the Data Area, this command will not 
function as a Track Copy and should be used only 
as a Diagnostic Program to test the ability to read 
addresses. 

WRITE TRACK FORMATTING THE DISK 

(Refer to section on Type III commands for flow 
diagrams.) 

Formatting the disk is a relatively simple task when 
operating programmed I/O or when operating under 
DMA with a large amount of memory. Data and gap 
information must be provided at the computer inter- 
face. Formatting the disk is accomplished by posi- 
tioning the R/W head over the desired track number 
and issuing the Write Track command. 

Upon receipt of the Write Track command, the head 
is loaded and the Busy Status bit is set. Writing starts 
with the leading edge of the first encountered index 
pulse and continues until the next index pulse, at 
which time the interrupt is activated. The Data 
Request is activated immediately upon receiving the 
command, but writing will not start until after the first 
byte has been loaded into the Data Register. If the 
DR has not been loaded by (within three byte times) 
the operation Is terminated making the device Not 
Busy, the Lost Data Status Bit is set, an the interrupt 
is activated. If a byte is not present in the DR when 
needed, a byte of zeroes is substituted. 

This sequence continues from one index mark to the 
next index mark. Normally, whatever data pattern 
appears in the data register is written on the disk with 
a normal clock pattern. However, if the WD279X 
detects a data pattern of F5 through FE in the data 
register, this is interpreted as data address marks with 
missing clocks or CRC generation. 

The CRC generator is initialized when any data byte 
from F8 to FE is about to be transferred from the DR 
to the DSR or by receipt of F5 in MFM. An F7 pat- 
tern will generate two CRC characters in FM or MFM 




< INTRO ^ 

■RESET BUSY J 



Q 



SET INTRO 
LOST DATA 
RESET BUSY 





TYPE III COMMAND WRITE TRACK 



1-106 



Floppy Disk Controller Devices 




(: 



INTRO RESET BUSV 



y^ DOES ^v 
^ DSR H ^ 


»ES 
TES 

VES 


WRITE JCHC 
CHARS CLK ■ FF 






Jno 




y^ DOES ^V 


WRITE FC 

ClK d; 






Jno 




^^^OOES^^^ 


WRITE FO FE OR 
F«.FB CLK . CT 

INITIALIZE CRC 


^>^ OR f i-FB y'^ 




^<(C 




WRITE OSR 
ClK : FF 


^ y'^ RH»s ^v 

-^ INDEX MARK ^ 


NO 






^/^ MAS ^V 


WRITE 
BYTE OF ZEROS 
SET DATA LOST 


^V^LOAOED' >^ 




1 






WRITE AriNUFM 
WITH MISSING CLOCK 
INITIALIZE CRC 



TYPE III COMMAND WRITE TRACK 



or by receipt of F5 in MFM. An F7 pattern will 
generate two CRC characters in FM or MFM. As a 
consequence, the patterns F5 through FE must not 
appear in the gaps, data fields, or ID fields. Also, 
CRC's must be generated by an F7 pattern. 
Disks may be formatted in IBM 3740 or System 34 
formats with sector lengths of 128, 256, 512, or 1024 
bytes. 
TYPE IV COMMANDS 

The Forced Interrupt command is generally used to 
terminate a multiple sector Read or Write Command 
or to insure Type I status in the Status Register. This 
command can be loaded into the command register 
at any time. If there is a current command under ex- 
ecution (busy status bit set) the command will be ter- 
minated and the busy status bit reset. 
The lower four bits of the command determine the 
conditional interrupt as follows: 
'0 - Not-Ready to Ready Transition 
'l = Ready to Not-Read Transition 
'2 = Every Index Pulse 
'3 = Immediate Interrupt 

The conditional interrupt is enabled when the cor- 
responding bit positions of the command ('3 -'O) are 
set to a 1. Then, when the condition for interrupt is 
met, the INTRQ line will go high signifying that the 
condition specified has occurred. If '3 -'O are all set 
to zero (HEX DO), no interrupt will occur but any com- 
mand presently under execution will be immediately 
terminated. When using the immediate interrupt con- 
dition ('3 =: 1), an interrupt will be immediately 
generated and the current command terminated. 
Reading the status or writing to the command register 
will not automatically clear the interrupt. The HEX DO 
is the only command that will enable the immediate 
interrupt (HEX D8) to clear on a subsequent load com- 
mand register or read status register operation. Follow 
a HEX D8 with DO command. 
Wait 8 micro sec (double density) or 16 micro sec 
(single density) before issuing a new command after 
issuing a forced interrupt (times double when clock 
= 1 MHz). Loading a new command sooner than this 
will nullify the forced interrupt. 
Forced interrupt stops any command at the end of 
an internal micro-instruction and generates INTRQ 
when the specified condition is met. Forced interrupt 
will wait until ALU operations in progress are com- 
plete (CRC calculations, compares, etc.). 



CONTROL BYTES FOR INITIALIZATION 



DATA PATTERN 
IN DR (HEX) 


WD279X INTERPRETATION 


WD279X INTERPRETATION 


IN FM (DDEN = 1) 


IN MFM (DDEN = 0) 


00 thru F4 


Write 00 thru F4 with CLK = FF 


Write 00 thru F4, in MFM 


F5 


Not Allowed 


Write A1* in MFM, Preset CRC 


F6 


Not Allowed 


Write 02** in MFM 


F7 


Generate 2 CRC bytes 


Generate 2 CRC bytes 


F8 thru FB 


Write F8 thru FB, CLK = C7, Preset CRC 


Write F8 thru FB, in MFM 


FC 


Write FC with CLK = D7 


Write FC in MFM 


FD 


Write FD with CLK = FF 


Write FD in MFM 


FE 


Write FE, CLK = C7, Preset CRC 


Write FE in MFM 


FF 


Write FF with CLK = FF 


Write FF in MFM 



o 

N> 
■>! 
CO 
X 

O 
N> 



*Missing clock transition between bits 4 and 5. 



**Missing clock transition between bits 3 and 4. 



Floppy Disk Controller Devices 



1-107 



o 

ro 

X 

I 

o 



More than one condition may be set at a time. If for 
example, the READY TO NOT-READY condition ('l 
= 1) and the Every Index Pulse ('2 = 1) are both set, 
the resultant command would be HEX "DA." The 
"OR" function is performed so that either a READY 
TO NOT-READY or the next Index Impulse will cause 
an interrupt condition. 

STATUS REGISTER 

Upon receipt of any command, except the Force Inter- 
rupt command, the Busy Status bit is set and the rest 
of the status bits are updated or cleared for the new 



command. If the Force Interrupt Command is receiv- 
ed when there is a current command under execu- 
tion, the Busy status bit is reset, and the rest of the 
status bits are unchanged. If the Force Interrupt Com- 
mand is received when there is not a current com- 
mand under execution, the Busy Status bit is reset 
and the rest of the status bits are updated or cleared. 
In this case, Status reflects the Type I commands. 

The user has the option of reading the Status Register 
through program control or using the DRQ line with 
DMA or interrupt methods. When the Data Register 



c 



J 



SET BUSY 

RESET STATUS 

BITS 2. 4,5 




COPYSF 
TOSSO 
(27957 


LAG 
INE 
MLV) 






SETHLD 






■c 



3 



TYPE III COMMAND 

Read Track/Address 



1-108 



Floppy Disk Controller Devices 



I'l READ ADDRESS 
y SEQUENCE 




<W^ 






*Ie't""hn™ J 






"v. OCTECTEO ^^ 

1 






1 




BYTE 10 on 
1 

SETono 




TRANSFER TRACK 






REGiSTOfl 






J^ 








<^.„"^\ 


YES 


SET cue 




\ ' / 






>[<o 


1 






1* 






( 


r ^^^^ ^ 


) 


TYPE III COMMAND 


Read Track/Address 



Is read the DRQ bit in the Status Register and the 
DRQ line are automatically reset. A write to the Data 
register also causes both DRQ's to reset. 

The busy bit in the status may be monitored with a 
user program to determine when a command is com- 
plete, in lieu of using the INTRQ line. When using the 
INTRQ, a busy status check is not recommended 
because a read of the status register to determine 
the condition of busy will reset the INTRQ line. 

The format of the Status Register is shown below: 



BITS 


7 


6 


5 


4 


3 


2 


1 





S7 


S6 


S5 


S4 


S3 


S2 


S1 


SO 



Status varies according to the type of command 
executed as shown in Table 4. 

Because of internal sync cycles, certain time delays 
must be observed when operating under programmed 
I/O. They are: (times double when clock = 1 MHz) 



Operation 


Next Operation 


Delay Req'd. 
FM MFM 


Write to 
Command Reg. 


Read Busy Bit 
(Status Bit 0) 


12fiS 6fiS 


Write to 
Command Reg. 


Read Status 
Bits 1-7 


28ms 14ms 


Write Any 
Register 


Read From Diff. 
Register 






o 
to 

<o 

X 

I 

o 
ro 



IBM 3740 FORMAT - 128 BYTES/SECTOR 

Shown below is the IBM single density-format with 
128 bytes/sector. In order to format a diskette, the 
user must issue the Write Track Command, and load 
the Data Register with the following values. For every 
byte to be written, there is one Data Request. 



NUMBER 


HEX VALUE OF 


OF BYTES 


BYTE WRITTEN 


40 
6 


FF (or 00)3 
00 




1 

^26 

6 


FC (Index Mark) 
FF (or 00) 
00 




1 
1 


FE (ID Address Mark) 
Track Number 




1 
1 
1 
1 
11 
6 


Side Number (00 or 01) 
Sector Number (1 thru 1A) 
00 (Sector Length) 
F7 (2 ORG'S written) 
FF (or 00) 
00 




1 

128 

1 

27 

247^ 


FB (Data Address Mark) 
Data (IBM uses E5) 
F7 (2 ORO's written) 
FF (or 00) 
FF (or 00) 



1 . Write bracketed field 26 times. 

2. Continue writing until 279X interrupts out. 
Approx. 247 bytes. 

3. A '00' option is allowed. 

IBM SYSTEM 34 FORMAT 
256 BYTES/SECTOR 

Shown below is the IBM dual-density format with 256 
bytes/sector. In order to format a diskette the user 
must issue the Write Track Command and load the 
Data Register with the following values. For every byte 
to be written, there is one Data Request. 



Floppy Disk Controller Devices 



1-109 



o 
ro 

CO 

X 
o 

N3 



NUMBER 


HEX VALUE OF 


OF BYTES 


BYTE WRITTEN 


80 


4E 


12 


00 


3 

1 

*50 


F6 (Writes C2) 
FC (Index Mark) 
4E 




12 


00 




3 
1 
1 
1 
1 
1 
1 
22 


F5 (Writes A1) 
FE (ID Address Marl<) 
Track Number (0 tliru 4C) 
Side Number (0 or 1) 
Sector Number (1 thru 1A) 
01 (Sector Length) 
F7 (2 CRC's written) 
4E 




12 


00 




3 

1 

256 


F5 (Writes A1) 

FB (Data Address Mark) 

DATA 




1 
54 


F7 (2 CRC's written) 
4E 


598** 


4E 



'Write bracketed field 26 times. 
'Continue writing until 279X interrupts out. 
Approx. 598 bytes. 



1. NON-IBM FORMATS 

Variations in the IBM formats are possible to a limited 
extent if the following requirements are met: 

1. Sector size must be 128, 256, 512, of 1024 bytes. 

2. Gap 2 cannot be vaired from the IBM format. 

3. 3 bytes of A1 must be used in MFM. 

In addition, the Index Address Mark is not required 
for operation by the WD279X. Gap 1,3, and 4 lengths 
can be as short as 2 bytes for WD279X operation, 
however PLL lock up time, motor speed variation, 
write splice area, etc. will add more bytes to each gap 
to achieve proper operation. It is recommended that 
the IBM format be used for highest system reliability. 





FM 


MFM 


Gap 1 


16 bytes FF 


32 bytes 4E 


Gap II 


11 bytes FF 


22 bytes 4E 


* 


6 bytes 00 


12 bytes 00 


* 




3 bytes A1 


Gap III** 


10 bytes FF 


24 bytes 4E 




4 bytes 00 


8 bytes 00 
3 bytes A1 


Gap IV 


16 bytes FF 


16 bytes 4E 



*Byte counts must be exact. 
*Byte counts are minimum, except exactly 3 bytes 
of A1 must be written. 



P»rs,c.i im 


■ r 


-n 




























s 


^- „.e..»«ss..,. 








'"wM^N*r" 


"S 


.hIe 


i-E 


i- 


~ 


% 


J& " 


'h -" 


-E" 


- 


"i;° "' 


..4 
.. 


'ih 


„., 


°iT° "" 








/ 


^~~~^-.^,_^ /■ 


X 


^^^ \ 








'=' 


-■" 


x%. 


ss". 


KSS 


i^\. 


.^r.% 


°S° 


"""-■ 


.;r^ 


SiU 




HHsSpE^;.. 




^-^ 


l^-— -^^ 








,_„._ 


j 


1 

1 

1 


•■ 












vi 


^^ ■ 




■ 













IBM TRACK FORMAT 



1-110 



Floppy Disk Controller Devices 



ELECTRICAL CHARACTERISTICS 

Absolute Maximum Ratings 

Voltage to any input with 

respect to ^88= +7 to -0.5V 
Operating Temperature: +15°Cto +50°C(NPO 

Capacitor, Pin 26) 

+ 5°C to +60°C (minimum, Neg. 3500 TC 

capacitor, Pin 26) 

0°C to +70°C (minimum, Neg. 3500 TC capacitor. 

Pin 26 and a thermistor in pump circuit) 

Storage temperature = -55°C to +125°C 



NOTE: Maximum limits indicate where permanent 
device damage occurs. Continuous operation at these 
limits Is not intended and should be limited to those 
conditions specified in the DC Operating 
characteristics. 



O 
to 

CO 

X 

■ 

o 
ro 



OPERATING CHARACTERISTICS (DC) 

Ta = See Electrical Characteristics 



SYMBOL 


CHARACTERISTIC 


MIN. 


TYP. 


MAX. 


UNITS 


CONDITIONS 


l|L 


Input Leakage 






10 


pA 


V|N = ^CC 


loL 


Output Leakage 






10 


hA 


^OUT = ^CC 


V|H 


Input High Voltage 


2.0 






V 




V,L 


Input Low Voltage 






0.8 


V 




VoH 


Output High Voltage 


2.4 






V 


'0 = -IOOmA 


Vol 


Output Low Voltage 






0.45 


V 


'0 = 1.6mA 


Vqhp 


Output High PUMP 


2.2 






V 


'OP = -1.0 mA 


VOLP 


Output Low PUMP 






0.2 


V 


'OP = +1.0 mA 


Pd 


Power Dissipation 






.75 


w 


All Outputs Open 


Rpu 


Internal Pull-Up* 


100 




1700 


mA 


V|N = OV 


■cc 


Supply Current 




70 


150 


mA 


All Outputs Open 



*lnternal Pull-up resistors on PINS 1, 17, 19, 22, 36, 37 and 40. Also pin 25 on WD2791 and 3. 

TIMING CHARACTERISTICS 

Ta See Electrical Characteristics Vgs = OV,Vcc = + 5 ± .25V 

READ ENABLE TIMING (See Note 2.) 



SYMBOL 


CHARACTERISTIC 


MIN. 


TYP. 


MAX. 


UNITS 


CONDITIONS 


TsET 


Setup ADDR & 08 to RE 


50 






nsec 


See Note 3 


Thld 


Hold ADDR & OS from RE 


10 






nsec 




Tre 


RE Pulse Width 


200 






nsec 


Cl= 50 pf 


"'"drr 


DRQ Reset from RE 




100 


200 


nsec 




TlRR 


INTRO Reset from RE 




500 


3000 


nsec 


See Fig. 3 


Tdacc 


Data Valid from RE 




100 


200 


nsec 


Cl= 50 pf 


Tdoh 


Data Hold From RE 


20 




150 


nsec 


Cl= 50 pf 



WRITE ENABLE TIMING (See Note 2) 



SYMBOL 


CHARACTERISTIC 


MIN. 


TYP. 


MAX. 


UNITS 


CONDITIONS 


TsET 


Setup ADDRS & OS TO WE 


50 






nsec 


See Note 3 


^HLD 


Hold ADDR & OS from WE 


10 






nsec 




TwE 


WE Pulse Width 


200 






nsec 




Tdrr 


DRQ Reset from WE 




100 


200 


nsec 




TlRR 


INTRO Reset from WE 




500 


3000 


nsec 


See Fig. 4 


Tds 


Data SetuD to WE 


150 






nsec 




Tdh 


Data Hold from WE 


50 






nsec 





Floppy Disk Controller Devices 



1-111 





J 


[-•— 'drr 


. 16- OH 32' oS •» 






1 






D„ f < 




—mJ 'SERVICE 


^ 




..0 














^SET 




-^ 


^OACC \-m- 






OATA 1 




vA .u 1 




_» 


fDOH-«- 



p, 



t SERVICE (WORST CASE) 



DRO RISING EDGE. INDICATES THAT THE DATA REGISTER HAS ASSEMBLED 

DATA 

DRO FALLING EDGE INDICATES THAT THE DATA REGISTER WAS READ 

INTRQ RISING EDGE OCCURS AT END OF COMMAND 

INTRO FALLING EDGE INDICATES THAT THE STATUS REGISTER WAS READ. 



J" 



iNlno ^ 



o 



K' 



Jvoi 



- f— 



DATA MUST I 
BEVM.IO r 



— 1 



-^'Oh|— - 



I SERVICE (WORST CASEI 



REGISTER USER CANNOT HEAD THIS REGISTER UNTIL 
AT LEAST 4 ySEC IN MFM AFTER THE RISMQ EDGE Of WE 

WHEN wRrrno into the co«imano register status 

IS NOT VALIO until SOME 2« tiSEC IN FM. 14 jiSEC M MFM 
LATER THESE TIMES ARE DOUBLED WHEN CLK - 1 MHI 
TIME DOUBLES WHEN CLOCK • tMHl 



DRO RISING EOOt INIXCATeS THAT THE DATA REOISTER IS EMPTY 
DRO FALLING EDGE: INDICATES THAT THE DATA REGISTER IS LOADED 
INTRO RISING EDGE: INDICATE THE END OF A COMMAND 
INTRQ FALLING EDGE: INDICATES THAT THE COMMAND REGISTER 
IS WRITTEN TO 



FIGURE 3. READ ENABLE TIMING 



FIGURE 4. WRITE ENABLE TIMING 



INPUT DATA TIMING 



SYMBOL 


CHARACTERISTIC 


MIN. 


TYP. 


MAX. 


UNITS 


CONDITIONS 


Tpw 
Tbc 


Raw Read Pulse Width 
Raw Read Cycle Time 


100 
1500 


200 
2000 




nsec 
nsec 





WRITE DATA TIMING: (ALL TIMES DOUBLE WHEN CLK = 1 MHzKNO WRITE PRECOMPENSATION) 



SYMBOL 


CHARACTERISTIC 


MIN. 


TYP. 


MAX. 


UNITS 


CONDITIONS 


Twp 


Write Data Pulse Width 


400 


500 


600 


nsec 


FM 


TwG 


Write Gate to Write Data 


200 


250 
2 


300 


nsec 
fisec 


MFM 
FM 


TwF 


Write Gate off from WD 




1 
2 
1 




jAsec 
fisec 
lAsec 


MFM 

FM 

MFM 



1-112 



Floppy Disk Controller Devices 



MISCELLANEOUS TIMING: 



SYMBOL 


CHARACTERISTIC 


MIN. 


TYP. 


MAX. 


UNITS 


CONDITIONS 


TcDi 


Clock Duty (low) 


230 


250 


20000 


nsec 




TcD2 


Clock Duty (high) 


230 


250 


20000 


nsec 




"•"STP 


Step Pulse Output 


2 or 4 






fisec 


See Notes 1 & 2 


"•"dir 


Dir Setup to Step 




12 




/isec 


± CLK ERROR 


Tmr 


Master Reset Pulse Width 


50 






/.isec 




Tip 


Index Pulse Width 


10 






lisec 


See Notes 1 & 2 


RPW 


Read Window Pulse Width 










Input 0-5V 






120 




700 


nsec 


MFM 






240 




1400 


nsec 


FM±15% 




Precomp. Adjust 


100 




300 


nsec 


MFM 


WPW 


Write Data Pulse Width 










Precomp = 100 nsec 






200 


300 


400 


nsec 


MFM 


WPW 


Write Data Pulse Width 










Precomp = 300 nsec 






600 


900 


1200 


nsec 


MFM 


VCO 


Free Run Voltage Controlled 


6.0 






MHz 


Cext = 




Oscillator. Adjustable by 




4.0 




MHz 


Cext = 35 pf 




ext. capacitor on Pin 26 














Pump Up +25% 


5.0 






MHz 


PU = 2.2V 
Cext =: 35 pf 


VCO 


Pump Down -25% 






3.0 


MHz 


PD = 0.2V 
Cext = 35 pf 




5% Change Vqc 


3.8 




4.2 


MHz 


Cext = 35 pf 


VCO 


Ta = 75°C 


3.5 






MHz 


Cext = 35 pf 


Cext 


Adjustable external capacitor 


6 


25 


60 


pf 


VCO = 4.0 MHz 
nom 


RCLK 


Derived read clock 
= VCO + 8, 16, 32 




500 




KHz 


VCO = 4.0 MHz 


DDEN = 














5/8 = 1 








250 




KHz 


DDEN = 
5/8 = 








250 




KHz 


DDEN = 1 
5/8 = 1 








125 




KHz 


DDEN = 1 














5/8 = 


PU/DON 


PU/PD time on 






250 


ns 


MFM 




(pulse width) 






500 


ns 


FM 



o 

ro 

CO 

X 

■ 

o 



Floppy Disk Controller Devices 



1-113 



h-'- — I 



1^ .-H 



h'"H 




_^ 



n 



(— 'Din— ]'sTf|— — — j'STp[-^ |-»'DIH-»^'STpj.«- 

ri_n^, ri. 



-ih 



NOTES: 

1. Times double when clock = 1 MHz. 

2. Output timing readings are at Vql = 0.8v and Vqh 
= 2.0V. 

3. TsEj may be reduced to nsec if Tre and Twe are 
increased the same amount. 



MISCELLANEOUS TIMING 
'FROM STEP RATE TABLE 



-H h*-Twp 

wn 


— ^ H* — TwG — ►! 


h*— TWF 


WG 




WRITE DATA TIMING 


\-* Tbc >j 


READ 

DATA 1 





READ DATA TIMING 







Table 4. STATUS REGISTER SUMMARY 








ALL TYPE 1 


READ 


READ 


READ 


WRITE 


WRITE 


BIT 


COMMANDS 


ADDRESS 


SECTOR 


TRACK 


SECTOR 


TRACK 


S7 


NOT READY 


NOT READY 


NOT READY 


NOT READY 


NOT READY 


NOT READY 


S6 


WRITE 
PROTECT 











WRITE 
PROTECT 


WRITE 
PROTECT 


S5 


HEAD LOADED 





RECORD TYPE 











S4 


SEEK ERROR 


RNF 


RNF 





RNF 





S3 


ORG ERROR 


CRC ERROR 


CRC ERROR 





CRC ERROR 





82 


TRACK 


LOST DATA 


LOST DATA 


LOST DATA 


LOST DATA 


LOST DATA 


S1 


INDEX PULSE 


DRQ 


DRQ 


DRQ 


DRQ 


DRQ 


SO 


BUSY 


BUSY 


BUSY 


BUSY 


BUSY 


BUSY 



STATUS FOR TYPE I COMMANDS 



BIT NAME 


MEANING 


S7 NOT READY 


This bit when set indicates the drive is not ready. When reset, it indicates that the 
drive is ready. This bit is an inverted copy of the Ready input and logically "ORed" 
with IV1R. 


S6 PROTECTED 


When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT 
input. 


S5 HEAD LOADED 


When set, it indicates the head is loaded and engaged. This bit is a logical "and" of 
HLD and HLT signals. 


S4 SEEK ERROR 


When set, the desired track was not verified. This bit is reset to when updated. 


S3 CRC ERROR 


CRC encountered in ID field. 


S2 TRACK 00 


When set, indicates Read/Write head is positioned to Track 0. This bit is an inverted 
copy of the TROO input. 


S1 INDEX 


When, set, indicates index mark detected from drive. This bit is an inverted copy of 
the IP input. 


SO BUSY 


When set command is in progress. When reset no command is in progress. 



1-114 



Floppy Disk Controller Devices 



STATUS FOR TYPE II AND ill COMMANDS 



BIT NAME 


MEANING 


S7 NOT READY 


This bit wlien set indicates the drive is not ready. When reset, it indicates that the 
drive is ready. This bit is an inverted copy of the Ready input and "ORed" with MR. 
The Type II and III Connmands will not execute unless the drive is ready. 


S6 WRITE 
PROTECT 


On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a 
Write Protect. This bit is reset when updated. 


S5 RECORD TYPE 


On Read Record: It indicates the record-type code from data field address marl<. 1 = 
Deleted Data Mark. = Data Mark. On any Write: Forced to a zero. 


S4 RECORD NOT 
FOUND (RNF) 


When set, it indicates that the desired track, sector, or side were not found. This bit is 
reset when updated. 


S3 CRC ERROR 


If S4 is set, an error is found in one or more ID fields; otherwise it indicates error in data 
field. This bit is reset when updated. 


S2 LOST DATA 


When set, it indicates the computer did not respond to DRQ in one byte time. This bit is 
reset to zero when updated. 


S1 DATA REQUEST 


This bit is a copy of the DRQ output. When set, it indicates the DR is full on a Read 
Operation or the DR is empty on a Write operation. This bit is reset to zero when 
updated. 


SO BUSY 


When set, command is under execution. When reset, no command is under execution. 



SUMMARY OF ADJUSTMENT PROCEDURE 



WRITE PRECOMPENSATION 








1) 
2) 
3) 
4) 
5) 
6) 


Set TEST (Pin 22) to a logic high. 

Strobe MR (Pin 19). 

Set TEST (Pin 22) to a logic low. 

Observe pulse width on WD (Pin 31). 

Adjust WPW (Pin 33) for desired pulse width (Precomp Value). 

Set TEST (Pin 22) to a logic high. 








DATA SEPARATOR 








1) 
2) 
3) 
4) 
5) 
6) 
7) 

8) 


Set TEST (Pin 22) to a logic high. 

Strobe MR (Pin 19). Insure that 5 /8, and DDEN are set properly. 

Set TEST (Pin 22) to a logic low. 

Observe Pulse Width on TG43 (Pin 29). 

Adjust RPW (Pin 18) for (205ns for 8" DD 450ns for 5 1/4" DD, etc.). 

Observe Frequency on DIRC (Pin 16). 

Adjust variable capacitor on VCO pin for Data Rate (500 KHz for 8" 

etc.). 

Set TEST (Pin 22) to a logic high. 


DD, 


250 


KHz for 5 1/4" DD, 


NOTE: To maintain internal VCO operation, insure that TEST = 1 whenever a master reset pulse is applied.] 



Floppy Disk Controller Devices 



1-115 



1-116 Floppy Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD279X-02 Floppy Disk Formatter/Controller 
Family Application Notes 



INTRODUCTION 

In an effort to simplify Floppy Diskette interfacing, 
Western Digital has been constantly improving the 
LSI Controller/Formatter, the most recent of which is 
the WD279X Family of LSI controller devices, incor- 
porating advanced technology to include controller, 
Write Compensation and Analog Phase Lock Loop 
in a single 40-pin dual-in-line package. With this 
package we can now offer the designer the simplest 
ever interfacing option. 

The family consists of four members: WD2791, 
WD2793, WD2795 and WD2797. WD2791 and WD2793 
offer internal clock divide in true and inverted data 
bus. The WD2795 and WD2797 offer internal side 
select. The family supports both 5 1/4" and 8" Diskette 
Drives and both single and double density. 

HOST INTERFACING 

The LSI Diskette Controller has been developed to 
ease the interfacing of Processor to Disk Device. The 
Host interfacing with WD279X Family is 
accomplished with minimum external devices via an 
8-bit bi-directional bus, read/write controls, register 
select lines and optional control line for chip select, 
5 1/4" or 8" select, enable mini floppy, double den- 
sity enable. The basic operation at the controller is 
accomplished by selecting the device via (CS) chip 
select line, enabling selection of one of the five inter- 
nal registers (Figure 1). 



A1 - AO 


READ (RE) 


WRITE (WE) 




1 

1 

1 1 


Status Regiser 
Track Register 
Sector Register 
Data Register 


Command Register 
Track Register 
Sector Register 
Data Register 



FIGURE 1. 

Each time a command is issued to the WD279X, the 
busy bit is set and INTRQ (Interrupt Request) line is 
reset. The user has the option of testing for the busy 
bit or polling INTRQ to determine if command has 
been completed. 

The busy bit will be reset whenever the WD279X is 
idle and awaiting a new command. The INTRQ line 
once set, can only be reset by reading of the status 
register or issuing a new command. 

The Aq, Ai Lines used for register selections can be 
configured at the CPU in a variety of ways. These lines 
may actually tie to CPU addressed like RAM. They 



may also be used under Program Control by tying to 
a port device such as the 8255, 6250, etc. As a 
diagnostic tool when checking out the CPU interface, 
the Track and Sector registers should respond like 
"RAM" when the WD279X is idle (Busy = INTRQ = 0). 

Because of internal synchronization cycles, certain 
time delays must be introduced when operating under 
Programmed I/O. The worst case delays are: 



OPERATION 


NEXT 
OPERATION 


DELAY 
FM 


REQ'D. 
MFM 


Write to 
Command Reg. 


Read Busy Bit 
(Status Bit 0) 


12^3 


6ms 


Write to 
Command Reg. 


Read Status 
Bits 1-7 


28ps 


14hs 


Write Any 
Register 


Read From Diff. 
Register 









Other CPU interface lines are CLK, MR and DDEN. 
The CLK line should be 2 MHz (8" drive) or 1 MHz (5 
1/4" drive) with 50% duty cycle. Accuracy should be 
+ 1% (crystal source) since all internal timing, 
including stepping rates, are based upon this clock, 
or a sin gle 2 MHz CLK on WD2791 and WD2793 since 
ENMF line will internally divide CLK. 

The Master Reset Line should be strobed a minimum 
of 50 microseconds upon each power-on condition. 
This line clears and initializes all internal registers and 
issues a restore command (Hex '03') on the rising 
edge. A quicker stepping rate can be written to the 
command register after a MR, in which case the 
remaining steps will occur at the faster programmed 
rate. The WD179X will issue a maximum of 255 step- 
ping pulses in an attempt to expect the TROO line 
to go active low. This line should be con- 
nected to the drive's TROO sensor. 



The DDEN line causes selection of either single den- 
sity (DDEN = 1) or double density operation. DDEN 
should not be switched during a read or write 
operation. 

The 5/8 Line selects internal VCO frequency to be 
used with 5 1/4" or 8" drives. 

FLOPPY DISK INTERFACE 

The Floppy Disk Interface can be divided into three 
sections: Motor Control, Write Signals and Read 
Signals. All of these lines are capable of driving one 
TTL load and not compatible for direct connection 



ro 

(O 



o 
ro 



Floppy Disk Controller Devices 



1-117 



D 

O 



to the drive. Most drives require an open-collector TTL 
interface with high current drive capability. This must 
be done on all outputs rom the WD279X. Inputs to 
the WD279X may be buffered or tied to the Drives' 
outputs, providing the appropriate resistor termina- 
tion networks are used. Undershoot should not 
exceed -0.3 volts, while integrity of V|h and Vqh 
levels should be kept within spec. 

MOTOR CONTROL 

Motor (Control is accomplished by the STEP and DIRC 
Lines. The STEP Line issues stepping pulses with 
period defined by the rate field in all Type I com- 
mands. The DIRC Line defines the direction of steps 
(DIRC = 1 STEP IN/DIRC = STEP OUT). 

Other Control Lines include the IP or Index Pulse. 
This Line is tied to the drives' Index LED. sensor that 
informs the WD279X that the stepper motor Is at is 
furthest position, over Track 00. The READY Line can 
be used for a number of functions, such as sensing 
"door open," Drive motor on, etc. Most drives provide 
a programmable READY Signal selected by option 
jumpers on the drive. The WD279X will look at the 
ready signal prior to executing READA/VRITE com- 
mands. READY is not inspected during any Type 1 
commands. All Type 1 commands will execute 
regardless of the Logic Level on this Line. 

GENERAL DISK WRITE OPERATION 

When writing is to take place on the diskette the Write 
Gate (WG) output is activated, allowing current to flow 
into the ReadA/Vrite head. As a precaution to 
erroneous writing the first data byte must be loaded 
into the Data Register in response to a Data Request 
from the WD279X before the Write Gate signal can 
be activated. 



Writing is inhibited when the Write Protect input is 
a logic low, in which case any Write command is 
im mediately termi nated, an interrupt is generated and 
the Write Protect status bit is set. 

RESTORE (SEEK TRACK 0) 



Upon receipt of this command the Track 00 (TROO) 
input is sampled. If TROO is active low indicating the 
Read-Write head is positioned over track 0, the Track 
Register is loaded with zeroes and an interrupt is 
generated. If TROO is not active low, stepping pulses 
(pins 15 to 16) at a rate specified by the r^ ro field are 
issued until the TROO input is activated. At this time 
the Track Register is loaded with zeroes and an inter- 
rupt is generated. If the TROO input does not go active 
low after 255 stepping pulses, the WD279X terminates 
operations, interrupts, and sets the Seek error status 
bit. A verification operation also takes place if the V 
flag is set. The h bit allows the head to be loaded 
at the start of command. Note that the Restore com- 
mand is executed when MR goes from an active to 
an inactive state. 



SEEK 

This command assumes that the Track Register con- 
tains the track number of the current position of the 
Read/Write head and the Data Register contains the 
desired track number. The WD279X will update the 
Track register and issue stepping pulses in the 
appropriate direction until the contents of the Track 
register are equal to the contents of the Data Register 
(the desired track location). A verification operation 
takes place if the V flag is on. The h bit allows the 
head to be loaded at the start of the command. An 
interrupt is generated at the completion of the com- 
mand. Note: When using multiple drives, the track 
register must be updated for the drive selected before 
seeks are issued. 

STEP 

Upon receipt of this command, the WD279X issues 
one stepping pulse to the disk drive. The stepping 
motor direction is the same as in the previous step 
command. After a delay determined by the r^ro field, 
a verification takes place if the V flag is on. If the T 
flag is on, the Track Register is updated. The h bit 
allows the head to be loaded at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. 

STEP-IN 

Upon receipt of this command, the WD279X issues 
one stepping pulse in the direction away from track 
0. If the T flag is on, the Track Register is decremented 
by one. After a delay determined by the r-i Tq field, a 
verification takes place if the V flag is on. The h bit 
allows the head to be loaded at the start of the com- 
mand. An interrupt is generated at the completion of 
the command. 

EXCEPTIONS 

On the WD2795/7 devices, the SSO output is not 
affected during Type I commands, and an internal 
side compare does not take place when the (V) Verify 
Flag is on. 

For write operations, the WD279X provides Write Gate 
(Pin 30) and Write Data (Pin 31) outputs. Write data 
consists of a series of pulses set to a width approx- 
imately three times greater than the precomp adjust- 
ment. Write Data provides the unique address marks 
in both formats. 

READY 

Whenever a Read or Write command (Type II or III) 
is received the WD279X samples the Ready input. If 
this input is logic low the command is not executed 
and an interrupt is generated. All Type I commands 
are performed regardless of the state of the Ready 
input. Also, whenever a Type II or III command is 
received, the TG43 signal output is updated. TG43 
may be tied to ENP to enable write precompensation 
on tracks 44-76. 



1-118 



Floppy Disk Controller Devices 



COMMAND DESCRIPTION 

The WD279X will accept eleven commands. Com- 
mand words should only be loaded in the Command 
Register when the Busy status bit is off (Status bit 
0). The one exception is the Force Interrupt command. 
Whenever a command is being executed, the Busy 
status bit is set. When a command is completed, and 



interrupt is generated and the Busy status bit is reset. 
The Status Register indicates whether the completed 
command encountered an error or was fault free. For 
ease of discussion, commands are divided into four 
types. Commands and types are summarized in Table 
1 and Table 2. 



a 

lO 
■>! 

o 
to 



TABLE 1. COMMAND SUMMARY 

A. Commands for Models: 2791, 2793 



B. Commands for Models: 2795, 2797 









Bits 


















Bits 






Type Command 


7 


6 


5 


4 


3 


2 







7 


6 


5 


4 3 


2 


1 


1 Restore 














h 


V 




^0 











h 


V 


M ^0 


1 Seek 











1 


h 


V 




^0 











1 h 


V 


^1 ^0 


1 Step 








1 


T 


h 


V 




^0 








1 


T h 


V 


'^ '0 


1 Step-in 





1 





T 


h 


V 




^0 





1 





T h 


V 


M ^0 


1 Step-out 





1 


1 


T 


h 


V 




^0 





1 


1 


T h 


V 


^1 ^0 


II Read Sector 










m 


S 


E 


C 













m L 


E 


U 


II Write Sector 







1 


m 


S 


E 


C 


^0 







1 


m L 


E 


U ^0 


III Read Address 




1 











E 










1 








E 


U 


III Read Track 




1 


1 








E 










1 


1 





E 


U 


III Write Track 




1 


1 


1 





E 










1 


1 


1 


E 


U 


IV Force Interrupt 




1 





'1 


'3 


'2 


'1 


'0 




1 





1 '3 


'2 


'1 '0 



Floppy Disk Controller Devices 



1-119 



TABLE 2. FLAG SUMMARY 



D 
lO 

(O 

o 



Command 
Type 


Bit 
No(s) 




Description 




0,1 


M ^0 = Stepping Motor Rate 
See Table 3 for Rate Summary 




II 


2 
3 
4 



V = Track Number Verify Flag 
h = Head Load Flag 
T = Track Update Flag 
^0 = Data Address Mark 


V = 0,No verify 

V = 1, Verify on destination track 
h = 0,Load head at beginning 

h = 2,Unload head at beginning 

T = 0,No update 

T = 1, Update track register 

^0 = 0,FB(DAM) 

^0 = 1,F8(deleted DAM) 


II &III 


1 


C = Side Compare Flag 


C = O.Disable side compare 
C = 1, Enable side compare 


II & III 


1 


U = Update SSO 


U = 0,Update SSO to 
U = 1, Update SSO to 1 


II & III 


2 


E = 15 MS Delay 


E = 0,No 15 MS delay 

E = 1,15 MS delay (30 MS for 1 MHz) 


II 


3 


S = Side Compare Flag 


S = O.Compare for side 
S = 1, Compare for side 1 


II 
II 


3 
4 


L = Sector Length Flag 




LSB's Sector Length in ID Field 

00 01 10 11 


L = 256 512 1024 128 


L = 1 128 256 512 1024 


m = Multiple Record Flag 


m = 0,Single record 
m = 1, Multiple records 


IV 


0-3 


'x = Interrupt Condition Flags 

'0 = 1 Not Ready To Ready Transition 

h = 1 Ready To Not Ready Transition 

'2 = 1 Index Pulse 

'3 = 1 Immediate Interrupt, Requires A Reset* 

'3-'0 = Terminate With No Interrupt (INTRQ) 



"NOTE: See Type IV Command Description for further Information. 



1-120 



Floppy Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD1691 Floppy Support Logic (F.S.L) 



o 

O) 



FEATURES 



DIRECT INTERFACE TO THE FD179X 

ELIMINATES EXTERNAL FDC LOGIC 

DATA SEPARATION / RCLK GENERATION 

WRITE PRECOMPENSATION SIGNALS 

VFOE/WF DEMULTIPLEXING 

PROGRAMMABLE DENSITY 

8" OR 5.25" DRIVE COMPATIBLE 

ALL INPUTS AND OUTPUTS TTL COMPATIBLE 

SINGLE + 5V SUPPLY 



GENERAL DESCRIPTION 

The WD1691 F.S.L. has been designed to minimize 
the external logic required to interface the 179X 
Family of Floppy Disl< Controllers to a drive. With the 
use of an external VCO, the WD1691 will generate the 
RCLK signal for the WD179X, while providing an 
adjustmen t pulse (P UMP) to control the VCO 
frequency. VFOE/WF de-multiplexing is also 
accomplished and Write Precompensation signals 
have been included to interface directly with the 
WD2143 Clock Generator. 

The WD1691 is implemented in N-MOS silicon gate 
technology and Is available In a plastic or ceramic 
20 pin dual-In-line package. 



WDIN 1 


V 

•1 


PC 


2 


PC 


3 


fC 


4 


stb| 


5 

Wl 


v\^dout| 


6 


WGJ 


7 


VFOE/WF 1 


8 


TG43C 


9 


vssC 


10 



■\y 



Z]vcc 

I LATE 
I EARLY 
I VCO 

HJdden 

Z]pu 
IUrclk 

ZIrdd 



VF06 

/WF 



WQ 

EARLY 
LATE 



Figure 1. WD1691 PIN DESIGNATION 




vFoe 

DEMUX 



PRECOMP 
LCX3IC 

E 
L 
N 



LATCH 
DECODE 



■^ PU 
♦• PO 



TQ43 
■IfA 



— WDIN 
•^ WDOUT 

■^ STB 



Figure 2. WD1691 BLOCK DIAGRAM 



Floppy Disk Support Devices 



2-1 



o 

O) 
CO 



PIN 


NAME 


SYMBOL 


FUNCTION 


1 


WRITE DATA 
INPUT 


WDIN 


Ties directly to the FD179X WD pin. 


2, 3, 4, 19 


PHASE 


02 03 01 04 


4 Phase inputs to generate a desired Write Precompen- 




2, 3, 1, 4 




sation delay. These signals tie directly to the WD2143 
Clock Generator. 


5 


STROBE 


STB 


Strobe output from the 1691. Strobe will latch at a high 
level on the leading edge of WDIN and reset to a low 
level on the leading edge of 04. 


6 


WRITE DATA 


WDOUT 


Serial, pre-compensated Write data stream to be sent 




OUTPUT 




to the disk drive's WD line. 


7 
8 


WRITE GATE 
VFO ENABLE/ 


WG 


Ties directly to the FD179X pin. 

Ties directly to the FD179X VFOE/WF pin. 


VFOE/WF 




WRITE FAULT 






9 


TRACK 32 


TG43 


Ties directly to the FD179X TG43 pin. If Write 
Precompensation is required on TRACKS 44-76. 


10 


Vss 


Vss 


Ground 


11 


READ DATA 


RDD 


Composite clock and data stream input from the drive. 


12 


READ CLOCK 


RCLK 


RCLK signal generated by the WD1691, to be tied to 
the FD179X RCLK pin. 


13 


PUMP UP 


PU 


Tri-state output that will be forced high when the 
WD1691 requires an increase in VCO frequency. 


14 


PUMP DOWN 


PD 


Tri-state output that will be forced low when the 


15 


Double Density 




WD1691 required a decrease in VCO frequency. 
Double Density Select input. When Inactive (High), the 


DDEN 




Enable 




VCO frequency is internally divided by two. 


16 


Voltage 


VCO 


A nominal 4.0 MHz (8" drive) or 2.0 MHz (5.25" drive) 




Controlled 




master clock input. 




Oscillator 






17, 18 


EARLY 


EARLY 


EARLY and LATE signals from the FD179X, used to 




LATE 


LATE 


determine Write Precompensation. 


20 


Vcc 


Vcc 


+ 5V ± 10% power supply 



Table 1. PIN DEFINITIONS 



2-2 



Floppy Disk Support Devices 




The signals, DDEN, TG43, and RDD have internal 
pull-up resistors and may be left open if a logic 1 is 
desired on any of these lines. 



Figure 3 PUMP SIGNAL TIMING DIAGRAM 

DEVICE DESCRIPTION 

The WD1691 is divided into two sections: 

1. Data Recovery Circuit 

2. Write Precompensation Circuit 

The Da ta Sep arator or R ecov ery Circuit has four 
inputs: DDEN, VCO^JIDD, and VFOE/ WF; an d 
three outputs: PU, PD, and RCLK. The VFOE/WF 
input is used in conjunction with the Write Gate signal 
to enable the Data recovery circuit. When Write Gate 
is high, a write operation is taking place, and the data 
recovery circuits are disabled, regardless of the state 
on any other inputs. 

The Write Precompensation circuit has been designed 
to be used with the WD2143-03 clock generator. When 
the WD1691 is operated in a "single density only" 
mode, write precompensation as well_ _as__the 
WD21 43-03 is not needed. In this case, 1,02,03,04, 
and STB should be tied together, DDEN left open, 
and TG43, WDIN, Early, and Late tied to ground. 

In the double-density mode (DDEN =0), the signals 
Early_and Late are used to select a phase input 
(01 - 04) on the leading edge of WDIN. The STB line is 
latched high when this occurs, cau_s|ng the 
WD2143-03 to start its pulse generation. 02 is used 
as the write data pulse on_nominal (Early = Late = 0) 
01 is used for early, and 03 is used for late. The 
leading edge of 04 resets the STB line in anticipation 
of the next write data pulse. When TG43 = or 
DDEN = 1, Precompensation is disabled and any tran- 
sitions on the WDIN line will appear on the WDout 
line. If write precompensation is desired on all tracks, 
leave TG 43 ope n (an internal pull-up will force a Logic 
1) while DDEN=0. 



WG 


VFOE/WF 


RDD 


PU + PD 


1 


X 


X 


Hl-Z 





1 


X 


Hl-Z 








1 


Hl-Z 











Enable 



Figure 4 DATA RECOVERY LOGIC 



When VFOE/WF and WRITE GATE are low, the 
data recovery circuit is enabled. When the RDD 
line goes Active Low, the PU or PD sig nals will be- 
come active. See Figure 4. If the RDD line has 
made its transition in the beginning of the RCLK win- 
dow, PU will go from a Hl-Z state to a Logic 1, 
reque sting an increase in VCO frequency. If the 
RDD line has made its transition at the end of tjie 
RCLK window, PU will remain in a Hl-Z state while PD 
will go to a logic zero, requesting a dec rease in VCO 
frequency. When the leading edge of RDD occurs 
in the center of the RCLK window, both PU and PD 
will remain tri-stated, indicating that no adjustment 
of the VCO frequency is need ed. See Figure 3. The 
RCLK sign al is a divide-bv-16 (DDEN = 1) or a 
divide-by-8 (DDEN =0) of the VCO frequency. 

The minimum Voh level on PU is specified at 2.4V, 
sourcing 200ua. During PUMP UP time, this output 
will gojrom a tri-state to .4V minimum. By typing PU 
and PD together, a PUMP signal is created that will 
be forced low for a decrease in VCO frequency and 
forced high for an increase in VCO frequency. To 
speed up rise times and stabilize the output voltage, 
a resistor divider can be used to set the tri-state level 
to approximately 1.4V. This yields a worst case swing 
of + IV; acceptable for most VCO chips with a linear 
voltage-to-frequency characteristic. 

Both PU and PD si gnals are affected by the width 
of the RAW READ (RDD) pulse. Thewider the RAW 
READ pulse, the longer the PU or PD signal (de- 
pending upon the phase relationship to RCLK) will 
remain active. If t he RAW READ pulse exceeds 250ns, 
(VCO = 4 M Hz. DDEN = 0), or 500 nsJVCO = 2 
MHz, DDEN =1), then both a PU and PD will oc- 
cur in the same window. This is undesirable and 
reduces the accuracy of the external integrator or low- 
pass filter to convert the PUMP signals into a slow 
moving D.C. correction voltage. 

Eventually, the PUMP signals will have corrected the 
VCO input to exactly the same frequency multiple as 
the RAW READ signal. The leading edge of the RAW 
READ pulse will then occur in the exact center of the 
RCLK window, an ideal condition for the FD179X 
internal recovery circuits. 



O 



Floppy Disk Support Devices 



2-3 



o 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature 

under Bias -25°C (-13°F) to 70°C (158°F) 

Voltage on any pin with respect \ 

to Ground (Vgs) -0.2 to + 7V 

Power Dissipation 1W 



Storage Temperature 

Ceramic-65°C (-85°F) to + 150°C (302°F) 
Plastic-55°C (-67°F) to +125°C (257°F) 

NOTE: Maximum iimits indicate wliere permanent 
device damage occurs. Continuous operation at tliese 
iimits is not intended and sliouid be limited to those 
conditions specified in the DC Electrical 
Characteristics. 



DC ELECTRICAL CHARACTERISTICS 

Ta = 0°C (32°F) to 70°C (158°i=); Vqc = 5.0V + 10%;Vss = OV 



SYMBOL 


PARAMETER 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


V,L 


Input Low Voltage 


-0.2 




+ 0.8 


V 




V,H 


Input High Voltage 


2.0 






V 




Vol 


Output Low Voltage 






0.45 


V 


'OL = 3.2 MA 


VoH 


High Level Output Voltage 


2.4 






V 


'OH = -200h a 


Vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




'go 


Supply Current 




40 


100 


MA 


All outputs open 



NOTE: For AC and functional testing purposes, a Logic 'O' is measured at 0.8V, and a Logic '1' at 2.0V. 

AC ELECTRICAL CHARACTERISTICS 

■^A = 0°C (32°F) to 70°C (158°F);Vcc = 5V + 10%; Vgs = OV 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNITS 


TEST CONDITIONS 


FIN 


VCO Input Frequency 


.5 


4 


6 


MHz 


DDEN = 






.5 


2 


6 


MHz 


DDEN = 1 


"pw 


RDD Pulse Width 


100 


200 




ns. 




We, 


EARLY (LATE) to WDIN 


100 






ns. 




Wpi 


PUMP UP/DN Time 
WDIN to WDOUT 







250 
80 


ns. 
ns. 




DDEN = 1 


Inr 


Internal Pull-up Resistor 


4.0 


6.5 


10 K 










1 
U— FIN -M 

1 




r 




1 






































RCLK 




— »• 


1 
1 


♦- Rpw 


















> i# — 




^ 













Figure 5. INTERNAL PULL-UP RESISTOR Figure 6. RDD AND RCLK PULSE DIAGRAMS 



2-4 



Floppy Disk Support Devices 





WDIN _ 


Wei -^ 


1 1— - 

1 
1 


♦• M WpW 


r- 




EARLY _ 
LATE 














L 
















/^ 


^^^ 






STB 


(^ 


/ u 


/U 


/^ 


1 p 




/ 


^ 


L 


1 


\ 


i 


- \ 

LATE 


-\~ 




WDOUT 


NOM 


EARLY 


NOM 


TG43 = 
DDEN = 


= "1" 
= "0" 











a 

(O 



Figure 7. WRITE DATA TIMING (MFM) 



\A/niM . . 




« — Wpw 






WDOUT 


1 
1 


n 


TG43 = "0" 
DDEN = "1" 


H 


'.•^ Wpi 



Figure 8. WRITE DATA TIMING (FM) 



Floppy Disk Support Devices 



2-5 



o 

(O 



RAW 
DATA 



o- 



1691 



RDD 
RCLK 



DDEN 
EARLY LATE-VFSE 



17 18 8 



15 



N.C. 







25 


1771-01 






74LS08 


— 


27 




^— 


FDDATA 


J 




26 


74LS04 




' V- 


FDCLOCK 


J 











Figure 9. WD1691 to FD1771-01 INTERFACE 



TYPICAL APPLICATIONS 

Figure 9 illustrates the WD1691 to FD1771-01 floppy 
disk controller. The RCLK signal is used to gate the 
RAW data pulses which are inverted by the 74LS04 
inverter. Since RLCK will be high during data and low 
during clock a 74LS08 is used to switch the proper 
clock or data pulse to the FD1771. 

Shown in Figure 10 is a Phase-Lock Loop data 
separator and the support logic for a single and 
double-density 8" drive. The raw data (both clock and 
data bits) are fed to the WDi691 and FD179X. The 
WD1691 outputs its PU or PD signal, which is 
integrated by the .33uf capacitor and 33ohnn resistor 
to form a control voltage for the 74S124 VCO device. 
The 4.0 MHz nominal output of the VCO then feeds 
back to the WD1691 completing the loop. The 
WD2143-03 is also used, providing write precompen- 
sation when in double-density, from tracks 44-77. The 
DDEN line can either be controlled by a toggle switch 
or a logic level from the host system. 

ALIGNMENT 

To adjust write precompensation, issue a command 
to the FD179X so that write data pulses are present. 
This can_be done with a 'WRITE TRACK' command 
and the IP line open, or a continuous 'WRITE 
SECTOR' operation. With a scope on pin 4 of the 
WD1691, adjust the precomp pot for the desired value. 
This will range from 100 to 300 ns typically. 

The pulse width set on pin 4 (01) will be the desired 
precomp delay from nominal. 

Th e data sepa rator must be adjusted with the RDD 
or VFOE/WF line at Logic 1. Adjust the bias voltage 



potentiometer for 1.4V on pin 2 of the 74S124. Then 
adjust the range control to yield 4.0 MHz on pin 7 of 
the 74S124. 

SUBSTITUTING VCO'S 

There are other VCO circuits available that may be 
substituted for the 74S124. The specifications 
required are: 

1) The VCO must free run at 4.0 MHz with a 1.4V con- 
trol signal. The WD1691 will force this voltage 1 
Volt in either direction (i.e., .4V = decrease fre- 
quency, 2.4V = increase frequency). If a + 15% 
capture range is desired, then a 1 Volt change on 
the VCO input should change the frequency by 
15%. Capture range should be limited to about 
+ 25%, to prevent the VCO from breaking into 
oscillation and/or losing lock because of noise 
spikes (causing abnormally quick adjustments of 
the VCO frequency). Jitter in the VCO output fre- 
quency may further be reduced by increasing the 
integration capacitor/resistor, but this will also 
decrease the final capture range and lock-up time. 

2) The sink output current of the WD1691 is 3.2ma 
minimum. The source output current is -200ua. 
Therefore, source current is the limiting factor. 
Insure that the input circuitry of the VCO does not 
require source current in excess of -200ua. 

Another alternative is to use a voltage follower/level 
shifter circuit to match the input requirements of the 
VCO chosen. A more complex filter can be used to 
convert the PUMP UP/PUMP DOWN pulses to the 
varying DC voltage signal required by the VCO, 
achieving an optimum condition between lock-up time 
and high frequency rejection. 



2-6 



Floppy Disk Support Devices 



200 NS ± 25 NOTE 4 



RAW DATA 
FROM DRIVE 






o 

i— 
m 

B 
O 

c 

00 

I— 
m 

o 
m 

z 



+5V 

V 



14 



+ 5V 



RANGE^ 
ADJ 



50K 



16 



R2 



CI 

C2 

F2 

74LS629 

°' FC 
SI 24 

RNG 

E 




+ 5 



20 



NOTE 3 



r.33/iF • 



33n 



47K 100K 

BIAS VOLTAGE 
ADJ 



47K 



VCC 

WDOUT 
DDEN 
RCLK 
WG 
WDIN 
EARLY 
LATE 
TG43 
VFOE 

Vss 

04 03 02 01 



VCO 
RDD 

WD1691 

PU 

PD 
STB 



19 



+ 12V 

1) ALL RESISTORS 'AW i 5% 

2) SPECIFICATIONS = 
CAPTURE RANGE: ±20% 
LOCK-UP TIME: 25^560 

(ALL ONES PATTERN, MFM) 

3) FOR 5 1/4- 8 

.ee^if ".33m» 
680 33n 

82Pf 47Pf 

4) RDD = ONE EIGHTH RCLK WIDTH MAXIMUM 
250ns for 4MHz 
500ns for 2MHz 



2K 



10K 



PRECOMPADJ 



SINGLE 
DENSITY 



1 DOUBLE 
DENSITY 



04 03 02 01 
STB IN 

WD2 143-03 
;^PW 



Vcc 
Vss 



""to <=H 



<3- 



<3 



<o- 



RAW READ 



FD179X 



VFOBWF 




DIRC 



WPRT 



TROO 
READY 



■<ii 






FROM 
DRIVE 



|.69l.aM 



2-8 Floppy Disk Support Devices 



WESTERN DIGITAL 

CORPORATION 

WD16C92 Floppy Read/Write Circuit Device 



FEATURES 

Compatible with NEC 765A Floppy Disk Controller 

CMOS 

TTL Compatible 

Single +5V Supply 

Phase Detector and Pulse shaping for Read Data 

Write Data Precompensation 

Floppy Controller Read/Write Clock Generation 

IBM PC/PC AT Bus Timing Compatible 



Vcc 



FDATA 


PLL LOGIC 

FRQ DET 
PHASE DET 
VCO SELECT 
PULSE SHAPE 


FDCLK 
FFDDATA 




VCOEN 


VCOEN 2 


OSC 2 


UP 4 


DN 4 




XTL 2 






CUOCK/REF GEN 
DATA RATE SELECT 

1 OF 4 DATA RATE 
OPT 2 SPEED DRIVE 
XTAL OSC 
FDC CLKS 




SDB 2 


24MHZ 


DRV 


FREP 


LDFCR 




MR 


FWCLK 






WDA 


WRITE PRECOMP LOGIC 


WRDATA 


WE 




PSO 


FDRO 


PS1 








PINT 


INT/DMA 

PC BUS TIMING 


FIRQ 


DRQ 




FDMAEN 


FDRQ 


DACK 









•Vss 
40 PIN DIP/44 PIN PLCC 



DESCRIPTION 

The WD16C92 is a 40-pln CMOS custom LSI device 
with full TTL level compatibility on input and output. 
It is intended to replace a number of discrete com- 
ponents needed with the NEC765A Floppy Disk Con- 
troller. The WD16C92 handles four primary functions: 

• PLL Logic 

• Clock Generation 

• Write Precompensation 

• Interrupt/DMA timing PC/PC AT Bus 

This floppy support device augments the 765A con- 
troller while it reduces overall cost. 



FWCLK 

DRV 

FDRO 

SDB1 

SDBO 



g: 



LDFCR 
0SC1 
0SC2 

FDCLK 

VC0EN1 

VC0EN2 

FREP 

FFDDATA 

VCOEN 

PSO 

PS1 

WDA 

WE 

WRDATA 

GND 



[T IN 

m IN 

d 

DI 

DI 
OE 

DI 

G? 
DI 



OUT 
OUT 
OUT 
OUT 
OUT 



\y- 



IN 
OUT 
OUT 
OUT 
OUT 
OUT 
OUT 
OUT 
OUT 
OUT 
OUT 
IN 
OUT 
(TEST POINT) OUT 



iaDVcc 


lO DRQ 


^ /DACK 


10 FDMAEN 


ID PINT 


m FIRQ 


Z]FDRQ 


"M] DNOO 


1] UPOO 


ID DN01 


"30l UP01 


;»] DN02 


Is] UP02 


ID DN03 


:^UP03 


Ig] XTL 


IT] XTL 


J3] (24MCLK) 


H] FDATA 


Jll MR 



o 

O 

CO 

to 



Floppy Disk Support Devices 



2-9 



SIGNAL DESCRIPTION 



PIN 


MNEMONIC 


DESCRIPTION 


1 


FWCLK 


WRITE CLOCK - TTL output, clock for write data. 


2 


DRV 


DRIVE TYPE - TTL input with internal pullup resistor. Low level indicates special drive. 


3 


FDRO 


SPEED SELECT - TTL output, latched image SDBO. (effective only on dual speed drives.) 


4 


SDB1 


DATA BUS BIT 1 - TTL input, of data bus bit 1. 


5 
6 

7 

8 


SDBO 


DATA BUS BIT - TTL input, of data bus bit 0. 


LDFCR 


LOAD FLOPPY CONTROL REGISTER - TTL input causes SDBO and SDB1 to be latched 
internally. 

OSCILLATOR 1 - TTL input, for 500 Kbs, 250 Kbs and 125 Kbs data rates (nominally 
2.0 MHz) 


0SC1 


0SC2 


OSCILLATOR 2 - TTL input for 300 Kbs data rate (nominally 2.4 MHz) 


9 
10 
11 


FDCLK 


READ DATA CLOCK - TTL output, provides window for floppy read data pulse. 


VC0EN1 


VCO ENABLE 1 - TTL output, enables VCO for 300 Kbs data rate. 


VC0EN2 


VCO ENABLE 2 - TTL output, enables VCO for 500, 250 and 125 Kbs data rates. 


12 


PREP 


CLOCK OUTPUT - TTL output, provides clock signal for the p*PD765A. 


13 


FFDDATA 


READ DATA - TTL output, floppy read data pulses. 


14 


VCOEN 


VCO ENABLE - TTL input, from the pPD765A when high enables reading from the floppy 
disk. 


15 


PSO 


PRECOMP BIT - TTL input, decodes for precompensation of write data. 


16 


PS1 


PRECOMP BIT 1 - TTL input, decodes for precompensation of write data. 


17 


WDA 


WRITE DATA - TTL input, write floppy data from the ^PD765A. 


18 


WE 


WRITE ENABLE - TTL input, from the ;iPD765A to enable writing data on the floppy disk. 


19 


WRDATA 


WRITE DATA - TTL output, precompensated data from the WD16C92 to be written on 
the floppy drive. 


20 
21 


GND 
MR 


GROUND 


MASTER RESET - TTL input, clears all internal conditions to be reset. WD16C92 will 
default to the 500 Kbs data rate following a MR. 


22 


FDATA 


READ DATA - TTL input, raw read data from the floppy drive. 


23 


24MCLK 


24 MHz CLOCK TEST POINT - TTL output, for test monitoring only; NOT to be used 
to drive any external circuitry. 


24 


XTL 


CRYSTAL RETURN - TTL output, return for 24 MHz crystal when used; otherwise not 
connected. 


25 


XTL 


CRYSTAL INPUT - TTL input connection for 24 MHz crystal. Can optionally be used for 
24 MHz TTL level square wave clock input. 


26 
27 


UP03 
DN03 


UP PUMP 3 - Open drain output, provides up pump for 125 Kbs data rate. 


DOWN PUMP 3 - Open drain output, provides down pump for 125 Kbs data rate. 


28 
29 


UP02 
DN02 


UP PUMP 2 - Open drain output, provides up pump for 250 Kbs data rate. 


DOWN PUMP 2 - Open drain output, provides down pump for 250 Kbs data rate. 


30 
31 


UP01 
DN01 


UP PUMP 1 - Open drain output, provides up pump for 300 Kbs data rate. 


DOWN PUMP 1 - Open drain output, provides down pump for 300 Kbs data rate. 


32 
33 


UPOO 
DNOO 


UP PUMP - Open drain output, provides up pump for 500 Kbs data rate. 


DOWN PUMP - Open drain output, provides down pump for 500 Kbs data rate. 



2-10 



Floppy Disk Support Devices 



SIGNAL DESCRIPTION (cont.) 



PIN 


MNEMONIC 


DESCRIPTION 


34 

35 

36 
37 

38 

39 

40 


FDRQ 

FIRQ 

FINT 
FDMAEN 


DELAYED DATA REQUEST - TTL TRI-STATE output, is the DRQ delayed by 2 jiS and 
enabled by FDMAEN. 

INTERRUPT REQUEST - TTL TRI-STATE output, generates an interrupt request on the 
PC/AT compatible bus and is gated by FDMAEN. 

FLOPPY INTERRUPT - TTL input from ;iPD765A to generate bus interrupt request. 

FLOPPY DMA ENABLE - TTL input to gate FIRQ and FDRQ onto the PC/AT compatible 
bus. 


DACK 

DRQ 

VCC 


DATA ACKNOWLEDGE - TTL input, data acknowledge signal from the PC/AT 
compatible bus. 

DATA REQUEST - TTL input, from the mPD765A to request a data transfer between the 
data bus. 

+ 5 volt ±5% power supply input. 



D 

o> 
O 

CO 



Floppy Disk Support Devices 



2-11 



2-12 Floppy Disk Support Devices 



WESTERN DIGITAL 

CORPORATION 

WD2143-03 Four Phase Clock Generator 



FEATURES 

IMPROVED VERSION OF WD2143-01 
TRUE AND INVERTED OUTPUTS 
SINGLE 5 VOLT SUPPLY 
TTL COMPATABLE 
ON CHIP OSCILLATOR 
TTL CLOCK INPUT 
TTL CLOCK OUTPUT 
PROGRAMMABLE PULSE WIDTHS 
PROGRAMMABLE PHASE WIDTHS 
NO EXTERNAL CAPACITOR 



GENERAL DESCRIPTION 

The WD2143-03 Four-Phase Clock Generator is a 
MOS/LSI device capable of generating four phase 
clocks. The ouput pulse widths are controlled by tying 
an external resistor to the proper control inputs. All 
pulse widths may be set to the same width by tying 
the <t>PW line through an external resistor. Each pulse 
width can also be individually programmed by tying 
a resistor through the appropriate <j)1PW-<t>4PW con- 
trol inputs. 



O 

CO 
■ 

o 

CO 



01 PW 



STB IN y- 



04 C 
<M IZ 
03 (Z 
03 
02 

02 a 

01 

01 \Z 

GND C 



ZI vcc 
Z] 0PW 

^ 04 PW 
Z] 03 PW 
Z] 02 PW 

;Z 01PW 

Zl NC 
Z] STB IN 
Z]NC 



02 PW y- 



03 PW y- 



PIN DESIGNATION 



04PW y 

0PW y- 



osc 



— WV — '^ 






T Q 
01 

Q 



_^^V\ 'y 



J Q 
02 
Q 



-A/V^. >y 



Ht q 



03 



-^^A '^ 



t q 

04 
Q 



01 



02 



02 



-► 03 



->- 03 
■^' 04 



04 



Figure 1. WD21 43-03 BLOCK DIAGRAM 



DEVICE OPERATION 

Each of the phase outputs can be controlled 
Individually by tying an external resistor from <}>1PW- 
<}>4PW to a +5V supply. When it is desired to have 
^^ through <t>4 outputs the same width, the <t)1PW- 
<|>4PW inputs should be left open and an external 



resistor tied from the <t)PW (Pin 17) input to +12V. 
STROBE IN (pin 11) is driven by a TTL square wave. 
Each of the four phase outputs provide both true and 
inverted signals, capable of driving 1 TTL load each. 



Floppy Disk Support Devices 



2-13 



PIN NUMBER 


SYMBOL 


DESCRIPTION 


1,3,5,7 


ff-H 


Four phase clock outputs. These outputs are inverted (active low). 


2,4,6,8 


</.1-04 


Four Phase clock outputs. These outputs are true (active high). 


9 


GND 


Ground. 


10 


NC 


No connection. 


11 


STB IN 


Input signal to initiate four-phase clock outputs. 


12 


NC 


No connection. 


13-16 

17 
18 


</)1PW-<^4PW 

0PW 
Vcc 


External resistor inputs to control the individual pulse widths of each output. 
These pins can be left open If </)PW is used. 

External resistor input to control all phase outputs to the same pulse widths. 
+ 5V ± 5% power supply input. 



Table 1. PIN DESCRIPTIONS 



TYPICAL APPLICATIONS 



VD1691 



STB 



2K 



^ 



12 )~'V\A— VWVWV — T 

10K "^ 



WD2143^3 
STB IN 

0PW 



7400 p 



STB IN 

WD2143-03 



Figure 2. WRITE PRECOMP OPERATION 
WITH F.S.L. WD1691 



Figure 3. TTL SQUARE WAVE OPERATION 



+ 12 



STB IN 
WD2 143-03 ^1 



0PW 



<*1 
<*2 
<t>3 



+ 5 
V 



I Wr-!^ 



10K 



STB IN 
01PW <*1 



02PW <A2 

WD2 143-03 
03PW <*3 



Figure 4. EQUAL PULSE WIDTH OUTPUTS 



Figure 5. INDIVIDUAL PULSE WIDTH OUTPUTS 



2-74 



Floppy Disk Support Devices 



L^= 



u 




Figure 6. WRITE PRECOMP FOR FLOPPY DISK 



l-t-tpD 










♦tpvv*. 

"N r 



o 

■(:» 

CO 
I 

o 

CO 



Figure 7. WD21 43-03 TIMING DIAGRAM 

SPECIFICATIONS Note: Maximum ratings Indicate limits beyond which 

Absolute Maximum Ratings permanent damage may occur. Continuous operation 

Operating ^^ these limits is not intended and should be limited 

Temperature 0°C (32°F) to +70°C (158°F) to the DC electrical characteristics specified. 

Voltage on any pin with 

respect to Ground* -0.5 to +7V *pin 27 = -0.5V to + 12V. Increasing voltage on Pin 

Power Dissipation 1 Watt 17 will decrease Tp^ 

Storage Temperature 

plastic -55°C (-67°F) to + 125°C (257°F) 

ceramic -65°C (-85°F) to + 150°C (302°F) 

DC ELECTRICAL CHARACTERISTICS 

Vcc = 5V ± 5%, GND = OV, Ta = 0°C (32°F) to 70°G (158°F). 



SYMBOL 


PARAMETER 


MIN 


MAX 


UNITS 


CONDITIONS 


Vol 


TTL low level output 




0.4 


V 


Iql = 1.6 m A 


VoH 


TTL high level output 


2.0 




V 


loH = -100/i A 


V|L 


STB In low voltage 




0.8 


V 




V,H 


STB In high voltage 


2.4 




V 




'cc 


Supply Current 




80 


mA 


All outputs open 



Table 2. DC ELECTRICAL CHARACTERISTICS 



Floppy Disk Support Devices 



2-15 



o 

to 

I 

O 
CO 



SWITCHING CHARACTERISTICS 

Vcc = 5V ± 5%, GND = OV, T^ = 0°C (32°F) to 70°C (158°F) 



SYMBOL 


CHARACTERISTIC 


MIN. 


MAX. 


UNITS 


CONDITIONS 


tpD 


STB IN to 01 




140 


ns 




'pw 


Pulse Width (any output) 


100 


300 


ns 


CL = 30pf 


tpR 


Rise Time (any output) 




30 


ns 


CL = 30pf 


tpF 


Fall Time (any output) 




25 


ns 


CL = 30pf 


fs 


STROBE PULSE WIDTH 




1.0 


ns 


combined tp^ = 400 ns 


towp 


Pulse Width Differential 




±10 


% 


Referenced to <A1, 100-300 ns 



Table 3. SWITCHING CHARACTERISTICS 
Note: Tpw measured at 50% Vqh Point; Vql = 0.8V, Vqh = 2.0V. 



2-16 



Floppy Disk Support Devices 



WESTERN DIGITAL 

CORPORATION 

WD9216-00/WD9216-01 
Floppy Disk Data Separator — FDDS 



o 

to 

I 

o 
o 



FEATURES 

• PERFORMS COMPLETE DATA SEPARATION 
FUNCTION FOR FLOPPY DISK DRIVES 

• SEPARATES FM OR MFM ENCODED DATA 
FROM ANY MAGNETIC MEDIA 

• ELIMINATES SEVERAL SSI AND MSI DEVICES 
NORMALLY USED FOR DATA SEPARATION 

• NO CRITICAL ADJUSTMENTS REQUIRED 

• COMPATIBLE WITH WESTERN DIGITAL 179X, 
176X AND OTHER FLOPPY DISK CONTROLLERS 

• SMALL 8-PIN DUAL-IN-LINE PACKAGE 

• +5 VOLT ONLY POWER SUPPLY 

• TTL COMPATIBLE INPUTS AND OUTPUTS 



GENERAL DESCRIPTION 

The Floppy Disk Data Separator provides a low cost 
solution to the problem of converting a single stream 
of pulses from a floppy disk drive into separate Clock 
and Data Inputs for a Floppy Disk Controller. 

The FDDS consists primarily of a clock divider, a long- 
term timing corrector, a short-term timing corrector, 
and reclocking circuitry. Supplied in an 8-pin Dual- 
in-Line package to save board real estate, the FDDS 
operates on -F 5 volts only and is TTL compatible on 
all inputs and outputs. 

The WD9216 is available in two versions; the 
WD9216-00, which is intended for 5 1 / 4" disks and 
the WD9216-01 for 5 1/4" and 8" disks. 











DSKD [2 


1 


J 

8 


3 vcc 


SEPCLK [2 


2 


7 


^ SEPD 


REFCLK \2 


3 


6 


"^ GDI 


GND Q 


4 


5 


^ CDO 











PIN CONFIGURATION 



REFCLK ► 

CDO ► 

CD1 ► 

DSKD ► 


















CLOCK 
DIVIDER 






-+5V 












— tJNU 




' 






DATA/CLOCK 

SEPARATION 

LOGIC 






PULSE 

REGENERATION 

LOGIC 


— ^ SEPCLK 
— ^ SEPD 










' 










' 








EDGE 

DETECTION 

LOGIC 













































FLOPPY DISK DATA SEPARATOR BLOCK DIAGRAM 



Floppy Disk Support Devices 



2-17 



o 

I 

o 
o 



ELECTRICAL CHARACTERISTICS NOTE: When powering this device from laboratory or 

IVIAXIIViUM RATINGS* system power supplies, it is important that the 

Absolute iVIaximum Ratings not be exceeded or 

Operating Temperature Rnge 0°C to + 70°C device failure can result. Some power supplies exhibit 

Storage Temperature Range -55°C TO 125° voltage spikes or "glitches" on their outputs when 

Positive Voltage on any Pin, the AC power is switched on and off. In addition, 

with respect to ground + 8.0V voltage transients on the AC power line may appear 

Negative Voltage on any Pin, on the DC output. If this possibility exists it is sug- 

with respect to ground -0.3V gested that a clamp circuit be used. 

'stresses above those listed may cause permanent 
damage to the device. This is a stress rating only and 
functional operation of the device at these or at any 
other condition above those indicated in the opera- 
tional sections of this specification is not implied. 

OPERATING CHARACTERISTICS (Ta = 0°C to 70°C, Vqc = ± 5%, unless otherwise noted.) 



PARAMETER 


MIN. 


TYP. 


MAX. 


UNITS 


COMMENTS 


D.C. CHARACTERISTICS 












INPUT VOLTAGE LEVELS 












Low Level V|l 






0.8 


V 




High Level V|l 


2.0 






V 




OUTPUT VOLTAGE LEVELS 












Low Level Vql 






0.4 


V 


Iql = 1.6 m A 


High Level Vqh 


2.4 






V 


loH = -100 A 


INPUT CURRENT 












Leakage I|l 






10 


/.A 


< V,N< Vdd 


INPUT CAPACITANCE 












All Inputs 






10 


PF 




POWER SUPPLY CURRENT 












'dd 






50 


mA 




A.C. CHARACTERISTICS 












Symbol 












fcY REFCLK Frequency 


0.2 




4.3 


MHz 


WD9216-00 


fcY REFCLK Frequency 


0.2 




8.3 


MHz 


WD9216-01 


tcKH REFCLK High Time 


50 




2500 


ns 




tr^i REFCLK Low Time 


50 




2500 


ns 




tc;nnM REFCLK to SEPD "ON" Delay 




100 




ns 




tsDOFF REFCLK to SEPD "OFF" Delay 




100 




ns 




tspcK REFCLK to SEPCLK Delay 


100 






ns 




tpLL DSKD Active Low Time 


0.1 




100 


/tS 




toLK DSKD Active High Time 


0.2 




100 


US 







4 fry - 1 




A 










REFCLK '*■ 


^»CKH««- 


■*tCKLi- 


i 


r 


/ 


\ 


/ 




^ 


^ » 


tsc 


)0N 


* — >■ 


tSDOFF 




SEPD- ' N 


^ 


~ 
















— 


}. 




• — *DW — *■ 










DSKD. \ 


r 










' 










1 



Figure 3. AC CHARACTERISTICS 



2-18 



Floppy Disk Support Devices 



DESCRIPTION OF PIN FUNCTIONS 



PIN 








NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


1 


Disk Data 


DSKD 


Data input signal direct from disk drive. Contains combined 
clock and data vi/aveform. 


2 


Separated Clock 


SEPCLK 


Clock signal output from the FDDS derived from floppy disk 
drive serial bit stream. 


3 


Referenced Clock 


REFLCK 


Reference clock input. 


4 


Ground 


GND 


Ground. 


5,6 


Clock Divisor 


CD0,CD1 


CDO and CD1 control the internal clock divider circuit. The 
internal clock is a submultiple of the REFCLK according to 
the following table: 

CD1 CDO Divisor 
1 

1 2 

1 4 


7 






1 1 8 
SEPD is the data output of the FDDS. 


Separated Data 


SEPD 


8 


Power Supply 


Vcc 


+ 5 volt power supply. 



o 

a> 

o 

o 























1 




4 MHz CRYSTAL 
OSCILLATOR 














+ 4 


1MHz 


















' 










1 






FLOPPY 
DISK 
DRIVE 




REFCLK 

SEPD 

DSKD 

WD9216-00, 01 

SEPCLK 
CDO GDI 


REGENERATED DATA 


ri 


.K 




RAW READ 


DERIVED CLOCK 


WD179X, 176X or Equlv. 
FLOPPY DISK 
CONTROLLER 

RCLK 


DISK DATA 












GND GND 













Figure 1. TYPICAL SYSTEM CONFIGURATION 
(5 1/ 4" Drive, Double Density) 



OPERATION 

A reference clock (REFCLK) of between 2 and 8 MHz 
is divided by the FDDS to provide an internal clock. 
The division ratio is selected by inputs CDO and CD1. 
The reference clock and division ratio should be 
(Chosen per Table 1. 

The FDDS detects the leading edges of the disk data 
pulses and adjusts the phase of the internal clock 
to provide the SEPARATED CLOCK output. 



Separate short and long term timing correctors assure 
accurate clock separation. 

The internal clock frequency is nominally 16 times 
the SEPCLK frequency. Depending on the internal tim- 
ing correction, the internal clock may be a minimum 
of 12 times to a maximum of 22 times the SEPCLK 
frequency. 

The reference clock (REFCLK) is divided to provide 
the internal clock according to pins CDO and CD1. 



Floppy Disk Support Devices 



2-19 



Table 1. CLOCK DIVIDER SELECTION TABLE 



D 

CO 

o 
o 



DRIVE 

(8" or 5 1 / 4") 


DENSITY 
(DD or SD) 


REFCLK 
MHz 


CD1 


CDO 


REMARKS 


8 
8 
8 


DD 
SD 
SD 


8 
8 

4 









1 




Select either one 


5 1/4 
5 1/4 


DD 
DD 


8 

4 






1 




Select either one 


5 1/4 
5 1/4 
5 1/4 


SD 
SD 
SD 


8 
4 
2 


1 







1 




Selecct any one 



INTCLK 

SEPCLK 
SEPD 



JTJTTLTXriJlJlJlJlJTrLJlJlJlJTJl^^ 



I I 
n — *^ 

always two internal clock cycles 



Figure 2. REFERENCE CLOCK TIMING 



2-20 



Floppy Disk Support Devices 



WESTERN DIGITAL 



O R 



ORATION 



WD92C32 Floppy Disk Digital Data Separator 



FEATURES 

• HIGH PERFORMANCE DIGITAL DATA 
SEPARATOR (Low error rates) 
NO ADJUSTMENTS 
8 PIN DIP 
TTL COMPATIBLE 
CMOS 

SINGLE 5V SUPPLY 
PIN FUNCTION COMPATIBLE WITH THE WD9216 



DSKDIJ 
SEPCLK Q 
REFCLK Fa" 
VssCI 



\->^ 



JjVcc 



SEPD 
"HcDI 
3] CDO 



GENERAL DESCRIPTION 

The WD92C32 digital data separator has been 
designed to address the high performance SVa" or 
8" floppy disk drive nnarket. It is pin function com- 
patible with the WD9216, although it provides superior 
performance in terms of available bit jitter window 
margins. The WD92C32 is designed to operate at data 
rates of 125, 250 and 300, and 500 Kb/s. 

The WD92C32 is a CMOS LSI product with TTL com- 
patible I/O which operates from a single 5 volt supply. 
Packaged as an 8 pin DIP, the WD92C32 represents 
a significant cost savings when compared to the cost 
of the analog components required to achieve equal 
performance. 

The device contains an internal power-up reset along 
with all of the necessary logic to achieve classical 
2nd order phase locked loop performance. 
Implemented digitally this design does not require any 
external adjustments or any additional logic to per- 
form the data separation. 



O 

CO 
O 

ro 

o 

o 



PIN CONFIGURATION 



DESCRIPTIONS OF PIN FUNCTIONS 



PIN NUMBER 


MNEMONIC 


SIGNAL NAME 


FUNCTION 


1 






Data input signal from the floppy drive containing both clock 


DSKD 


Disk Data 








and data information. 


2 


SEPCLK 


Separated Clock 


Resultant clock recovered from the disk serial bit stream. 
Sometimes called RCLK. 


3 


REFCLK 


Reference Clock 


Reference clock input from a crystal oscillator. 


4 


Vss 


Ground 


Ground 


5 


CDO, 


Clock Divisor 


Encoded bits which are used to select 1 of 4 reference clock 


6 
7 


CD1 




division factors. 

Sometimes called RDATA, this is still the encoded serial 


SEPD 


Separated Data 








bit stream, but which has been re-synchronized to the phase 








of Recovered Clock. 


8 


Vcc 


Power Supply 


+ 5V power supply 



Floppy Disk Support Devices 



2-21 



2-22 Floppy Disk Support Devices 



WESTERN DIGITAL 

CORPORATION 



WD1010-05 Winchester Disk Controller 



o 

I 

o 

U1 



FEATURES 

ST506-SA1000 COMPATIBLE 

MULTIPLE SECTOR READ/WRITE 

UP TO 5 MBITS/SEC DATA RATE 

UNLIMITED SECTOR INTERLEAVE 

AUTOMATIC FORMATTING 

CRC/ECC CAPABILITY WITH EXTERNAL ECC 
GENERATOR/CHECKER 

PROGRAMMABLE RETRIES 

VARIABLE SECTOR SIZE 

SINGLE +5V SUPPLY 

DESCRIPTION 

The WD1010-05 is a MOS/LSI device which performs 
the functions of a Winchester Disk Controller/Format- 
ter. It is compatible with the Seagate ST506 and the 
Shugart Associates SA1000 drives, as well as all other 
5 Vi" and 8" products utilizing the same type of inter- 
face. On the host side, an 8-bit bi-directional bus 
accepts all commands, data, and status bytes. The 
Western Digital WD1000 series of board level con- 
trollers are software compatible with the WD1010-05. 

Operating from a single 5 volt supply, the WD1010-05 
is implemented in NMOS silicon gate technology and 
is available in a 40-pin dual-In-line and QSM package. 

ARCHITECTURE 

The WD1010-05 Winchester Disk Controller provides 
the necessary link between an 8-bit, parallel processor 
and a Winchester disk drive. The WD1010-05 may be 
programmed to either automatically retry errors, or 
to terminate the command. The internal architecture 
of the WD1010-05 is shown in Figure 1. Its major func- 
tional blocks are: 

PLA Controller 

The PLA interprets commands and provides all con- 
trol functions. It is synchronized with WCLK. 

Magnitude Comparator 

A 10-bit magnitude comparator is used for calcula- 
tion of drive step, direction, present and desired 
cylinder position. 



BCSCZ 


1 ^ 40 


bcrcz: 


2 


39 


intrqCZ; 


3 


38 


NCCZj 


4 


37 


MR en 


5 


36 


RE[= 


6 


35 


weCZ 


7 


34 


nsl 


8 


33 


AnI 


9 


32 


AiCZ 


10 


31 


A2l= 


11 


30 


D7C= 


12 


29 


D6l 


13 


28 


D5L 


14 


27 


D4l= 


15 


26 


03 1 


16 


25 


n9l 


17 


24 


Dll= 


18 


23 


nni. 


19 


22 


VssCZ: 


20 


21 



ivcc 

I RCLK 
I RG 
I RD 
I BDRQ 
I BRDY 
I DRUN 
I RWC 
I SC 
I TKOOO 
I WF 
I INDEX 
I DRDY 
I STEP 
I DIRIN 
I WCLK 
I WG 
I EARLY 
I LATE 
WD 



BDRQd 40 

rdC 

rgQ 

rclkCZ 

VccC 

bcsC 
bcrCZ 

INTRQ m 

NCd 
NCC 
NO [2 



PIN DESIGNATION 



T ' D 

B D K N D S I W 

RRR DRTRC 

nnnnnn n n n nn 



39 38 37 36 35 34 33 32 31 30 29 



28 3^ NC 
27 21] WG 



25 H] LATE 



7 8 9 10 11 12 13 14 15 16 17 



uuuuuuuuuuu 



EARLY 



1 WD 

23 1 I Vss 

I DO 
|D1 
I D2 
I D3 
18 1 I D4 



M R W 
REE 



A A A D D D 
1 2 7 6 5 



QUAD PIN DESIGNATION 



Winchester Disk Controller Devices 



3-1 



PIN DESCRIPTION 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


FUNCTION 


1 
2 


BCS 
BCR 


BUFFER CHIP SELECT 


Active low output used to enable reading or writing 
of the external sector buffer. 

Active low output that is strobed by the WD1010-05 
prior to read/write operations. This pin is strobed 
whenever BCS changes state. 


BUFFER COUNTER 
RESET 


3 


INTRQ 


INTERRUPT REQUEST 


INTRQ is an output asserted upon completion of 
a command and de-asserted when the Status 
Register is read or a new command is written into 
the Command Register. This signal can be pro- 
grammed to occur with BDRQ and DRQ during 
Read Command. 


4 


NC 


NO CONNECTION 




5 
6 

7 

8 


MR 
RE 

WE 

CS 


MASTER RESET 


A logic low in this input will initialize all internal 
logic. 

Tri-state bi-directional line used as an input for 
reading the task register and an output when the 
WD1010-05 is reading the buffer. 

Tri-state bi-directional line used as an input for 
writing into the task register and as an output when 
the WD1010-15 is writing to the buffer. 

A logic low on this input enables both WE and 
RE signals. 


READ ENABLE 


WRITE ENABLE 


CHIP SELECT 


9 
10 
11 


AG 
A1 
A2 


ADDRESS 
ADDRESS 1 
ADDRESS 2 


These three inputs select the register to re- 
ceive/transmit data on D0-D7. 


12 

thru 

19 


D7 

thru 

DO 


DATA 7 

thru 

DATAO 


8-bit tri-state bi-directional bus used for transfer of 
commands, status, and data. 


20 


Vss 


GROUND 


Ground. 


21 

22 
23 


WD 


WRITE DATA 


This output contains the MFM clock and data 
pulses to be written on the disk. 

Precompensatlon outputs used to delay the WD 
pulses externally. 


LATE 
EARLY 


LATE 
EARLY 


24 


WG 


WRITE GATE 


This output is set to a logic high before writing is 
to be performed on the disk. 


25 


WCLK 


WRITE CLOCK 


4.34 or 5.0 MHz clock input used to derive all inter- 
nal write timing. 


26 


DIRIN 


DIRECTION IN 


This output determines the direction the stepping 
motor will move the heads. High = in, Low = out. 


27 


STEP 


STEP PULSE 


This output generates a pulse for stepping the drive 
motor. 


28 


DRDY 


DRIVE READY 


This input must be at a logic high in order for com- 
mands to execute. 


29 


INDEX 


INDEX PULSE 


A rising edge on this input informs the WD1010-05 
when the index hole has been encountered. 


30 


WF 


WRITE FAULT 


An error input to the WD1010-05 which indicates 
a fault condition at the drive. 


31 


TKOOO 


TRACK 000 


An input to the WD1010-05 which indicates posi- 
tioning over track 000. 



3-2 



Winchester Disk Controller Devices 



PIN DESCRIPTION (Continued) 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


FUNCTION 


32 


SC 


SEEK COMPLETE 


A rising edge on this input informs tlie WD1010-05 
when head settling time has expired. In the For- 
mat Command, it is used to extend the gap. 


33 


RWC 


REDUCED WRITE 
CURRENT 


This output can be programmed to reduce write 
current on a selected starting cylinder. 


34 


DRUM 


DATA RUN 


This input informs the WD1010-05 when a field of 
ones or zeroes have been detected. 


35 


BRDY 


BUFFER READY 


The rising edge of this input informs the controller 
that the Sector Buffer is full or empty. 


36 


BDRQ 


BUFFER DATA 
REQUEST 


BDRA and DRQ (Bit 3 Status Register) are asserted 
when the Buffer is to be read from or written to, 
by the Host. BDRQ can be used by a DMA con- 
troller or by the Host during Programmed I/O. DRQ 
must be polled by the Host if used during pro- 
grammed I/O. 


37 


RD 


READ DATA 


Data input from the Drive. Both MFM clocks and 
data pulses are entered on this pin. 


38 


RG 


READ GATE 


This output is set to a logic high when data is 
being inspected from the disk. 


39 


RCLK 


READ CLOCK 


A nominal square wave clock input derived from 
the external data recovery circuits. 


40 


Vcc 


+ 5 VOLT 


-fSV 



I/O BUFFERS 



RE 

WE 

A2-A0 

INTRQ 

"mr 
cs 

BCR 
BRDY 
BDRQ 

BOS 

Vcc 

VSS 



f^ 



ORG LOGIC 



HOST 
IPC 



MAGNITUDE 
COMPARATOR 



BUFFER 
IFC 



PLA 
CONTROLLER 



PARALLEL 

TO 

SERIAL 




MFM 
ENCODER 





• WD 
WCLK 



SERIAL 

TO 

PARALLEL 






MFM 
DECODER 





SYNCHRONIZER 



DRIVE 
IFC 



PPL 
IFC 



STEP 
DIRIN 
EARL Y 
LATE 

DRDY 
WF 

TKOOO 
INDEX 
SC 

RWC 
WG 
RG 
DRUN 



FIGURE 1. 
WD1010 BLOCK DIAGRAM 



Winchester Disk Controller Devices 



3-3 



g 
o 

O 
O 



CRC Logic 

Generates and checks the cyclic redundancy check 
characters appended to the ID and data fields. The 
polynomial is X^^ + X^^ ^X^ + 1. 

MFM Encode/Decode 

Encodes and decodes MFM data to be written/read 
from the drive. The MFM encoder operates from 
WCLK; a clock having a frequency equivalent to the 
bit rate. The MFM decode operates from RCLK; a bit 
rate clock generated from the external data separator. 
RCLK and WCLK need not be synchronized. 

AM Detect 

The address mark detector checks the incoming 
data stream for a unique missing clock pattern 
(Data = A1 hex, Clock = OA hex) used in each 
ID and data field. 

Host/Buffer IFC 

This logic contains all of the necessary circuitry 
to communicate with the 8-bit host processor. 



Drive IFC 

This logic controls and monitors all lines from the 
drive, with the exception of read and write data. 

DRIVE INTERFACE 

The drive side of the WD1010-05 controller requires 
three sections of external logic. These are buf- 
fers/receivers, data separator, and write precompen- 
sation. Figure 2 illustrates a drive side interface. 

The buffer/receivers condition the control lines to be 
driven down the cable to the drive. The control lines 
are typically single-ended, resistor terminated TTL 
levels. The data lines to and from the drive also 
require buffering, but are differential RS-422 levels. 
The interface specification to the drive can be found 
in the manufacturers' OEM manual. The WD1010-05 
supplies TTL compatible signals, and will interface 
to most buffer/driver devices. 

The data recovery circuits consist of a phase-lock 
loop data separator and associated components. The 
WD1010-05 interacts with the data separator through 
the DRUN and RG signals. The block diagram of the 



/ N 
















1 


RG 
DRUN 

RD 
RCLK 

WD1010 

WD 
EARLY 

LATE 
RWC 

STEP 

DIRIN 

DRDY 

WF 

TKOOO 

INDEX 

SC 

WG 




DATA 
SEPARATOR 






* 












/'^\ 








WRITE 
PRECOMPENSATION 

AND 
SYNCHRONIZATION 






I ^ ' 




DISK 
DRIVE 




HOST ( DATA/CTRL \ 




* 


\ / 














BUFFER/ 
RECEIVERS 




* 








^ 


■ 




^ 






"* 




* 


1 

























FIGURE 2. DRIVE INTERFACE BLOCK DIAGRAM 









































RETRIGGERABLE 
ONE-SHOT 




DRUN 

RD 

WD1010 

RCLK 

RG 
WCLK 










MFM 

nrck- X., 1 














DATA "^ 








l_ 


J Q 

C 

K 








1 


PHASES. 
COMJX' 






r 


l- 




FILTER 
AND VCO 






A 

MUX 
B 






h r 






'* 


H.2 M 




' 






, 




























+ 2 




10 MHZ 
OSC 























































FIGURE 3. DATA RECOVERY CIRCUIT 



3-4 



Winchester Disk Controller Devices 



















1 


c 


START 
(RG DE-ASSERTED) 


) 












A 




/ DRUN \ 


NO 






\^ 2 BYTE TIMES /^ 






y^YES 






ASSERT RG 






j/dhvnk 

/assertedV 

/an additional^ 


MO 






\ 5 TIMES ^ 

\ BYTE / 

>^R more/ 








N/yes 










/\ 


1 




VES 


/ AM \. 

< (A1) > 

\ DETECTED / 














^fNO 










/ DRUN \n° 

V DE-ASSERTED / " 










Yyes 








/ AM \ 

/ OCCURRED X 

\ IN 1-1/2 /■ 

\ BYTES / 


MO 










Jl YES 






/ proper \_ 


NO 






v. ID field ?" 




'' 


' 




\/ 


DE-ASSERT 
RG 




Iyes 










▼ 










c 


TO DATA 
FIELD 


^ 




K, 


J 

























o 

o 

o 
■ 

o 



FIGURE 4. PLL CONTROL SEQUENCE FOR ID FIELD 



Winchester Disk Controller Devices 



3-5 



o 

o 
o 
o 



c 


FROM 

10 
FIELD 


) 


1 


DE-ASSERT 
RG 







TRANSFER 

DATA AND 

CHECK CRC/ECC 



FIGURE 4. (CONT.) 
PPL CONTROL SEQUENCE FOR DATA FIELD 



data separator circuit Is shown in Figure 3. Read data 
from the drive is presented to the RD input of the 
WD1010-05, the reference multiplexor, and a retrig- 
gerable one shot. The read gate output will be low 
when the WD1010-05 is not inspecting data. The PLL 
at this time should remain locked to the reference 
ciocl<. 

When any Read/Write command is initiated and a 
search for address marl<s begins, the DRUM input is 
examined. The DRUM one-shot is set for slightly 
greater than one bit time, allowing It to retrigger con- 
stantly on a field of ones and zeroes. An internal 
counter times out to see that DRUN is high for 2 byte 
times. Read gate is set by the WD1010-05, switching 
the data separator to lock onto the incoming data 
stream. If DRUN falls prior to 7 bytes times, RG is 
lowered and the process Is repeated. Read gate will 
remain active high until a non-zero, non-address mark 
byte Is detected. It then will lower read gate for 2 byte 
times (to allow the PLL to lock back on the reference 
clock) and start the DRUN search over again. If an 
address mark is detected, read gate will be held high 
and the command will continue searching for the pro- 
per ID field. This sequence is shown In the flow chart 
of Figure 4. 

The write prec ompens ation logic is controlled by the 
signals RWC, EARLY and LATE. The cylinder in 
which the RWC line becomes active Is controlled by 
a register in the Task File. It can be used to turn on 
the precomp circuitry on a predetermined cylinder. 
If the write precomp register value is FF, then RWC 
will always be low. 

The signals EARLY and LATE are used to tell the 
precomp how much delay is required on the write 
data pulse about to be sent. The amount of delay is 
determined externally through a digital delay line 
or equivalent circuitry. Since the signal EARLY oc- 
curs after the fact, write da ta sh ould b e delayed one 
Interval when both EA RLY an d LATE are deassert- 
ed; two Inte rvals wh en LATE is asserted; and no 
delay when EARLY is asserted. A n Inter val, for 
exam ple, is 12-15 ns. on the ST506. EARLY or 
LATE will be a ctiv e sligh tly ahead of the write data 
pulse; EARLY and L ATE wi l l neve r be asserted at 
the same time. The EARLY LATE signals function 
independently of the content of the RWC register. 

Examples for all three of the above circuits can be 
found in the WD1010 Application Note. 

HOST INTERFACE 

The primary Interface between the host processor and 
the WD1010-05 is through an 8-bit bi-directional bus. 
This bus is used to transmit/receive data to both the 
WD1010-05 and a sector buffer. The sector buffer is 
constructed with either FIFO memory or static RAIV1 
and a counter. Since the WDIOIOOS will make the bus 
active when accessing the sector buffer, a transceiver 
must be used to isolate the host during this time. 
Figure 5 shows a typical connection to a sector buf- 
fer implemented with RAM memory. 



3-6 



Winchester Disk Controller Devices 



Whenev er the WD1 01005 is not using the sector buf- 
fer, the BCS is de-asserted. This allows the host to 
access the WD1010's Task File, and to set up 
parameters prior to issuing a command. It also allows 
the host to access the RAM buffer. A decoder is used 
to generate a chip select when Aq- A2 are '000'; an 
unused address in the WD1 01 0-05. A binary counter 
is enabled whenever RE or WE goes active and in- 
cremented on the trailing edge of the chip select. This 
allows the host to access sequential bytes within the 
RAM. The decoder also generates another chip select 
when A0-A2 '000'; allowing access to the 
WD1010O5's internal registers while keeping the RAM 
tri-stated. 

During write sector commands, the processor sets 
up data in the Task File and issues the command. 
The WD1010 then generates a status to inform the 
host it may load the buffer with the data to be writ- 
ten. When the counter reaches its maximum count, 
the BRDY signal is made active (by the "carry" out 
of the counter), informing the WD1010-05 that the 



buff er is f ull. (BRDY is a rising edge activated signal). 
The BCS is then asserted, disconnecting the host 
through the transceivers, and the RE and WE lines 
become outputs from the WD1010-05 to allow it 
access to the buffer. When the W D1010-05 is done 
using the buffer, it disables BCS which again 
allows host access to this local bus. The read sec- 
tor commands operate in a similar manner, except 
the buffer is loaded by the WD1010-05 instead of the 
host. 

Another control signal called BDRQ can be connected 
to a DMA controller in the Host, or can be polled by 
the Host for programmed I/O. For further explanation, 
refer to the description of the individual commands 
and the A.C. Timing Specifications. In a read com- 
mand; an interrupt may be specified to occur either 
at the end of the command or when BDRQ is 
activated. The INTRQ is cleared either by reading the 
status register or by writing a new command in the 
command register. 



O 

o 
o 

■ 

o 
en 



i ^ 




hv 


s 






RE 
WE 

DoD7 
BCR 

WD1010 

BCS 

"cs 

Ao-2 
BRDY 
BDRQ 






1 












' 


DATA BUS (8) 












n 


1 ~ 


DATA 






TRANSCEIVER 
























"^ 




















\ 












-1 






HOST 
PROCESSOR 


r 


Qo 

>CK ; 

MR • 
TC °X 






Aq DATA 
Ai RE 

• WE 

"^ CS 
















1 — 


D 
E 
C 

D 
E 














i 










^ 




' 








SEL 


^/ ,. 


" 






3/ 




/ • 










/ 








CP 
RST 


N.U. 














^0' 


? 






J 







FIGURE 5. 
HOST INTERFACE 



Winchester Disk Controller Devices 



3-7 



o 

CJl 



TASK FILE 

The Task File is a bank of nine registers used to hold 
parameter information pertaining to each command. 
These registers and their addresses are: 



Aj Ai Aq 


READ 


WRITE 





(Bus Tri-Stated) 


(Bus Tri-Stated) 


1 


Error Flags 


Write Precomp 
Cylinder 


1 


Sector Count 


Sector Count 


1 1 


Sector Number 


Sector Number 


1 


Cylinder Low 


Cylinder Low 


1 1 


Cylinder High 


Cylinder High 


1 1 


SDH 


SDH 


1 1 1 


Status Register 


Command 
Register 



NOTE: Registers are not cleared by master reset (MR). 

ERROR REGISTER 

This read-only register contains specific error status 
after the completion of a command. These bits are 
defined as follows: 

7 6 5 4 3 2 10 



BB 


CRC 


- 


ID 


- 


AC 


TK 


DM 



Bit 7 - Bad Block Detect 

This bit is set when an ID field has been encountered 
that contains a bad block mark. Used for bad sector 
mapping. 

Bit 6 - CRC Data Field 

This bit is set when a CRC error occurs in the data 
field. With Retry enabled, ten more attempts are made 
to read the sector correctly. If none of these attempts 
are successful, the Error Status is set also (bit in 
the Status Register). If one of the attempts is suc- 
cessful, this bit remains set to inform the Host that 
a marginal condition exists. However, the Error Status 
bit is not set. Even if errors exist, the data can be read. 

Bit 5 - Reserved 

Not used; forced to a zero. 
Bit 4 - ID Not Found 

This bit is set to indicate that the correct cylinder, 
head, sector number or sector size parameter could 
not be found, or that a CRC error occurred on the ID 
field. This bit is set on the first failure and remains 
set even if the error is recovered on a Retry. When 
recovery is unsuccessful, the Error Status bit is set 
also (bit in the Status Register). 

Bit 3 - Reserved 

Not used; forced to a zero. 
Bit 2 - Aborted Command 

This bit is set if a command was issued while the 
DRDY is de-asserted or the WF is asserted. The 
aborted command bit will also be set if an undefined 
command code is written into the command register, 
but an implied seek will be executed. 



Bit 1 - Track Zero Error 

This bit is set only by the restore command. It 
indicates that the TKOOO has not gone active after the 
issuance of 1024 stepping pulses. 

Bit - Data Address Mark Not Found 

This bit is set during a read sector command if the 
data address mark is not found after the proper sec- 
tor ID is read. 

WRITE PRECOMP CYLINDER 

This register is used to define the cylinder number 
where the RWC is to be asserted: 

7 6 5 4 3 2 10 



CYLINDER NUMBER 



The value 00-FF loaded into this register is internally 
multiplied by 4 to specify the actual cylinder where 
RWC is asserted. Thus, a value of 01 hex will cause 
RWC to activate on cylinder 4; 02 hex on cylinder 8, 
and so on. Switching points are then 0, 4, 8, . . . The 
RWC will be asserted when the present cylinder is 
equal to 4 times or more than the value in this register. 
For example, the ST506 requires precomp on cylinder 
128 (80 hex) and above. Therefore, the write precomp 
cylinder register should be loaded with 32 (20 hex). 

A value of FF hex will always cause RWC to be low, 
no matter what the cylinder number values are. 

SECTOR COUNT 

This register holds the number of sectors that are to 
be transferred to the buffer. 



# OF SECTORS 



This register is used during a multiple sector R/W 
command. The written value is decremented after 
each sector is transferred to the sector buffer. A zero 
represents a 256 sector transfer, a 1 = one sector 
transfer, etc. This register is a "don't care" when 
single sector commands are specified. 

SECTOR NUMBER 

This register holds the sector number of a desired 
sector: 



SECTOR NUMBER 



During a multiple sector command, this register 
specifies the first sector in the transfer. It is internally 
incremented after each transfer of data to the sec- 
tor buffer. The sector number register may contain 
any value from to 255. 

CYLINDER NUMBER LOW 

This register holds the least significant eight bits of 
the desired cylinder number. 



3-8 



Winchester Disk Controller Devices 



1 



LS BYTE OF CYLINDER NUMBER 



Internal to the WD1010-05 is another pair of registers 
that hold the actual position number where the R/W 
heads are located. The cylinder number high and Ikow 
registers can be considered the cylinder destination 
for seeks and other commands. After these com- 
mands are executed, the internal cylinder position 
registers' contents are equal to the cylinder high/low 
registers. If a drive number change is detected on a 
new command, the WD1010-05 automatically reads 
an ID field to update its internal cylinder position 
registers. This affects all commands except a Restore. 



SDH BYTE 

This register contains the desired sector size, drive number, and head number parameters. The format is: 



It is used with the cylinder number high register to 
specify a range of to 1023. 

CYLINDER NUMBER HIGH 

This register defines the two most significant bits of 
the cylinder number desired: 

7 6 5 4 3 2 10 



X 


X 


X 


X 


X 


X 


(9) 


(8) 



o 

01 



7 6 5432 10 

EXTj SIZE I DRJVE | HEAD 



/ 



\ 



6 


5 


SECTOR SIZE 








256 





1 


512 


1 





1024 


1 


1 


128 



4 


3 


DRIVE # 





1 
1 




1 


1 


DSEL1 
DSEL2 
DSEL3 
DSEL4 



2 


1 





HEAD# 











HSELO 








1 


HSEL1 





1 





HSEL2 





1 


1 


HSEL3 


1 








HSEL4 


1 





1 


HSEL5 


1 


1 





HSEL6 


1 


1 


1 


HSEL7 



Both head number and sector size is compared 
against the disks' ID field. Head select and drive 
select lines are not available as outputs from the 
WD1010-05, and must be generated externally. Figure 
6 shows the logic to implement these select lines. 

Bit 7, the extension bit, is used to extend the data 
field by seven bytes when using ECC codes. CRC is 
not appended to the data field when EXT = 1; the 
data field becomes "sector size + 7" bytes long. CRC 
is checked on the ID field regardless of the state of 
the extention bit. Note that the sector size bits are 
written to the ID during a format command. The 



SDH byte written into the ID field is different than the 
SDH register contents. The recorded SDH byte does 
not have the drive number written but does have bad 
block mark written. The format is: 



BAD 
BLOCK 


SIZE 





HEAD# 



6 5 



4 3 



2 1 



V 



AO > 



h=B=i> 



cs >- 



J^ 



■ HSELO 
. HSEL 1 
. HSEL2 



FIGURE 6. 
DRIVE/HEAD SELECT LOGIC 



— DSEL 1 
DSEL2 

— DSEL 3 

— DSEL 4 



Winchester Disk Controller Devices 



3-9 



o 
en 



STATUS REGISTER 

The status register is a read-only register wliich 
informs the host of certain events performed by the 
WD1010 as well as reporting status from the drive 
control lines. The term INTRQ, if set, will be cleared 
when the status register is read. The format is: 
7 6 5 4 3 2 10 



BSY RDY WF SC DRQ 



CIP ERR 



Bit 7 - Busy 

This bit is set whenever the WD1010-05 is accessing 
the disk. Commands should not be loaded into the 
command register while busy is set. Busy is made 
active when a command is written into the WDIOIOOS 
and is deactivated at the end of all commands except 
the read sector. While executing a read sector com- 
mand, busy is deactivated after the sector buffer has 
been filled. When the BUSY bit is set, no other bits 
in either the status or other registers are valid. 

Bit 6 - Ready 

This bit reflects the state of DRDY. 

Bit 5 - Write Fault 

This bit reflects the state of the WF. Whenever the 
WF bit goes high, an interrupt will be generated. 

Bit 4 - Seek Complete 

This bit reflects that state of the SC. When a seek 
has been initiated by a command, it will pause until 
the seek is completed. 

Bit 3 - Data Request 

This bit reflects the state of the BDRQ. It is set when 
the sector buffer should be loaded with data or read 
by the host, depending upon the command. 
DRQ/BDRQ remains high until BRDY is sensed, 
indicating the operation is completed. The BRDQ 
signal can be used in DIVIA interfacing or Programmed 
I/O, while the DRQ bit can be used only for pro- 
grammed I/O transfers. 

Bit 2 - Reserved 

Not used. This bit is always forced to a zero. 

Bit 1 - Command In Progress 

When this bit is set, a command is being executed 
and a new command should not be loaded until reset. 
Although a command may be executing, the sector 
buffer is still available for access by the host. When 
the WD1010 is not busy (bit 7 = 0) the status register 
may be read. If other registers are read while CIP, the 
status register contents are returned. 

Bit - Error 

This bit indicates that a non-recoverable error has 
occurred. When the Host reads the status and finds 
this bit set, it must then read the Error Register to 
determine the type of error. This bit is reset when a 
new command is written into the command register. 



COMMAND REGISTER 

This write-only register is loaded with desired 
command: 

7 6 5 4 3 2 10 



C O IVI M A N D 



The command begins to execute immediately upon 
loading. This register should not be loaded while the 
Busy or CIP bits are set in the status register. The 
INTRQ, if set, will be cleared by a write to the com- 
mand register. 

INSTRUCTION SET 

The WD1010 will execute six commands. Prior to 
loading the command register, the host must first set 
up the task file with the proper information needed 
for the command. Except for the command byte, the 
other registers may be loaded in any order. Any subse- 
quent writes to the command register will be ignored 
until execution is completed indicated by the reset- 
ting of the CIP bit in the status register. 

COMMAND SUMMARY 



COMMAND 


7 


6 


5 


4 3 2 10 


RESTORE 











1 R3 R2 Ri Rq 


SEEK 





1 


1 


1 R3 R2 Ri Rq 


READ SECTOR 








1 


1 M T 


WRITE SECTOR 








1 


1 M T 


SCAN ID 





1 





T 


WRITE FORMAT 





1 





10 



R3-R0 Rate Field 


For 5 MHz WCLK: 


R3-R0 = 0000 


35 fiS. 


0001 


.5 ms. 


0010 


1.0 ms. 


0011 


1.5 ms. 


0100 


2.0 ms. 


0101 


2.5 ms. 


0110 


3.0 ms. 


0111 


3.5 ms. 


1000 


4.0 ms. 


1001 


4.5 ms. 


1010 


5.0 ms. 


1011 


5.5 ms. 


1100 


6.0 ms. 


1101 


6.5 ms. 


1110 


7.0 ms. 


1111 


7.5 ms. 



Bit 0, ("T") Read Sector, Write Sector Commands 
T = Enable retries 
T = 1 Disable retries 

M = Multiple Sector Flag 

M = Transfer 1 sector 

M = 1 Transfer multiple sectors 

I = Interrupt Enable 

I = Interrupt at BDRQ time 

I = 1 Interrupt at end of command 



3-10 



Winchester Disk Controller Devices 



c 



J 



RESET INTRQ, 

ERRORS, 
SET BUSY, CIP 



RESET RWC 

SET DIRECTION 

= OUT 

STORE STEP RATE 




PULSE BCR 
SET AC, INTRQ 
RESET BSY, CIP 



3 



SET 
TKOOO ERROR 



ISSUE A 
STEP PULSE 



c 



PULSE BCR 

SET INTRQ 

RESET BSY, CIP 



D 



RESTORE COMMAND 

The restore command is usually used on a power-up 
condition. The actual stepping rate used for the 
restore is determined by Seek Complete time. A step 
pulse is issued and the WD1010-05 waits for a rising 
edge on the seek complete line before issuing the 
next pulse. If 10 index pulses are received with- 



out a rising edge of seek complete, the WD1010 will 
switch to sensing the level of the SC line. If after 1,024 
stepping pulses, the TKOOO lines do not go active, the 
WD1010-05 will set the Track Zero error bit in the error 
register and terminate with an INTRQ. An interrupt 
will also occur if the write fault goes active or the 
DRDY goes inactive during execution. 

The rate field specified (R3-R0) is stored in an inter- 
nal register for future use in commands with implied 
seeks. 

SEEK COMMAND 

Since except for the SCAN ID all commands feature 
an implied seek, the seek command is primarily used 
for overlap seek operations on multiple drives. The 
actual step rate used is taken from the rate field, 
which is also stored in an internal register for future 
use. If DRDY goes inactive or WF goes active, the 
command is terminated and an INTRQ is generated. 

The direction and number of step pulses needed are 
calculated by comparing the contents of the cylinder 
register high/low to the cylinder position number 
stored internally. After all steps have been issued, the 
internal cylinder position register is updated and the 
command is terminated. Seek complete is not 
checked at the beginning or end of the command. 

If an implied seek was performed, the WD1010^5 will 
wait until a rising edge of SC is received. If 10 revolu- 
tions occur before the rising edge of SC, the WD1010 
will switch to level sensing of SC. 

READ SECTOR 

The read sector command is used to transfer one or 
more sectors of data from the disk to the sector buf- 
fer. Upon receipt of this command, the WD1010-05 
checks the cylinder registers against its internal cyl- 
inder position register to see if they are the same. If 
not, the direction and number of steps calculation is 
performed and seek takes place. If an implied seek 
was performed, the WD1010^5 will search until a ris- 
ing edge of seek complete is received. Write Fault and 
DRDY lines are checked throughout the command. 

After seek complete is found to be true (with or 
without an implied seek), the search for an ID field 
occurs. The WD1010-05 must find an ID with the cor- 
rect cylinder, head, sector size, and CRC within 10 
revolutions if T bit of command is zero, and within 
2 revolutions if T = 1; else the appropriate error bits 
will be set and the command terminated if T = 1. 
Both the Read and Write sector commands feature 
a "simulated completion" to ease programming. 
DRQ/BDRQ will be generated upon detecting an error 
condition. This allows the same program flow for suc- 
cessful or unsuccessful completion of a command. 
If T = 0, an automatic scan ID is performed to obtain 
cylinder position information and then, if necessary, 
a seek is performed. The search for the correct ID field 
is continued for 10 more disk rotations. 



D 

o 
o 

I 

o 



Winchester Disk Controller Devices 



3-11 



o 

o 
o 

o 

en 



c 



SEEK 



3 



RESET INTRO, 

ERRORS, 

SET BUSY, CIP 

STORE STEP RATE 



YES 



SCAN ID 
GET CYL # 



SET 
DIRECTION 



CALCULATE 
# OF STEPS 





NO 


«• 




ISSUE STEP 
PULSE 




' 






DELAY 

ACCORDING TO 

RATE FIELD 




^^ STEPS ^^ 
^N^ ISSUED ^y^ 


NO 






3-12 



Winchester Disk Controiier Devices 



READ SECTOR 




*lf T bit of command = 1 then dashed path is tai^en after 2 index pulses. 



Winchester Disk Controller Devices 



3-13 




SET BAD 
BLOCK BIT 



DEACTIVATE BCS 

PULSE BCR 

RESET BSY, CIP 

SET INTRQ 



DEACTIVATE BCS 
PULSE SCR 




INCREMENT SECTOR # 

DECREMENT SECTOR 

COUNT 



YES 



SET 
INTRQ 




DEACTIVATE BC5 
PULSE BCR 



RESET BDRQ 
PULSE BCR 
SET INTRQ 
RESET CIP 




o 



SET CRC 
ERROR 



SET DAM 
NOT FOUND 




YES 



RESET BDRQ 



*lfT bit of command = 1 then dashed path is taken. 
'*lf T bit of command = 1 then test is for 2 index pulses. 



3-14 



Winchester Disk Controller Devices 



When the data address mark is found, the WD1010-05 
is ready to transfer data to the buffer. After the sec- 
tor data has been transferred, the I flag is checked. 
If the I flag is 0, the INTRQ is made active coincident 
with BDRQ, indicating a transfer of data is required 
by the host. If I = 1, the INTRQ will occur at the end 
of the command (i.e., after the buffer is unloaded by 
the host). 

An optional M flag may be set for multiple sector 
transfers. When M = 0, one sector is transferred and 
the sector count register is ignored. When M = 1, 
multiple sectors are enabled. After each sector is 
transferred, the WD1010-05 decrements the sector 
count register and increments the sector number 

When M = (Single Sector Read) 



register. The next logical sector will be transferred, 
regardless of the interleave. Sectors are numbered 
at format time by a byte in the ID field. 

For the WD1010 to make multiple sector transfers to 
the buffer, the BRDY line must be toggled low to high 
for each sector. The sector transfers will continue 
until the sector count register equals zero. If the sec- 
tor count register is non-zero (indicating more sec- 
tors are to be transferred but the buffer is full), BDRQ 
will be made active and the host must unload the buf- 
fer. Once this occurs, the buffer will again be free to 
accept the next sector in this multiple sector read 
command. 



(1) 


Host 


Sets up parameters; issues read sector command. 


(2) 


1010: 


Strobes BCR; sets BCS = (On). 


(3) 


1010: 


Finds sector specified; transfers data to buffer (by WE strobes). 


(4) 


1010: 


Strobes BCR; sets BCS = 1 (Off). 


(5) 


1010: 


Sets BDRQ = 1; sets DRQ flag. 


(6) 


1010: 


If 1 bit = 1 then (9). 


(7) 


Host 


Reads out contents of buffer (by strobing RE). 


(8) 


1010: 


Waits for BRDY then sets INTRQ = 1; End. 


(9) 


1010: 


Sets INTRQ = 1. 


(10) 


Host 


Reads out contents of buffer (by strobing RE); End. 



When M = 1 (Multiple Sector Read) 



(1) 


Host: 


Sets up parameters; issues read sector command. 


(2) 


1010: 


Strobes BCR; sets BCS = (On). 


(3) 


1010: 


Finds sector specified; transfers data to buffer (by WE strobes). 


(4) 


1010: 


Decrements sector count reqister; increments sector number reqister. 


(5) 


1010: 


Strobes BCR; sets BCS = 1 (Off). 


(6) 


1010: 


Sets BDRQ = 1; DRQ flag = 1. 


(7) 


Host: 


Reads out content of buffer (by RE strobes). 


(8) 


Buffer: 


Indicates data has been transferred by asserting BRDY. 


(9) 


1010: 


When BRDY is asserted, go to (11) if sector count = 0. 


(10) 


1010: 


Go to Step (2). 


(11) 


1010: 


Activates INTRQ. 



WRITE SECTOR 

The write sector command is used to write one or 
more sectors of data to the disk. Upon receipt of this 
command, the WD1010-05 checks the cylinder 
registers against its internal cylinder position register 
to see if they are the same. If not, the direction and 
number of steps are calculated and a seek command 
takes place. Write fault and DRDY lines are checked 
throughout the command. 

After Seek complete is found to be true (with or 
without an implied seek), the BDRQ signal is made 
active and the host proceeds to load the buffer. When 
the WD1010-05 senses the BRDY line going high, the 
ID field with the specified cylinder, head, and sector 
size is searched for. Once found, the write gate signal 
is raised and the data is written to the disk. It is 
necessary to resynchronize the write data due to the 



fact that a bit cell can extend from 295ns to 315ns 
during a write cycle. If retries are disabled and if the 
ID field cannot be found within 2 revolutions, the ID 
not found bit is set and the command is terminated. 

If retries are enabled, and the ID field cannot be found 
within 10 revolutions, an automatic scan ID and seek 
commands are performed. The ID Not Found error bit 
is set if the ID field is not found after 10 more 
revolutions. 

During a multiple sector write operation (M flag = 
1), the sector number is incremented and the sector 
count register is decremented. If the BRDY lines is 
asserted after the first sector is read out of the buf- 
fer, the WD1010-05 will continue to read data out of 
the buffer for the next sector. If BRDY is inactive, the 
WD1010-05 will raise BRDQ and wait for the host to 
place more data in the buffer. 



o 



Winchester Disk Controller Devices 



3-15 






o 

CJl 



f WRITE SECTOR j 



RESET INTRQ, 
ERRORS, DRQ 
SET BSY, CIP 



YES 




SCAN ID 
GET CYL # 



G> 



DRIVE # 
^CHANGED 



NO 





ACTIVATE BDRQ, 
DRQ 



BRDY 
ACTIVE 




YES 



RESET BDRQ 



ACTIVATE BCS 
PULSE BCR 




■o 



WRITE DATA 

TO SECTOR 

THEN DEASSERT WG 








PULSE BCR > 

SET ID NOT FOUND 
INTRQ, RESET BSY, CIP 
DEACTIVATE BC5 > 



INCREMENT SECTOR 

NUMBER; DECREMENT 

SECTOR COUNT 




■HDEACTIVATE BCS 

PULSE BCR 
SET INTRQ; RESET 
V BUSY, CIP 



DEACTIVATE BCS 

PULSE BCR 
ACTIVATE BDRQ 




SET ABORTED 

COMMAND 

BIT 



Mf retries disabled then dashed path is 
tal<en after2 index pulses. 



PULSE BCR 

SET INTRQ 

RESET BSY, CIP 

DEACTIVATE BCS 



3-16 



Winchester Disk Controller Devices 



In summary then, the write sector operation is as follows: 



(1) 


Host: 


Sets up parameters; issues write sector command. 


(2) 


1010: 


Sets BDRQ = 1. DRQ flag = 1. 


(3) 


Host: 


Loads buffer with data (by WE strobes). 


(4) 


1010: 


Waits for BRDY = low to high. 


(5) 


1010: 


Finds specified ID field, write out sector. 


(6) 


1010: 


If M = 0, then interrupt; End. 


(7) 


1010: 


Increments sector number, decrements sector count. 


(8) 


1010: 


If sector count = 0, then interrupt; End. 


(9) 


1010: 


Go to (2). 



SCAN ID 

The scan ID command is used to update the head, 
sector size, sector number and cylinder registers. 

The ready and write fault lines are checked 
throughout the command. When the first ID field is 
encountered, the ID information is loaded into the 
SDH, cylinder, and sector number registers. The inter- 
nal cylinder position register is also updated. If a bad 
block is detected, the bad block bit will also be set. 
CRC is checked and if an error is found, the 
WD1010-05 will retry up to 10 revolutions to find an 
error-free ID field. There is no implied seek with this 
command and the buffer is left undisturbed. 

FORMAT 

The format command is used to format one track 
using the task file and the sector buffer. During this 
command, the sector buffer is used for additional 
parameter information instead of sector data. Shown 
in Figure 7 is the contents of the sector buffer for a 
32 sector track format with an interleave factor of two. 
Each sector requires a two byte sequence. The first 
byte designates whether a bad block mark is to be 
recorded in the sector's ID field. A 00 is normal; an 
80 hex indicates a bad block mark for that sector. In 
the example of Figure 7, sector 04 will get a bad block 
mark recorded. 

The second byte indicates the logical sector number 
to be recorded. Using this scheme, sectors may be 



recorded in any interleave factor desired. The remain- 
ing memory in the sector buffer may be filled with 
any value; its purpose is only to generate a BRDY to 
tell the WD1010-05 to begin formatting the track. 

An implied seek is also in effect on this command. 
As in other commands, if the drive number has 
changed, an ID field will be scanned for cylinder posi- 
tion information before the implied seek is performed. 
If no ID field can be read (because the track had been 
erased or because an incompatible format had been 
used), an IDNF error will result and the Format com- 
mand will be aborted. This can be avoided by issu- 
ing a Restore command before formatting. 

The sector count register is used to hold the total 
number of sectors to be formatted, while the sector 
number register holds the number of bytes minus 3 
to be used for Gap 1 and Gap 3. For instance, if the 
sector count register value is 2 and the sector number 
register value is 0, then 2 sectors are written and 3 
bytes of 4E hex are written for Gap 1 and Gap 3. The 
data fields are filled with FF hex, and CRC is 
automatically generated and appended. The sector 
extension bit of the SDH register should not be set. 
After the last sector is written, 4E hex is filled until 
index. 

The Gap 3 value is determined by the drive motor 
speed variation, data sector length, and the interleave 
factor. The interleave factor is only important when 
1:1 interleave is used. The formula for determining 











DATA 








ADDR 





1 


2 


3 4 


5 


6 


7 


00 


00 


00 


00 


10 00 


01 


00 


11 


08 


00 


02 


00 


12 00 


03 


00 


13 


10 


80 


04 


00 


14 00 


05 


00 


15 


18 


00 


06 


00 


16 00 


07 


00 


17 


20 


00 


08 


00 


18 00 


09 


00 


19 


28 


00 


OA 


00 


1A 00 


OB 


00 


IB 


30 


00 


OC 


00 


1C 00 


OD 


00 


ID 


38 


00 


OE 


00 


IE 00 


OF 


00 


IF 


40 


FF 


FF 


FF 


FF FF 


FF 


FF 


FF 


FO 


FF 


FF 


FF 


FF FF 


FF 


FF 


FF 



o 

o 
o 
o 

01 



FIGURE 7. 
FORMAT COMMAND BUFFER CONTENTS 



Winchester Disk Controller Devices 



3-17 



o 
en 



the minimum Gap 3 value is: 

Gap 3 = 2*M*S + K + E 

M = motor speed variation (e.g., .03 for ± 3%) 

S = sector length in bytes 

K = 25 for interleave factor of 1 

K = for any other interleave factor 

E = 7 if the sector is to be extended 

Like all commands, a write fault or not ready condi- 
tion will terminate the command. Figure 8 shows the 
format that the WD1010-05 will write on the Disk. 



( SCAN ID ) 



RESET INTRO, 

ERRORS 
SET CIP, BSY 




/^ SET INTRO, AC ^ 
^ RESET BSY, CIP J 



SEARCH FOR 
ANY ID FIELD 




UPDATE SDH, 

CYL, SECTOR, 

CYL POS. REG'S 




PULSE BCR 
SET ERROR, INTRO 
RESET BSY, CIP 




BAD 
BLOCK 
DETECT 



YES 



SET BAD BLOCK BIT 



CRC 
ERROR 




YES 



NO 



(PULSE BCR \ 

SET INTRO I 

RESET BSY, CIP ^ 



'If retries are disabled, path 
is taken after 2 index pulses. 







> 




s 




A1= A1 hex with OA hex clock HEAD= BitsO, 1,2 = Head Number A1 = A1 hex with OA hex Clock 

IDENT= 2 LS.B. = Cylinder High Sl^M^S , o- F8= Data Address Mark; Nomial Clock 

^p:^1i%Se. Bir/^BlclSt;^. USER= Da,aH»,<1128.o1024By.es 

FC = 512-767 Cylinders Sec #= Logical Sector Number NOTES: 

FD = 768-1023 Cylinders • GAP1 and 3 length detemnined by sector number 

register contents during formatting. 
• If EXT bit in SDH register is set to 1 then an additional 

7 data bytes are written, no CRC bytes are written. 






CO 

a. w 

O 






^° 
m 

n 








c 




CJOCOcvJ 


O 
_l 
UJ 

u. 

§ 

o 


ooco'- 


Q 
EC 
UJ 

w 

3 


o 

LU 


u. CO 


<y- 


X 

o 

a. 
o 
u. 

Q 
m 

tu 


C/J 
UJ 

Si 

CM 


CO 
UJ 

m 
n 


Ul 

a 

UJ 

1- 
cc 
5 




■c 

L 
U 

c 




O CO CM 


otro'- 


CO UJ U « 


XUJ<Q 


-■OS 
b>-' 


— QUJZI- 


<^ 






UJ 


1 — 






X 

LU 

a 

z 


> 




'v 




_l 

UJ 

E 

2 



FIGURE 8. 
FORMAT 



3-18 



Winchester Disk Controller Devices 








YES 


^y^ DRIVE # ^^ 


1 






V^^HANGED ^y^ 


SCAN ID 
GET CYL # 




NO 


' 








' 




SEEK TO 
DESIRED CYL 




STROBE BCR_ 
ACTIVATE BCS 





WRITE 
SECTOR 



WRITE 4E'S 
UNTIL INDEX 





g 

o 
o 
o 



^y^ SEEK ^\ 

V^ COMPLETE = ^^ 


rES 


EXTEND 
GAP 


^\ 


NO 


" 


" 








DECREMENT 
SECTOR COUNT 





PULSE BCR 

SET INTRO 

RESET BSY. CIP 

DEACTIVATE BCS 



3 



SET WG ON 



YES 



SET ABORTED 
COMMAND BIT 



RESET WG. BCS 
PULSE BCR 
SET INTRO 

RESET BSY, CIP 




NO 



WF 



o 



Winchester Disk Controller Devices 



3-19 



o 

o 
o 

o 

01 



ELECTRICAL CHARACTERISTICS 

MAXIMUM RATINGS 

Vcc with respect to Vgs (Ground) + 7V 

Max Voltage on any Pin with 

respect to Vss -0.5V to + 7.0V 

Operating Temperature 0°C to 70°C 

Storage Temperature -55°C to +125°C 

DC Operating Characteristics Ta = 0°C to 70°C; Vgs 



NOTE: IVIaximum ratings indicate operation where 
permanent device damage may occur. Continuous 
operations at these limits is not intended and should 
be limited to those conditions specified in the DC 
operating characteristics. 



OV, Vcc = + 5V ± .25V 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


UNITS 


CONDITIONS 


l|L 


Input Leakage 




±10 


mA 


V,N = -4 to Vcc 


loL 


Output Leakage (Tristate & Open 












Drain) 




±10 


mA 


Vqut = -4 to Vcc 


V|H 


Input High Voltage 


2.0 




V 




V|L 


Input Low Voltage 




0.8 


V 




Vqh 


Output High Voltage 


2.4 




V 


10 = - lOO^A 


Vol 


Output Low Voltage 




0.4 


V 


10 = 1.6mA 


Vol 


Output Low Voltage(Pins 21-23) 




0.45 


V 


10 = 4.8mA See Note 10 


'go 


Supply Current 
For Pins 25, 34, 39: 




200 


mA 


All Outputs Open 


V,H 


Input High Voltage 


4.6 




V 




V|L 


Input Low Voltage 




0.5 


V 




TRS 


Rise and Fall Time 




30 


nsec 


.9V to 4.2V points 


C|N 


Input Capacitance 




15 


PF 





AC Timing Characteristics T^ = 0°C to 50°C; Vss = OV, Vcc = +5V ±.25V 



ADDR 



OS 



DBO-7 



X 



n: 



-Tase- 

-TCSE- 



Ao,Ai,A2 STABLE 



X 






Thld' 



J^ 



Trdr" 



^;: 



-Tre- 



yn 



■Tdac-H ' ; 

<;^ data valid ^^ 



tdoh 



HOST READ TIMING 



HOST READ TIMING WD1010-05 WC = 5 MHZ 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


UNITS 


CONDITION 


Tase 


ADDR Setup to RE 


100 




nsec 




Tdac 


Data Valid from RE 




375 


nsec 




Tre 


Read Enable Pulse Width 


.4 


10 


f^sec 




Tdoh 


Data Hold from RE 


20 


200 


nsec 




Thld 


ADDR, OS, Hold from RE 







nsec 




Trdr 


Read Recovery Time 


300 




nsec 




Tqse 


OS Setup to RE 







nsec 


See Note 8 



3-20 



Winchester Disk Controlier Devices 



X 



Ao,Ai,A2 STABLE 



X 



Tahw 



TSEW- 



ru^ 



■TwER" 



-•i '♦-TCHW 



> 



•TWE 



. Tps- 






r^—ToH 



oBo. XXXXXXX^?^?X°---""3tbevauo 3 x 3^^^ 



o 

o 
o 
o 



HOST WRITE TIMING 



HOST WRITING TIMING WD1010-05 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


UNITS 


CONDITION 


TsEW 


ADDR, CS Setup to WE 





10 


fisec 




Tds 


Data Bus Setup to WE 


.2 


10 


Msec 




TwE 


Write Enable Pulse Width 


.2 


10 


/^sec 




Tdh 


Data Bus Hold from WE 


10 




nsec 




Tahw 


ADDR Hold from WE 


30 




nsec 




Twer 


Write Recovery Time 


1.0 




Msec 


See Note 1 


TcHw 


CS Hold Time from WE 









See Note 9 



-Ih 



RE 

(OUTPUT) 



•> 



I i-^-Trds-^-I I I 



\ 



X 



Hh 




■Thre 



DBO-7 



\/\/\/\/\/W\> DATA MUST V\/\/\/ VK/ DATA MUST V/^J K/\/\/ 
/\/\y\/\y\/^/\ BEVALID /\y\y\y\/^A BEVALID X ^j j/VX A 



Trr 

BUFFER READ TIMING 



BUFFER READ TIMING (WRITE SECTOR CMD) WD1010-05 WC = 5MHZ 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


Trev 


RE Float to RE Valid 


15 




100 


nsec 


Cl= 50 pf 


Treb 


RE Output Pulse Width 


300 


400 


500 


nsec 


See Note 4 


Trds 


Data Setup to RE 


140 






nsec 




Trr 


RE Repetition Rate 


1.2 


1.6 


2.0 


fisec 




Trf 


RE Float from BCS 






100 


nsec 


Cl = 50 pf 


Thre 


Data Hold from RE 









nsec 





Winchester Disk Controller Devices 



3-21 



"X 



TWEV 



WE 

(OUTPUT) 



^>r 



\ ti»-TwRB— »g /r7 



'''VWE-W '.*- 



DBO-7 



< 



DATA VALID 



(^-Thwe 



'^di; 



■TWF 



-/^ DATA VALID \— -J L 



•Trr- 



BUFFER WRITE TIMING 



BUFFER WRITE TIMING (READ SECTOR CMD) WD1010-05 WC = 5 MHZ 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


TwEv 


WE Float to WE Valid 


15 




100 


nsec 


Cl = 50 pf 


"•"WRB 


WE Output Pulse Width 


300 


400 


500 


nsec 


See Note 4 


TvwE 


Data Valid from WE 






150 


nsec 




Thwe 


Data Hold from WE 


60 






nsec 




Trr 


WE Repetition Rate 


1.2 


1.6 


2.0 


Msec 


See Note 2 


TwF 


WE Float from BCS 


15 




100 


nsec 


Cl = 50 pf 



u— tbd— ! 


/ 


.0^ \ /r \ 


nRMN 


^y \ 


\ Torn / 



READ DATA TIMING 
READ DATA TIMING WD1010-05 WC = 5 MHZ 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


Trcp 


RCLK Pulse Width 


95 




2000 


nsec 


50% Duty Cycle 


Txi 


RD from RCLK Transition 







Trop 


nsec 




Tx2 


RD to RCLK Transition 


20 




Trcp 


nsec 




Trd 


RD Pulse Width 


40 




Trcp 


nsec 




Torn 


DRUN Pulse Width 


30 






nsec 




Trcf 


RCLK Frequency 


.250 




5.25 


MHz 


See Note 6 



3-22 



Winchester Disk Controller Devices 



BRDY 
BDRQ 



A 



•Tbry ' 



' I 



N^ ,., Tbcr ^ 

^^♦*^*— TSTP— ^ 



yf^*— T|DX » H 



MISCELLANEOUS TIMING 



^ 



C5,WE 
MR 








\ / 

1 

il5zi=:7J^TMRw»J 


\=^ 


WCLK - 
RCLK- 




1 


-/ 


l" 


1 

I^RC ►] 

S TIMING 


1 

r* 

MISCELLANEOU 



o 
o 
o 

o 
en 



MISCELLANEOUS TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


Trq 


BDRQ Reset from BRDY 


40 




200 


nsec 




Tbcr 


Buffer Counter Reset Pulse 
Width 


1.4 


1.6 


1.8 


^sec 


See Note 2 


TsTP 


Step Pulse Width 


8.3 


8.4 


8.7 


Msec 


See Note 2 


TlDX 


Index Pulse Width 


500 






nsec 




Tmr 


Master Reset Pulse Width 


24 






WC 


See Note 3 


Fwc(-05) 


Write Clock Frequency 


.25 


5.0 


5.25 


MHz 


50% Duty Cycle 


Frc(-05) 


Read Clock Frequency 


.25 


5.0 


5.25 


MHz 


See Note 6 


Tbry 


BRDY Pulse Width 


800 






nsec 


See Note 5 


Tmrb 


MR Trailing to BCR 


1.6 


3.2 


6.4 


;.<sec 


See Note 2 


Tmrw 


MR Trailing to Host Write 


6.4 






fisec 


See Note 2 



NOTES: 

1. AC timing measured at Vqh = 2.0V, Vql - 0.8V, 
Cl= 50 pf. 

2. Based on WCLK = 5.0 MHz. 

3. 24 WCLK periods (4.8 Msec at 5.0 MHz). 

4. 2 WCLK ± 100 nsec. 

5. To drive a DMA controller, BRDY must be >4 /^sec 
or a spurious BDRQ pulse may exist for up to 4 
Msec after rising edge of BRDY. 



6. Trcf = TwcF ±15%. 

7. 2WCLK ± 50 nsec. 

8. RE may precede CS if CS plus RE meets the 
TRE width. , 

9. WE may precede CS If CS plus WE meets 
the TWE width. 

10. Pins 21-23 should be loaded with a IK pull-up 
resistor. 



Winchester Disk Controller Devices 



3-23 



1 












^ 


TwD-»^ l^r- 




Two i 

1 

1 


H- 




o 
o 
o 




r~ 


~^ 


o 


WCLK /] -t ^1 


\ 


1 
__ 1 

— »J 1^ — TwLE 

1 
1 
1 


-^ r* — ^ELw 
1 1 

1 
1 




..^ / 






EARLY 




X 


T 



WRITE DATA TIMING 
WRITE DATA TIMING WD1010-05 WC = 5 MHZ 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


Twc 


WCLK Pulse Width 


95 




2000 


nsec 




TwD 


Propagation Delay WCLK 
to WD 


10 




65 


nsec 




TwLE 


WCLK to Leading Early/Late 


10 




65 


nsec 




Telw 


WCLK to Trailing Early/Late 


10 




65 


nsec 




TwcF 


WCLK Frequency 


.250 




5.25 


MHz 


See Note 6 



3-24 



Winchester Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD1010 Application Notes 



o 



FLEXIBLE CONTROLLER MATES WITH POPULAR 
WINCHESTER DRIVES 

To take advantage of the growing demand for Seagate 
Technology-type 5 1/4-in. Winchester disl< drives in 
personal computers, electronic work stations, and 
small-business systems, designers need an 
appropriate controller that is inexpensive. In fact, 
today's designs must implement the control link bet- 
ween a Host CPU and a disk drive at far lower cost 
than the drive itself. That requires a single-chip con- 
troller rather than discrete, gate-array-intensive cir- 
cuits that take up valuable board space in ever 
smaller computer equipment. 

Such a device is now available in the form of an LSI 
single-chip Winchester controller-formatter. The chip 
incorporates 80% of the circuitry required for Win- 
chester control, eliminating between 50 and 75 SSI 
and MSI devices used in earlier designs. 

A controller that claims Seagate compatibility must 
be sufficiently flexible to meet not only the company's 
original ST506 specifications, but also the various 
deviations from them. The basic specifications 
include a data rate of 5.0 Mbits/s and open-collector 
outputs and differential signal inputs for the separate 
control and data interface cables. The recording for- 
mat is modified frequency modulation (MFM), but 
more importantly, the structure of the format defines 
both specific address-mark bytes and ID fields. These 
are fixed specifications, but manufacturers of 
Seagate-type drives sometimes make other changes. 
For example, the track density on high-capacity drives 
may be greater than that in the original ST506 
specification. Also, the number of sectors and bytes 
per sector on each cylinder can vary according to the 
application. In each case, a compatible controller 
must be able to handle the original specifications plus 
the deviations. 

The ST506 interface is a spinoff of the Shugart 
Associates SA1000 drive, first introduced in 1979. Two 
important differences between the interfaces are the 
data rates and a timing-clock differential signal on 
the SA1000. The latter operates at 4.34 Mbits/s vs 5 
Mbits/s for the ST506, but the remaining signals have 
enough similarity to permit a single controller design 
to run either an 8-in. SA1000 drive or the 5 1/4-in. ST506 
drive. The advantage of the WD1010 Winchester 
controller-formatter is that it works with either and 
with other manufacturers' variations as well. 

Operation of the drive begins when a Host processor 
initiates a command after first loading a set of inter- 
nal task registers called the task file. Information such 



as cylinder, sector, and head number is written to 
these registers, which are selected by address lines. 
The memory-mapped register scheme allows 
individual accesses to each register. Thus, the Host 
need not waste valuable time reading all the registers 
to obtain a specific parameter. 

The WD1010, which comes in a 40-pin DIP or 44-pin 
QSM, is run by an internal microcontroller - a PLA 
(programmable logic array) serving as a state machine 
(Fig. 1). This logic controls the flow of data throughout 
the chip, recognizes and processes commands, and 
formats the data. 

WRITING AND READING DATA 

During a write operation, parallel data is read from 
the data bus and written to a specific sector. But first 
the cylinder and sector must be located on the 
requested disk drive. The WDIOIO's microcontroller 
accesses its internal cylinder-position data and com- 
pares it with the requested cylinder number. If 
necessary, a seek is performed automatically to posi- 
tion the head assembly over the desired cylinder. 

If the drive requested is changed before a Seek Com- 
mand is executed, the WD1010 enables its read logic 
and searches for an ID field on the currently selected 
drive. Then it reads the cylinder number for the new 
ID field and determines whether to seek in or out to 
find the requested cylinder. This so-called implied 
seek is a feature of all commands (see "Macro Com- 
mands Provide Multiple Options"). 

After the WD1010 finds an ID field that matches the 
cylinder, head, sector, sector size and CRC (cyclic 
redundancy check) value, it writes a field of Os and 
a new address mark - later these two fields will be 
used for synchronization during a read operation. The 
chip then reads parallel data in from the data bus, 
serializes it, and converts it into the MFM format. 
Next, a new CRC value is calculated for the incom- 
ing data and is appended to the data field (after the 
last byte). If the original command specifies multiple 
sectors, the next logical sector must be searched for 
and the process repeated. After the last sector is writ- 
ten, the WD1010 gives the bus back to the Host and 
waits for the next command. 

Although the chip does not generate an error correc- 
tion signal, an optional command bit can be set to 
disable cyclic redundancy checks of the data field. 
The sector is extended by seven bytes to allow the 
Host to write its 56-bit error detection and correction 
code. Later, during a read operation, these seven 
bytes are transferred back to the Host to permit it to 
identify a syndrome and correct any errors that were 
encountered. For systems that require such opera- 
tions, the WD1014 error detection and correction and 



Winchester Disk Controller Devices 



3-25 



D 

O 
O 



WD1015 buffer controller chips are available. 

Reading is similar to writing except ttiat data is sent 
out on the data bus and written Into the sector 



buffer at the Host. MFM data is entered on the RD 
pin along with a synchronous clock (RCLK) generated 
from an external data separator (Figure 2). 



Do-D?/- 



1/0 BUFFERS 



RE- 



WE 

A2A0T<- 

IRQ 

MR 

C§— I 



Tt 



DATA REGISTER 



STATUS REGISTER 



HOST 
INTERFACE 



MAGNITUDE 
COMPARATOR 



BCR — 
BRDY 
BDRQ 

bCs— 

vcc- 
vss- 



BUFFER 
INTERFACE 



MICROCONTROLLER 
(PLA) 



c 



U SYNC 
GENERATOR 



PARALLEL-TO- 
SERIAL 
CONVERTER 



SERIAL-TO- 
PARALLEL 
CONVERTER 



uT 



MFM 
ENCODER 



WD 
WCLK 



uV 



MFM 
DECODER 



SYNCHRONIZER 



>*c 



AM DETECTOR 



DRIVE 
INTERFACE 



PHASE-LOCKED 
LOOP INTERFACE 



STEP 
-DIRC 
• EARLY 
■LATE 

DRDY 

WF 

TKOOO 

INDEX 

SC 

■ RWC 

■ WG 
- RG 

DRUN 



Figure 1. 



The architecture of the WD1010 Winchester controller-formatter chip is designed to reduce a Host processor's 
overhead burden. An internal microcontroller (PLA) manages data flow, incoming commands, and formatting. 



Since the data rate is relatively high, the data 
separator must instruct the controller to lock on to 
the incoming data stream only during a field of 1s 
and Os. A Data Run (DRUN) signal to the WD1010 
indicates such an occurrence. When DRUN is active, 
the WD1010 counts off 16 bits - 2 byte time - sets 
the Read Gate (RG) signal, and starts to search the 
data stream for an address mark. 



IMPLEMENTING THE 
PRECOMPENSATION ALGORITHM 


ALREADY 
SENT 


SENDING 


TO BE 
SENT 


SHIFT 
REQUIRED 


X 


1 


1 





Early 


X 





1 


1 


Late 











1 


Early 


1 











Late 



NOTE: All other patterns produce no shift. 



WD1012 WRITE 

PRECOMPENSATION 

DEVICE 



€ 



JT 



TO WD101 
DATA SEPARATOR 



,ir 



MFD 



1SH 
RG 
WC 



X2 
TANK 



TA 



ERR 
RCLK 
DATA DDATA 



1 "WS I 



IN" OUT 

60NS 
DELAY LINE 



DRUN 

RG 

WCLK 

WD1010 



Figure 2. 

A separate IC - the WD1012 - performs the data 
separation for the WD1010. The data separator sends 
a DRUN signal to the controller when it encounters 
a data field (Is and Os). 



3-26 



Winchester Disk Controller Devices 



An address mark is a unique pattern of clocl< and data 
bits that does not appear in any piace that normal 
MFM data appears. If an address mark is not detected 
within nine bytes or if a non-0 pattern is detected 
within nine bytes, RG is turned off and the search is 
repeated. Since the data fields within sectors can con- 
tain Os or all Is, the DRUN algorithm is also triggered 
in these cases. But the address mark will not be 
detected, preventing erroneous data from being 
transferred. 

After the ID field is compared and verified, a search 
begins for the address mark. Resynchronization 
occurs and the data is transferred to an intemal MFM- 
to-NRZ converter. Data is then shifted through a 
double-buffered shift register and placed on the data 
bus for loading to the buffer. Either the cyclic redun- 
dancy code at the end of the data field is checked 
or the error detection and correction bytes are 
transferred in parallel to the host, depending on which 
option is used. Then the host processor can read the 
data from its local buffer. 

Like all magnetic recording media, Winchester disks 
are not immune to the effects of bit shifts at high 
recording densities. The WD1010 uses an algorithm 
that informs external delay circuits when to shift out- 
going data. A register within the task file specifies 
which cylinder receives reduced write current and if 
precompensation is needed. Typically, both occur on 
the same cylinder about half way down the disk 
surface. 

The W D1 010's precompensation signals are called 
Early and Late. Depending on the bit pattern leaving 
the device, data will be shifted early, late, or not at 
all. The WD1011 data separator implements the 
precompensation delay network (Figure 2). 



Since the Early signal and the current data (or 
clock) bits leaving the WD1010 have already occur- 
red. the WD1 011 p erfo rms no delay function on 
Early. If both Early and Late are in activ e, the 
WD1011 inserts a 12-ns delay; if only Late is ac- 
tive, it inserts a 24-ns delay. The result is a ± 12-ns 
shift of the data from its nominal position. An inac- 
tive Reduced Write Current (RWC) signal from the 
WD1010 disables the WD1011. The WD1010 then fur- 
nishes precompensation signals independent of cur- 
rent cylinder position. 

INTERFACING WITH CABLES AND BUSES 

The remaining function on the drive side is to pro- 
vide sufficient buffers to drive the cables between the 
chip and the interface connectors. Single-ended open- 
collector signals are used for the control cable, and 
differential receiver-drivers are used for the data cable 
(Figure 3). Each line must have such buffers, since 
the controller is designed to drive one TTL load on 
all inputs and outputs. 

At a 5-Mbit/s data transfer rate to the host interface, 
a byte of data must be read every 1.6 ^s - in 8-bit 
parallel fomn. Few microprocessors can access a port 
and check status within this period. Consequently, 
a design objective of the WD1010 is compatibility with 
a programmed I/O environment, as well as the sup- 
port of off-line error detection and correction. 
Moreover, the chip can transfer multiple sectors on 
one command. To achieve such performance within 
the constraints of a 40-pin package, the WD1010 relies 
on a unique approach to the traditional peripheral 
interface. 

Three modes of communication can exist at the host 
interface: between the host and the WD1010, between 
the host and the buffer, and between the WD1010 and 
the buffer. For the host-WD1010 communication the 



-o 



WD1010 



-o TO DRIVE INPUTS 



i" 



FROM DRIVE 
' OUTPUTS 




TO DRIVE INPUTS 



-rr 



COMMON 



•51 > 51 



(A) 




FROM DRIVE OUTPUTS 



(B) 



o 

o 
o 



Figure 3. 

Buffering circuits from the WD1010 to the control cable (A) and the data cable (B) must be used because the 
controller has a rather limited drive capability (one TTL load each on inputs and outputs). 



Winchester Disk Controller Devices 



3-27 



a 

o 

o 



chip, like many microprocessors, tail<s over an 8-bit 
bi-directionai bus, plus Read, Write and chip select 
lines (Figures 4,5). Three address lines access 
registers within the chip. 



In host-buffer or WD1010-buffer communications 
(Figures 4,5), when the chip r eads or writes to the buf- 
fer, the Buffer Chip Select (BSC) line is pulled low. 
This signal should be used to disconnect the host 
data bus and Read and Write lines from the WD1010. 







r 




\_ 






ADo 
ADi 
AD2 
CS 

DB0-DB7 

HOST 
PROCESSOR 

Rd 

WR 
BUSY 




P-^ 




Ao 
A1 
A2 

5s 

Do-D/ 

WD1010 
BDRY 

bCR 

ffE 

We 
b5s 






















" 








^^ 






— 




DATA BUS (8) 






r-J 
















b--^ 


CS '°-"^TATlCRAM '^^ 
Aq , . . Ax RE 








1_> 










It- 




III 


T T 1 1 1 — ^ 




1 1 1 1 1 1 I' 








■«^ 


do • • • Qx 

BINARY COUNTER 

CP RST 




r-3r^T% 


_l 


1 




JN 


-J y~^-^ 








rs 


i^ 


1 






Y 

































Figure 4. 

Communications between a host and the WD1010 can be effected with the static RAM and binary counter cir- 
cuitry shown in Figure 4. These devices form a sector buffer that stores data sent from the host or the con- 
troller. This hardware handles both read and write operations on multiple sectors. 




DATA BUS (8) 



PORT B 
WD1510 ^^ 
DIR FIFO 
BUFFER 

EMPTY 
CSB FULL 



<F 



O 



S 



ENABLE— oj ^ N ^ \ 



Ao 
Al 
A2 
CS 

Do-D7 

BCR 

WD1010 
BDRY 

RE 
WE 



Figure 5. 

A variation on the circuit of Figure 4. uses a WD1510 FIFO buffer to replace the counter-RAM circuitry. The 
scheme works well at high throughput rates since the buffer need not be filled to transfer data supplied by 
the WD1010 to the host. 



3-28 



Winchester Disk Controller Devices 



The Read (RE) and Write (WR) lines become out- 
puts from the WD1010 and are strobed as each byte 
is placed on the bus. 

The sector buffer in Figure 4 is implemented with a 
binary counter and a static RAM. With each RE or 
WE probe, the counter is incremented so that the 
following byte can be read from or written to the next 
sequential location in the RAM. After all memory loca- 
tions are written to, a carry signal from the counter 
goes to the Buffer Ready (BRDY) line of the WD1010. 
This signal informs the controller that the counter has 
rolled over and that the buffer is either full or empty, 
depending on the command. 

During multiple-sector transfers, the RAM can be as 
large as the available sectors on each cylinder. The 
controller continues to load the RAM with data when 
a sector is being read. When no more memory is 
available, BRDY signals the WD1010. The command 
will then pause, wait for the host to dump the 
memory, and then begin filling the RAM again. This 
scheme permits both read and write operations on 
multiple sectors. 

Signals for host an d buf fer control include the Buf- 
fer C ounter Reset (BCR) line, whi ch is pulsed when 
BCS makes an active transition. BCR resets the 
binary counter before a read or write operation. Since 
address location 000 does not exist in the WD1010, 
a decoder can be used to make this address loca- 
tion enable the RAM and simulate a data register. For 
DMA applications, the Buffer Data Request (BRDQ) 
line is activated when data is available for host use. 

Numerous other methods can be used with these 
same control signals. For example, a first-in, first-out 
buffer (Figure 5) can replace the counter-RAM. In this 
scheme, the host can dump data before the WD1010 
fills the buffer. With sufficient throughput, the FIFO 
buffer need not have the storage capacity of an en- 
tire sector if the host can empty it quickly enough 
with a burst mode. In that case, the BRDY signal 
becomes the OR function of the Empty and Full 
signals from the FIFO buffer. 

MACRO COMMANDS PROVIDE MULTIPLE OPTIONS 

Each of the WD1010 Winchester controller-formatter's 
six macro commands contains several option flags. 
These flags allow the selection of stepping rates, 
multiple-sector transfers, and interrupt timing. The 
WD1010's task file contains additional options that 
are programmed before the command is actually 
issued. The operations of each command are as 
follows: 

Restore causes the read/write head assembly to move 
to track 000. The stepping rate is determined by the 
state of Seek Complete (pin 32), which is activated 
by the drive to indicate its readiness. The stepping 
rate specified in the Restore Command is not actually 
used but retained internally for an implied track later 
on. 

Activation of Seek causes a seek operation for any 
desired cylinder. The selected cylinder is loaded into 



the cylinder register. Then the controller decides 
which way to seek and how many steps to use. The 
Seek Complete line is not checked, making possible 
overlapping seek operations on several drives. 

The actual transfer of data from the WD1010 to sec- 
tor buffer is performed under the Read Sector com- 
mand. This command also causes a search for the 
specified cylinder, drive, head, and sector. Multiple 
sectors are specified and enabled through the sec- 
tor count register. If the multiple-option flag is set, 
the number of sectors specified are transferred to the 
buffer. 

Data in the sector buffer is written on the disk under 
the Write Sector command. Like the Read Sector 
command, it specifies and enables multiple drives 
through the sector count register. 

Both the Read and Write Sector commands will retry 
up to eight times before automatically performing a 
restore operation. After a restoration, the controller 
seeks out the marginal sector and tries to determine 
whether an error condition was caused by a misposi- 
tioning of the head or a problem in the actuator. 

The Format command is used to initialize a track with 
ID fields, gaps, and all information necessary for 
subsequent read and write operations. The sector buf- 
fer plays a unique role in this command, since it pro- 
vides information on error mapping and interleaving 
rather than data from a sector. The order in which 
each sector is to be recorded is specified in the buf- 
fer, together with information indicating whether a 
sector contains a bad block or an error flag. Gap sizes, 
number of sectors, and other information are 
specified in the task file to allow further control over 
the format. By incrementing the cylinder number 
register, an entire surface can be formatted by 
accessing just two registers. 



O 
o 

o 



THE WDIOIO'S MACRO COMMANDS 




CODE 


7 


6 


5 


4 


3 


2 


1 





Restore 











1 


R3 


R2 


Ri 


Ro 


Seek 





1 


1 


1 


R3 


R2 


Ri 


Ro 


Read Sector 








1 





1 


M 








Write Sector 








1 


1 





M 








Scan ID 





1 




















Write Format 





1 





1 















M = Multiple Sector Flag 

M = - transfer 1 sector 

M = 1 - transfer multiple sectors 

I = Interrupt Enable 

1 = 0- interrupt at BDRQ time 

1 = 1- interrupt at end of command 



Winchester Disk Controller Devices 



3-29 



o 

-a 

o 
o 



A MULTIPLE-DRIVE SYSTEM 

For multiple drive-head configurations, the WD1010's 
sector-drive-head (SDH) register Is decoded at address 
110 to produce Individual, latched drive-selection 
signals whenever the host writes to this address loca- 
tion. Binary head selection does not require a 
separate decoder, since one Is located at the drive. 

When the WD1010 senses a change In drive number, 
It automatically reads a cylinder. This takes place 
before the execution of the current command. The 
chip records the new cylinder number it has read and 
stores It internally as a reference for future seek 
operations on the current drive. 

After the execution of any command, the WD1010 
informs the host processor of any errors encountered 
during execution. On-board status and error registers 
report error condltons and signal status from the 
drive. To eliminate tedious en-or detection procedures, 
the host processor need only check the error bit In 



the status register to determine whether any bits are 
set in the error register. 

Bit of the status register Is set if any of 5 bits in 
the 8-bit error register are set - bit establishes the 
logical OR of the status register. Other error Indicators 
include a Bad Block Detect bit, which Is activated 
when an ID field contains a bad block mark, and an 
ID Not Found bit, which Is set when the desired 
cylinder, head, sector, or size parameter Is not found 
after 16 revolutions of the disk. The latter is also set 
if the data address mark of the data field is Incorrect 
when a read is executed. 



TO 
HOST 



TO 
DRIVE 



"s 




\ 

HEAD SELECT 
HEAD SELECT 1 
HEAD SELECT 2 
DRIVE SELECT 1 
DRIVE SELECT 2 
DRIVE SELECT 3 
DRIVE SELECT 4 



Figure 6. 

Four Winchester drives can be controlled by the WD1010 using an external latch and a 2-to-4-llne decoder. If 
the drive being accessed changes, the controller performs an automatic read operation. It records the cylinder 
number of the read for future seeks. 



3-30 



Winchester Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD1050 SMD Controller/Formatter 



o 

O 

Ol 

o 

C/) 



FEATURES 

16 BIT HOST INTERFACE 
9.677 M BITS/SEC DATA RATE 
SINGLE/MULTIPLE SECTOR TRANSFERS 
FIXED SECTOR FROMAT 
TTL COMPATIBLE INPUT/OUTPUT 
68 PIN JEDEC TYPE C CHIP CARRIER PACKAGE 
COMPATIBLE WITH SMD, MMD, FHT, LMD, AND 
CMD FAMILIES 
• SINGLE +5V SUPPLY 

DESCRIPTION 

The WD1050 SMD Controller/Formatter is an 
MOS/LSI device designed to interface an SMD com- 
patible rigid disk drive to a Host processor. The device 
is compatible with all rigid disk drives adhering to 
Control Data Corporation's flat cable interface for 
SMD, MMD, FHT, FMD, LMD and CMD families (CDC 
specification 64712400 Rev H). It is TTL compatible 
on most inputs and outputs, with interface capability 
for 8 or 16 bit data buses. 

The WD1050 contains a powerful set of Macro Com- 
mands for Read/Write and control functions. An inter- 
nal 16 bit task file is used to process a selected 
command based upon parameter information in the 
file. 

The WD1050 operates from a single -i-5V supply and 
Is available in a 68 pin JEDEC Type C chip-carrier 
package. 



DOC 
D1 
D2C 
D3C 
DA\Z 
DSC 
D6[Z 
D7IZ 
D8C 
DQC 
DIOC 
DUC 
D12C 
D13C 
D14C 
DISC 

wdC 



Z CD DO ^ 

^ ^ 5 ?» " <^l 2 S^ >" ^M^ O 33 O O tI 

o o -» fo wl ml ml o " t; 33l o -< D 3)1 wl 3 

nnnnnnnnnnnnnnnnn 

9 a 7 fi S 4 n 9 1 fifl fi7 fift fi^ ftj R-i o Ai 



3 2 1 68 67 66 65 64 63 62 61 



27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 



uuuuuuuuuuuuuuuuu 



60^ NO 

69 2I]CPO 
58^CP1 
57Z]CP2 

66rjcp3 

55|_JCP4 
M^CPS 

53:;3CP6 

52^CP7 
51 I] CP8 

49 I] US3 

48^US2 
47 ZH US1 
46 ^ USO 

45 ^TAG3 
44 I]TAG2 



PIN DESIGNATION 



Winchester Disk Controller Devices 



3-31 



PIN 
NUMBER 


NAME 


SYMBOL 


DESCRIPTION 


1 


Vcc 


Vcc 


-f-5V ±5% power supply input 


2 
3 

4 

5 


NO CONNECTION 


NO 
RE 

WE 

CS 


TrI-state bi-directional line, used as an input when 
reading the task file and an output when the WD1050 
is reading from the buffer. 

Tri-state bi-directional line used as an input when 
writing to the tasi< file and an output when the 
WD1050 is writing to the buffer. 

A logic low on this input enables both WE and RE 
signals as inputs. 


READ ENABLE 


WRITE ENABLE 


CHIP SELECT 


6-8 


ADDRESS 0-2 


A0A2 


These three inputs select a task file register to 
receive/transmit data. 


9 


NO CONNECTION 


NO 




10-25 
26 


DATA BUS 0-15 


D0-D15 
WD 


Sixteen bit bi-directional bus used for transfer of 
commands, status, and data. 

Open drain, NRZ data output which is synchronized 
to the Servo Clock Input. 


WRITE DATA 


27 


READ CLOCK 


RCLK 


Input clock from the drive which is synchronized 
with the Read Data input. 


28 


SERVO CLOCK 


SCLK 


A nominal 9.677 MHz clock input from the drive. This 
clock must be valid when Unit Ready (Pin 31) is 
active and Fault (Pin 34) is inactive. 


29 


READ DATA 


RD 


NRZ data input from the drive which must be syn- 
chronized to the Read Clock (Pin 25) input. 


30 


INDEX PULSE 


IP 


Active high input used to monitor the Index signal 
from the drive. 


31 


SECTOR 


SEC 


Active high input used to monitor sector pulses from 
the drive. 


32 


UNIT SELECTED 


USEL 


Active high input used to verify the selected drive. 


33 


UNIT READY 


URDY 


Active high input used to Inform the WD1050 of a 
ready condition on a selected drive. If this line is 
made inactive during any command, command 
execution is terminated. 


34 


UNIT BUSY 


UBSY 


Active high input used to monitor drive status dur- 
ing a unit selection. If the unit had previously been 
selected and/or reserved prior to issuing a USTAG, 
the UBSY must be made active within one microse- 
cond of the USTAG selection. This signal is used 
for dual-channel access applications and should be 
tied to ground when not used. 


35 


GROUND 


Vss 


Ground. 


36 


FAULT 


FAULT 


Active high Input used to detect a fault condition 
at the drive. Command execution Is terminated if 
Fault is made active during any command. Only the 
Fault Clear Command may be issued while this line 
is asserted. 



3-32 



Winchester Disk Controller Devices 



PIN 
NUMBER 


NAME 


SYMBOL 


DESCRIPTION 


37 


SEEK ERROR 


SKERR 


Active high input used to detect a seek error at the 
drive. 


38 


ON CYLINDER 


ONCYL 


Active high input used to inform the WD1050 when 
the heads are settled and positioned over a cylinder. 


39 


WRITE PROTECT 


WPROT 


Active high input used to monitor the Write Protect 
signal from the drive. 


40 


NO CONNECTION 


NCCTP) 


Test Point. 


41 


NO CONNECTION 


NO 




42 


UNIT SELECT TAG 


USTAG 


Active high output used for selection of a unit on 
US0-US3 lines. 


43-45 


TAG1-TAG3 


TAG1-TAG3 


Active high outputs used to strobe specific data out 
on the Control Port Lines. Tag definitions are: 
TAG1 _ Cylinder address 
TAG2 _ Head/Volume select 
TAG3 _ Control Tag 


46-49 


UNIT SELECT 0-3 


US0-US3 


These four outputs reflect the contents of the unit 
address field of the task file and are used to select 
one of 16 drives. 


50-59 


CONTROL PORT 
BITS 9-0 


CP9-CP0 


Ten bit output bus used to issue tag parameters to 
the selected drive. 


60 


NO CONNECTION 


NO 




61 
62 

63 


NO CONNECTION 


NC(TP) 
BCS 

BCR 


Test Point. 

Active low output used to enable reading or writing 
to the external buffer by the WD1050. 

Active low output that is strobed prior to Read/Write 
Commands. Used to clear an external buffer counter. 


BUFFER CHIP 
SELECT 


BUFFER COUNTER 
RESET 


64 


BUFFER DATA 
REQUEST 


BDRQ 


This output is set to initiate data transfers to/from 
the external buffer. 


65 


BUFFER READY 


BRDY 


This input informs the WD1050 that the buffer is 
either full or empty. 


66 
67 


INTERRUPT 
REQUEST 


INTRO 
MR 


Active high output which is set at the completion 
of any command, providing the '1' bit is also set in 
the command word. INTRO is reset subsequent to 
a Status register read. 

Active low input used to initialize the WD1050, 
usually after a power-UP condition. 


MASTER RESET 


68 


CLOCK 


CLK 


2 MHz Master Clock is input. 



Winchester Disk Controller Devices 



3-33 



o 

o 
o 

O 



FUNCTION DESCRIPTION 

The WD1050 SMD Winchester Controller performs the 
necessary link between an 8 or 16 bit processor and 
an SMD compatible drive. The internal architecture 
of the WD1050 is shown in Figure 1. The major func- 
tional blocks are: 

CONTROL UNIT 

This section decodes commands, implements com- 
mand execution sequencing, monitors the com- 
parator and CRC logic, monitors status and issues 
control to the Host and Drive Interfaces. It also writes 
appropriate information to the Status register during 
command execution. 

DATA I/O BUFFERS 

A 16-bit bi-directional three-state bus (D15-D0) for data 
transfers between the Host CPU or data buffer and 
the HDC. (The higher order 8-bits of this bus [D15-D8] 
may be used for 8-bit data bus transfers between the 
Host CPU and the HDC). 

HOST/BUFFER CONTROL 

This section allows HDC register selection and com- 
munication by the CPU, issues interrupt requests, and 
provides Direct Buffer Access (DBA) transfers bet- 
ween the disk drive and the data buffer. 



STATUS REGISTER 

A 16-bit register reflecting operational status of the 
HDC and disk drive. This is a read-only register, 

COMMAND REGISTER 

A 16-bit field containing command information that 
dictates operational control sequencing of the Host 
and Drive Interfaces by the HDC. This is a write-only 
register. 

DATA REGISTER 

A 16-bit field used to assemble/disassemble 
words/bytes during data transfers. This register is 
internally interfaced to the HDC's Data I/O Buffers 
('D' bus) and the HDC's Read Data Holding (RDH) 
register or Write Data Holding (WDH) register (as 
appropriate) during Host/drive data transfers. The 
contents of this register are compared to the 
appropriate Task File field as required by command 
execution. 

CRC LOGIC 

This logic is used to generate or check the 16-bit 
Cyclic Redundancy Check (CRC). The polynominal is: 

G(x) = X^^ + X12 + x^ + 1 



-(r) 



DATA- 

1/0 

BUFFER 



r^2[ZIZ) 



WE 

BCS ■♦■ 



BCR -*- 

BRDY 

BDRQ -*- 
INTRO ■*- 



HOST/ 
BUFFER 
CONTROL 



TASK 
FILE 



COMPARATOR 



CONTROL 
UNIT 



CONTROL 
PORT 



-o 



UNITSEL 
PORT 



:> 



CPO- 
CP9 



USO- 
US3 






DRIVE 

CONTROL 

PORT 



■ WD 
SCLK 



TAG 1- 

TAG 3 

■INDEX 

■SECTOR 

■ FAULT 

•SKERR 

■ONCYL 

■URDY 

"WPROT 

■UBUSY 

•USEL 



Figure 1. BLOCK DIAGRAM 



3-34 



Winchester Disk Controller Devices 



The CRC includes all information beginning with the 
Sync character and ending with the CRC word. The 
CRC is preset to ones prior to a data transmission. 

The CRC is Implemented in parallel eight bits at a 
time as data is transferred between the HDC's Data 
register and the HDC's Read or Write Data Holding 
registers. The CRC word is transferred to the HDC's 
Data register and appended to the ID Field and Data 
Field (if enabled) during Format Sector or Write Data 
Commands. 

COMPARATOR 

A 16-bit comparator used to compare the appropriate 
HDC's Task File field with the respective byte(s) read 
from the disk. 

READ DATA SHIFT REGISTER (RDS) 

This 8-bit register shifts data read from Read Data 
(RD) input via the drives Read Clock (HDC's RCLK 
input). 

READ DATA HOLDING REGISTER (RDH) 

This 8-bit holding register assembles bytes from the 
Read Data Shift register and transfers them to the 
Data register. 

WRITE DATA HOLDING REGISTER (WDH) 

This 8-bit holding register receives bytes from the 
Data register and provides an eight bit parallel input 
to the HDC's Write Data Shift register (WDS). 

WRITE DATA SHIFT REGISTER (WDS) 

This 8-bit shift register converts the eight bit parallel 
input from the Write Data Holding register (WDH) into 
a se rial bit stream issued to the HDC's Write Data 
(WD) output via the drive's Servo Clock (HDC's SCLK 
input). 

DRIVE CONTROL 

This section monitors drive status, synchronizes the 
byte boundaries generated by the Servo Clock to the 
sync character read from the disk or the drive's Index 
or Sector pulse as appropriate, and issues control 
tags to the drive. 

CONTROL PORT (CPO-9) 

This 10-bit output is used to provide the drive with 
volume/head #, cylinder address, and control infor- 
mation in conjunction with outputs Tag 1 (cylinder 
address), Tag 2 (volume/head #), and Tag 3 (control). 
The contents of the appropriate HDC register or 
signals generated from the Control Unit are gated to 
the Control Port during command execution. 

UNIT SELECT PORT (USO-3) 

This 4-bit output port reflects the contents of the Unit 
Address register. The Unit Select Tag output selects 
the desired disk drive unit. 



HOST INTERFACE 

The primary interface between the Host processor 
and the WD1050 is through a 16-bit bi-directional bus. 
This bus is used to transfer status, parameter, and 
command information between the WD1050 and the 
Host, as well as data between the WD1050 and sec- 
tor buffer. The external sector buffer is constructed 
with either FIFO memory or a RAM and binary 
counter. Since the WD1050 will make this bus active 
when accessing the sector buffer, a transceiver must 
be used to isolate this bus from the Host. Figure 2 
shows a typical Host Interface using a RAM and 
Binary counter. The Sector Buffer may be one or more 
sectors in length, depending upon system 
requirements. 

Whenever the WD1050 is n ot us ing the sector buf- 
fer, the Buffer Chip Select (BCS) is high (disabled). 
This allows the Host to access the WDIOSO's Task 
File, read status, and issue commands. It also allows 
the Host to access data within the Sector Buffer. A 
separate RAM select line from the Host is used to 
access the data in memory. With each RE or WE 
strobe from the Host, the address counter is 
incremented on the trailing edge of RE or WE, point- 
ing to the next sequential memory location. Whenever 
the WD1050 ch anges the state of BCS, the Buffer 
Counter Reset (BCR) Line is strobed, causing the 
address counter to be reset to zero. The RE and 
WE lines become outputs from the WD 1050 to 
allow access to the buffer only when BCS is low. 
Although 8-bit programming is allowed via the use 
of Address Line 0. the data path to and from the 
WD1050 must be 16 bits wide. 

TASK FILE 

The WD1050 contains five 16-bit registers called the 
Task File. These registers are used to set up 
parameter information prior to issuing a command. 
These registers are: 



A2 


A1 


AO 


15 REGISTER 











HEAD/SECTOR ADDRESS 





1 





SECTOR COUNT/LENGTH & 
UNIT ADDRESS 


1 








CYLINDER REGISTER 


1 


1 





COMMAND REGISTER (WRITE 
ONLY) 


1 


1 





STATUS REGISTER (READ 
ONLY) 



Each register in the Task File is accessed by selec- 
ting the proper address while CS (pin 4) is low, 
then strobing the WE or RE lines. All registers in the 
Task File are Read/Write except for the Com- 
mand/Status register. The Command register can only 
be written to, while the Status register is a read-only 
register. The command and status registers have the 
same address. 



O 
o 
o 
C/) 



Winchester Disk Controller Devices 



3-35 



D 
o 

Ol 

o 
C/) 

O 



D0-Dl5 



HOST 
INTERFACE 



RD 

WR 

INTR REQ 

DATA REQ 



CHPSEL 
ADDR 



4>^ 



DATA BUS (16) 



D- 



DATA 

STATIC 

RAM 

ADR 



r 



BINARY 

COUNTER 
1_- 



-\> 



D0D15 



BCR 
BRDY 

SCS 

RE" 

WE 

INTR 

BDRQ 

CS 

Ao-A2 



Figure 2. TYPICAL HOST INTERFACE 



An 8-bit mode can also be used for accessing the 
Task File. Data Is read/written on the most signifi- 
cant 8-blts of the Data bus (D15-D8). The upper byte 
is accessed with Aq (pin 7) Is high, and the lower 
byte is accessed when Aq Is low. The upper byte (Aq 
= 1) must be accessed first, followed by the lower 
byte. This Insures that data is transferred to the inter- 
nal 16-blt bus properly, and that a command will 
execute after the full 16-blt word Is written. 

HEAD/SECTOR ADDRESS 

This register holds the Head number and Sector 
Address fields: 
15 8 7 



HEAD NUMBER 



SECTOR ADDR 



The Sector Address byte (bits 7-0) holds the logical 
sector number used for comparison when searching 
for the specified ID field. The Head number byte (bits 
15-8) holds the logical head number, and volume flag 
(where applicable). This 8 bit field is sent to the drive 
via the Control Port (CP7-0) when Tag 2 is issued. Note 
that all 8-bits of each byte are wrtten into the ID field 
during formats and are compared during other 
commands. 

CYLINDER REGISTER 

This register holds the 16-blt cylinder number: 
15 



The least significant 10-bits of this register (bits 9- 0) 
are transferred to the Control Port (CP9-0) when Tag 
1 is Issued. All sixteen bits of this register are writ- 
ten to the ID field during formats and are compared 
during other commands. 

SECTOR COUNT/LENGTH & UNIT ADDRESS 

This register holds the Sector Count, Sector Length 
and Unit Address fields: 

15 14 8 7 4 3 



M 


SECTOR COUNT 


LENGTH 


UNIT 



The four bit Unit Address field (bits 3-0) contains the 
physical Unit Address and is reflected at the drive via 
the Unit Select Port (US3-0). This port is used in con- 
junction with the Unit Select Tag (USTAG) output to 
select the desired drive. 

The four bit sector length field is used to determine 
the number of bytes to be read/written from the disk. 
The allowable Sector Lengths are: 





BITS 




# OF BYTES 


7 


6 5 


4 


IN DATA FIELD 


1 








128 





1 





256 





1 





512 








1 


1024 



CYLINDER REGISTER 



3-36 



Winchester Disk Controlier Devices 



If the CE bit (CRC Enable) in the command word is 
zero, an additional 8 bytes are added to the above 
sector length (and the CRC bytes are not appended 
to the data field). These bytes can be used to append 
ECC codes to each sector. 

The Sector Count Field, seven bits of which (bits 14-8) 
are used to control single/multiple record operation 
for commands where the LS (Logical Sector) Flag is 
set, is decremented by one for each sector 
encountered after the desired sector has been located 
on the disk. The Op Code Command is repeated until 
the contents of this field (bits 14-8) are equal to zero. 
For single sector operation, this field (bits 14-8) must 
equal "0000000". (This field [bits 14-8] is ignored for 
the Fault Clear Command). 

For the Format Sector, Verify Sector, and commands 
where the LS flag is not set, the Sector Count Field 
(bits 14-8) must contain the desired physical sector 
location (i.e., the Sector Count number of sector 
pulses from the Index Pulse = physical sector loca- 
tion). This register is counted down to zero to deter- 
mine the physical sector location for these com- 



mands. For physical sectored commands, bit 15 is 
used as a one bit field controlling single/multiple 
record operation. For bit 15 equal to '0', a single sec- 
tor command is executed. For bit 15 equal to '1', these 
commands are repeated until the Index pulse is re- 
encountered, allowing multiple sector operations. 

For logical sectoring, bit 15 of this register should 
equal '0'. 

COMMAND REGISTER 

This "write-only" register is used to load in the desired 
command: 

15 



COMMAND REGISTER 



The command register may be loaded whenever the 
Command-In-Process (CIP) status bit is low. 

STATUS REGISTER 

This "ready-only" register is used to monitor status 
and error conditions as the result of command execu- 
tion or its format is: 



o 

CJl 

o 



15 


14 


13 


12 


11 


10 


9 


8 


7 


6 


5 


4 


3 


2 


1 





BCS 


CIP 


UBSY 


USEL 


WPRT 


URDY 


OCYL 


SKER 


BCS 


FLT 


BDRQ 


- 


DFCE DFNF 


IDCE 


IDNF 



BIT 


NAME 


DESCRIPTION 





ID Field Not Found (ID/NF) 


Set if the sync character preceding the ID Field contents read from 
the disk do not match the respective Task File contents. 


1 


ID CRC Error (IDCE) 


Set if the CRC calculation on the ID Field read from the disk is in error. 


2 


Data Field Not Found 
(DFNF) 


Set if the Data Field sync pattern following the ID Field does not match 
the sync character. 


3 


Data Field CRC Error (DFCE) 


Set if the CRC Calculation on the Data Field read from the disk is in 
error 


4 


Not Used 


This bit is not used; it is forced to a zero. 


5 


Buffer Data Request (BDRQ) 


Reflects the Buffer Data Request output. 


6 


Fault (FLT) 


Reflects the status of the Fault (FLT) input. 


7 


Buffer Chip Select (BSC) 


This bit is an inverted copy of the Buffer Chip Select (BCS) output. 


8 


Seek Error (SKER) 


Reflects the status of the Seek Error (SKER) input. 


9 


On Cylinder (ONCYL) 


Reflects the status of the On Cylinder (ONCYL) input. 


10 


Unit Ready (URDY) 


Reflects the status of the Unit Ready (URDY) input. 


11 


Write Protect (WPRT) 


Reflects the status of the Write Protect (WPRT). 


12 


Unit Selected (USEL) 


Reflects the status of the Unit Selected (USEL) input. 


13 


Unit Busy (UBSY) 


Reflects the status of the Unit Busy (UBSY) input. 


14 


CIP 


Set when a command is in progress. 


15 


Buffer Chip Select (BCS) 


This bit is an inverted copy of the Buffer Chip Select (BCS) output. This 
bit also appears in Status Bit 7. 



Note: That Status Register bits 13-8 are frozen upon premature command termination (as described in Com- 
mand Execution, step 2). These bits are released to active monitoring and error bits 3-0 are reset low following 
a read of the Status register (or following programming of the Command register) when the Command register 
CIP bit is low and/or the INTR output is inactive. 



Winchester Disk Controiier Devices 



3-37 






INSTRUCTION SET 

The WD1050 will execute eight commands. Prior to 
Issuing a command, the Host must first setup the 
Task File with parameter information. 



A command can only be accepted if the CIP bit In 
the status register is low. 



COMMAND 


MSB 








COMMAND REGISTER BITS 










LSB 


15 14 


13 


12 


11 


10 9 8 7 6 5 


4 


3 


2 


1 





Fault Clear 


1 











10 





U 


s 


E 


D 


Return to Zero 


1 





1 





10 


M 


U 


s 


E 


D 


Seek Cylinder 


1 


1 





V 


L 1 Z C H 


M 


u 


s 


E 


D 


Read ID Field 


1 


1 


1 


R 


L 1 Z C H 


M 


u 


s 


E 


D 


Read Sector 


1 1 








R 


L 1 Z C H 


M 


u 


s 


E 


D 


Write Sector 


1 1 





1 


R 


L 1 Z C H 





u 


s 


E 


D 


Format 


1 1 


1 





R 


P 1 Z C H 





u 


s 


E 


D 


Verify 


1 1 


1 


1 


R 


P 1 Z C H 


M 


u 


s 


E 


D 



FLAG SUMMARY 


V = Verify 


1 = Interrupt Enable 


R = CRC Enable 


Z = Volume/Head Change 


L = Logical Sectoring 


C = Cylinder Addr 


P = Programmable Sectors 


H = Head Selection 


= On Cylinder 


M = Marginal Data Recovery 


E = Priority Release/Early 


U = Unit Sel/Servo Minus 


D = Unit Deselect/LATE 


S = Priority Sel/Servo Plus 



COMMAND FLAG DESCRIPTION 



BIT 


NAME 


DESCRIPTION 


V 

R 

L 

P 


1 


Verify 

Data Field CRC Enable 
Logical Sectoring 

Programmamble Sectors 

On Cylinder 
Interrupt Enable 


Compare The Head number and Cylinder Address word of the ID field with 
the appropriate Task File field when On Cylinder becomes active. The Sec- 
tor Address byte in the ID Field is not compared, althought the CRC is 
checked. This flag is valed only for the Seek Cylinder Command. 

Data Field CRC is enabled. If the flag is not set, the condition of the DFCRC 
Status bit will not affect command execution; the data field is extended 
by four words (8 bytes), and the CRC bytes are not appended. 

Locate sector by matching the ID Field bytes read from the disk to the 
appropriate field in the HDC Task File. The Sector Count register in the 
Task File is used to indicate the additional number of sectors to be transfer- 
red for multiple sector commands. 

If L is not set, physical sectoring is implemented. The Task File Sector 
Count register is decremented to locate the desired physical sector from 
the Indes pulse. ID Field compares are made, but do not affect command 
execution. 

The Head Number/Sector Address register is read from the buffer as each 
sector is encountered per command execution. (This allows an entire track 
to be formatted/verified with interleave sectors in one revolution of the 
disk). This flag is valid only for the Format Sector or Verify Sector 
Commands. 

For the Seek Cylinder Command, command completion requires activa- 
tion of On Cylinder or Seek Error inputs. 

For other commands. On Cylinder is required before a read or write can 
occur. 

Enable the interrupt output (INTRO) for activation upon completion or ter- 
mination of command execution. 



3-38 



Winchester Disk Controller Devices 



COMMAND FLAG DESCRIPTION 



BIT 


NAME 


DESCRIPTION 


Z 


Volume/Head 


Issue Tag 2 as required for volume/head cfiange. 


c 


Cylinder 


Issue Tag 1 as required for cylinder address selection. (Tag 1 will follow 
Tag 2 if the Z and C flags are both set). 


H 


Head 


Issue Tag 2 as required for head selection. (Tag 2 will follow Tag 1 if the 
C and H flags are both set). 


M 


Marginal Data 


Attempt a marginal data recovery, (marginal data recovery may be attemp- 
ted only where a command requires reading from the drive). 

This bit controls the function of bits 3-0 (U, S, E, D). (See Note 1) 


U 


Unit Select/Servo 
Offset Minus 


For M = (or not applicable, set Unit Select Tag as required for unit selec- 
tion. Unit Selected must become active for command execution to 
continue. 


S 


Priority Select/ 
Servo Offset Plus 


For M =0, issue priority select control as required to reserve the unit. See 
Note 2). 

For M =1, issue servo offset plus control for marginal data recovery 
attempt. 


E 


Priority Release/ 
Data Strobe Early 


For M = 0, issue priority release control as required to release reserve 
of the unit. (See Note 2) 

For M = 1, issue data strobe early control for marginal data recovery 
attempt. 


D 


Unit Deselect/Data 


For M - 0, reset Unit Select Tag at Completion of the command. 




Strobe Late 


For M - 1, issue data strobe late contron for marginal data recovery 
attempt. 



Note 1: Certain marginnal data recovery features are not applicable depending on the particular drive type 

under control. (Refer to CDC Interface Specification 64712400). 
Note 2: Priority select and release features are applicable only for dual channel drive applications. 



COMMAND EXECUTION 

Command work architecture has been designed to 
provide comprehensive control of the drive unit via 
programmable macro-level commands. For example, 
unit selection, cylinder seek, head selection, Op Code 
execution (of multiple records if desired), and unit de- 
selection can be performed with a single command. 

Command execution follows the following sequence 
(for'M'flag =0): 

1. If the U flag is set, the Unit Select (US) Tag is 
activated. (The drive should select the unit 
specified by the Unit Select bus [USO-3] when the 
US Tag is activated.) 

If the S flag is also set, CP9 will be activated when 
the US Tag is activated (exclusively reserving the 
unit to that channel until released). 

2. The following conditions must be met and main- 
tained for command execution to continue: 
Unit Ready input active 

Unit Selected input active 
Unit Busy input not active 



If these comditions are not met, command execu- 
tion is terminated with the appropriate bit set in 
the Status register. 

For all commands except the Fault Clear Com- 
mand, the Fault input must also be inactive and 
remain inactive for command execution to 
continue. 

For the Write Data and Format Commands, the 
Write Protect Status bit is checked; if true com- 
mand execution is terminated. 

For the Write Data Command, and the Format 
Verify Command with the P (programmable sec- 
tor) flag set, the HDC activates BDRQ requesting 
the Host to provide the required data to the buffer. 

If the Z flag is set (indicating a volume change), 
the Head number field of the Task File is issued 
to the Control Port (Head field bits 15-8 to CP lines 
7-0 respectively), and Tag 2 is pulsed. (Applies only 
for drives with volume select.) 

If the C flag is set (indicating a cylinder address 
seek), the Cylinder Address field of the Task File 
is issued to the Control Port (bits 9-0 respectively), 
and Tag 1 is pulsed. 



o 
o 
C/) 



Winchester Disk Controller Devices 



3-39 



o 

o 
en 

o 

CO 

<: 



NOTE: 

For the Seek Cylinder Command, and for other 
commands where the On Cylinder flag is set, the 
On Cylinder Input must be active before Tag 1 will 
be issued. (If the Seek Error input is active or 
becomes active before On Cylinder is active, 
execution is terminated with the Seek Error status 
recorded in the Status register). 

7. If the H flag is set (indicating a head selection), 
the Head number field of the Task File is issued 
to the Control Port (Head field bits 15-8 to CP lines 
7-0 respectively), and Tag 2 is pulsed. 

8. For commands other than Seek Cylinder, flag 
operation is as follows: 

If is set, execution is suspended pending an 
active On Cylinder input. 

if O is not set, the command is executed 
regardless of the condition of On Cylinder. 

NOTE: 

Data transfer to/from the drive with On Cylinder 
inactive is allowed only under certain cir- 
cumstances on specific drives. For example, on 
a drive with both fixed and moveable heads, it is 
possible to execute a Seek Cylinder Command 
with the C flag not set to the moveable heads (On 
Cylinder will drop). The fixed heads may then be 
given a Read Data command with the O flag not 
set. The Fixed head can then be read regardless 
of the condition of On Cylinder. (This is an overlap 
seek within a given unit between the fixed and 
moveable media). For valid read/write operation 
without an active On Cylinder, refer to the 
appropriate drive operating specification. 

For commands with C set and Seek Error received 
instead of On Cylinder, command execution is 
terminated. 

9. For the Write Data Command, and the Format and 
Verify Commands with the P flat set, the BRDY 
input is inspected. Command execution is 
suspended pending reception of a lovy to high 
transtion on the BRDY input. 

NOTE: 

For commands where M is set, marginal data 
recovery control as described in the chart below 
is issued to the control port prior to the activation 
of Tag 3. Note that unit selection, channel reserve 
control, and unit deselection must be 
accomplished with a non-marginal data recovery 
command since the U, S, E, and D flags assume 
marginal data recovery control significance. 



COMMAND 

FLAG 
IF MD IS SET 


FEATURE 


CONTROL 

PORT BIT 

ACTIVATED 


U 
8 
E 
D 


Sen/o Offset Plus 
Servo Offset Minus 
Data Strobe Early 
Data Strobe LATE 


2 

3 

7 
8 



Location of the appropriate sector within the cylinder 
is common to all commands except Fault Clear and 
RTZ. One of two methods is used: logical sector search 
(for commands where the L flag is set) and physical sec- 
tor locating (for the Format and Verify Commands and 
commands where the L bit is not set). 

Logical sector search consists of reading the first 
encountered ID Field, comparing these bytes to the 
appropriate fields in the HDC's Task File, (including the 
sync byte) and checking the ID Field CRC bytes. When 
a valid compare with correct CRC are found, execution 
continues. If a valid compare with correct CRC are not 
found before four Index pulses are detected, the 
appropriate Status bits are set (IDNF and/or IDCE) and 
command execution is complete. For mulitple sector 
commands. The Sector Address field of the Task File 
is incremented between sectors and the Sector Count 
field is used to indicate the number of additional sec- 
tors for which the command is to be executed. A single 
sector sommand is executed for Sector Count = 
'00. . .00". 

Physical sector locating is accomplished by decremen- 
ting the Sector Count field of the Task File by one for 
each Sector pulse encountered after the Index pulse is 
located until the Sector Count field = '0000000'. For 
Sector Count = '0000000', the command will be 
executed to the sector immediately following the Index 
pulse. The ID Field compares and the IDCE check are 
still made and the appropriate bit set in the Status 
register (if applicable), but command execution is not 
affected by an error condition. A single sector command 
is executed if bit 15 of the Sector Count/Sector 
Length/Unit Address register of the Task File is zero. 
If bit 15 is one, command execution is repeated until 
the Index pulse is re-encountered. Note that Status 
register error bits are not cleared between sectors (one's 
catching). 

Tag 3 (Control Select) is activated for all commands 
except Seek Cylinder with the V flag not set. 

When the appropriate Sector pulse is encountered, CPI 
(Read Gate) is activated and the HDC synchronizes to 
the first low to high transition on the Read Data (RD) 
input. This initiates the following three compares: the 
sync byte FE preceded by eight zeros, the upper and 
lower Cylinder Address, and the Head number and Sec- 
tor Address. (The Sector Address compare is sup- 
pressed on the Seek Cylinder command). The ID FIELD 
CRC is then checked. CPI is deactivated and command 
execution follows. 

FAULT CLEAR 

CP4 (Fault Clear) is pulsed and this completes execu- 
tion. This command is intended to clear the Fault out- 
put of the drive. The condition causing the fault within 
the drive should no longer exist when this command 
is issued. 

RTZ (RETURN TO ZERO) 

CP6 (RTZ) is pulsed and the Cylinder Address, Head 
number, and Sector Address fields of the Task File 
are all set to zero. This completes execution. 



3-40 



Winchester Disk Controller Devices 



SEEK CYLINDER 

Execution of this command is controlled completely 
by the command flags. If O is set, execution is 
suspended until On Cylinder (or Seek Error) is 
received. If the V flag is not set, receipt of On Cylinder 
completes execution. If C and V are both set, and On 
Cylinder is received, CPI (Read Data) is issued and 
the ID Field is inspected. The Sector Address com- 
pare is not made for this command. 

NOTE: 

If L is set (logical sectoring), execution is complete 
when ID Field is successfully found or when the 4th 
Index pulse is encountered. There is no multiple sec- 
tor operation when L is set for this command. If L 
is not set (physical sectoring), the IDNF and IDCE 
Status bit are one's catching. (The entire track may 
be verified with multiple sector operation). 

The V flag is ignored if the O flag is not set. 

If the C flag is not set, this command may be used 
for Unit Select only functions. 

READ ID FIELD 

The Read ID Field command is provided to allow 
transfer of the ID Field f ormatted on the disk to the 
data buffer (i.e., BCS • D15-Do • WE pulses). 
The Sector Address field is not compared in this 
command. 

If the L flag is set, the first encountered ID Field is 
transferred to the buffer. The following bytes are 
transfered: OOFE, Upper and Lower Cylinder Address, 
Head numberj Sector Address, and two CRC bytes. 
Thus four WE pulses are issued. 

If the L flag is not set, the physical sector is located 
and the corresponding ID Field is transferred to the 
buffer. 

There are no retries with this command if ID Field 
compare errors result. 

For the Read ID Field command, CP1 is reactivated, 
and the first low to high transition on the RD input 
initiates a compare for the Data Field sync character. 
If the compare does not match, the Data Field Not 
Found (DFNF) Status bit is set. The Data Field CRC 
(DFCE) Status bit is set if an error is detected. CP1 
is then deactivated. 

Note that the Data Field is not transferred with this 
command, but that the following eight bytes are 
transferred: 00, FE, Upper Cylinder Address, Lower 
Cylinder Address, Head #, Sector Address, and the 
two CRC bytes. 

If the L flag is not set, multiple sector operation con- 
tinues to the next INDX pulse without inspection 
BRDY. 

For multiple sector operation, the Sector Address 
Field of the Task File is automatically incremented. 



If the L flag is set, the BRDY input is inspected follow- 
ing each sector's transfer. If a low to high transition 
has not occurred (i.e., buffer not full) execution is then 
repeated. If a low to high transition has occurred, (i.e., 
buffer is full) BSC is deactivated, BCR is pulsed, and 
BDRQ is activated. Execution is suspended pending 
a low to high transition of BRDY (i.e., buffer empty). 
BCR is then pulsed, and execution is repeated. If a 
Data Field CRC is detected, the command will not 
terminate. 

READ DATA 

After the appropriate sector has been located. Data 
Field operation is as described under the Read ID 
Field Command, except that the Data Field is transfer- 
red to the buffer. Note that only the Data Field data 
bytes are transferred with this command. 

This completes execution for single sector com- 
mands and for multiple sector commands where the 
L and R flags are set. If a Data Field sync error (DFNF) 
or a Data Field CRC (DFCE) error has occurred, the 
command will be terminated. 

For multiple sector commands where the R flag 
and/or L flag is not set, or for multiple sector com- 
mands where no Data Field error has occured, execu- 
tion is repeated. 

Note that if the R flag and/or the L flag is not set, 
the DFNF and DFCF Status bits are one's catching. 

WRITE DATA 

After the appropriate sector has been located, CPO 
(Write Gate) is activated. Thirteen bytes of zeros (two 
Write Splice bytes and eleven PLO Sync bytes) are 
written followed by the sync character. The Data Field 
is th en written to the disk from the data buffer (i.e., 
BCS • D15-D0 • Re pulses). The CRC bytes and 
two bytes of zeros (End of Record) are appended to 
the Data Field and written to the disk. 

For multiple sector operation, the BRDY input is 
inspected following each sector's transfer. If a low 
to hig h transition has not o ccurred (i.e., buffer empty), 
BCS is deactivated, BCR is pulsed, and BDRQ is 
activated. Execution is suspended pendin g a lo w to 
high transition on BRDY (i.e., buffer full). BCR is 
then pulsed, and execution is repeated. 

FORMAT SECTOR 

Physical sectoring only applies to the Format Sec- 
tor Command. Upon reception of the appropriate Sec- 
tor pulse, CPO (Write Gate) is activated. Twenty seven 
bytes of zeros (16 Head Scatter bytes and eleven PLO 
Sync bytes), and the sync character are written to the 
disk from the HDC's Task File, and the resultant CRC 
is appended. Thirteen bytes of zeros are written (two 
Write Splice bytes and eleven PLO sync bytes) 
followed by the sync character. The Data Field (For- 
mat Character E5 repeated) is then written. If the R 
bit is set, then the two CRC bytes are appended; if 



O 

o 
o 

C/) 
O 



Winchester Disk Controlier Devices 



3-41 



o 

o 
o 

C/) 

o 



R is not set, eight additional E5's are added to tlie 
data field. Zeros are written until the next Sector or 
Index pulse is encountered. 

For single sector operations CPO is then deactivated. 
For multiple sector operation, CPO remains active, and 
execution is repeated until the Index pulse is again 
encountered. 

If the P flag is set, the HDC will fetch the Head 
Number/ Sector Address from the data buffer prior 
to encountering each ID Field. Thus, by filling the data 
buffer with the desired Head Number /Sector 
Address information, the HDC can format an entire 
track with any given programmed sector interleave 
in one revolution. 

If the P Flag is not set, the contents of the Sector 
Address field of the Tasl< File will be incremented by 
one between sectors. 



The BCS output will remain active for the 
duration of this command. 

VERIFY SECTOR 

This command allows verification of sector format 
without transfer of data. Sector addressing is iden- 
tical to that described for the Format Sector Com- 
mand. The IDNF, IDCE, DFND and DFCE bits are set 
if errors are found (all bits are one's catching for multi- 
ple sector operation). With multiple sector operation, 
an entire tracl< can be verified in a single revolution. 

NOTE: 

When used with the Lark drive, the validity of the 
DFCE bit is not guaranteed with this command if it 
immediately follows a FORMAT of the sector. 



n 


— ((J~ 






ir' 




16 BYTES 
•00' 


11 BYTES 


S 
Y 
N 
C 


ID 
FIELD 


2B 

W 


11 BYTES 
■00' 


S 
Y 
N 
C 


DATA FIELD ' 
128 TO 1024 BYTES 


C 
R 
C 


C 


2B 
W 


7 BYTES 
MINW 


i 


1 






If' 




1 


1 


(6 BYTES) 


1 




V 


ID FIELD 










UPPER 
CYL 


LOWER 
CYL 


HEAD 


SECTOR 
ADDR 


CRC 

1 


CRC 
2 

















FIXED SECTOR FORMAT 



















1 






^ ISSUE ^ 

L COMMAND J 


YES 








NO 


C^ FUG SET ^ 

\^ ? ^y^ 

YES 






SETCIP 
ISSUE b5r 












' ' 


SETCP9 




<_ FLAG SET _> 

^s^ ? ^>^ 

Tno^ 
























SET USTAG 






C^ FLAG SET ^ 












NO 


RESET CP9 
(IF SET) 

























3-42 



Winchester Disk Controller Devices 



ISSUE CP4 PULSE 
(FC) 




SET TAG 3 



ISSUE CP6 PULSE 
(RTZ) 



o 

O 

o 
C/) 




P ^^ NO 

FLAG SET 



SET BDRQ 



YES 




YES 



Z ^^ NO 
FLAG SET 




HEAD & SECTOR ADDR. 

TO CONTROL PORT 

PULSE TAG 2 




SET BDRQ 



Winchester Disk Controller Devices 



3-43 



o 

o 
01 

o 

C/) 

o 







NO y^ c 

FLAG SET 




NO ^ O 

FLAG SET 



CYLINDER ADDRESS 

TO CONTROL PORT 

PULSE TAG 1 




H ^>s^ NO 

FLAG SET 



HEAD & SECTOR ADDR 

TO CONTROL PORT 

PULSE TAG 2 



6 




YES 







3-44 



Winchester Disk Controller Devices 




o 

o 
en 

o 

CO 

o 



Winchester Disk Controller Devices 



3-45 



o 

-A 

o 
01 

o 

CO 

o 




YES 



SET B.CS 
PULSE BCR 



o 



3-46 



Winchester Disk Controiier Devices 




o 

CXI 

o 
C/) 



Winchester Disk Controller Devices 



3-47 



g 
o 
o 
C/) 

o 



COMPARE ID SYNC 
CYLINDER, AND 
HEAD ID FIELD, 

BYTES FROM DISK 




COMPARE SECTOR 

ID FIELD BYTE 

FROM DISK 




SET ID NF 



READ IDCRC 
BYTES FROM DISK 




SET IDCE 



RESET CPI 
(READ GATE) 



3-48 



Winchester Disk Controller Devices 




D 

O 

o 
C/) 

a 



Note: If the R Flag is not set, 8 additional bytes are included in the Data Field for appended ECC. 



Winchester Disk Controller Devices 



3-49 



o 

o 
o 
C/) 

D 




SET CP1 
(READ GATE) 



SET CPO 
(WRITE GATE) 



COMPARE DATA 
FIELD SYNC BYTE 



READ DATA 

FROM 

BUFFER 



SET DFNF 




WRITE PAD, SYNC, 

DATA & CRC (IF 
ENABLED) TO DISK 



TRANSFER 
DATA TO 
BUFFER 



YES 



RESET CPO 
(WRITE GATE) 



SET DFCRC 
RESET CP1 
(READ GATE) 




RESET CP1 
(READ GATE) 



■© 



3-50 



Winchester Disk Controller Devices 




o 

o 
en 

o 

CO 

o 



Note: if the R flag is not set, 8 additional E5 bytes are included in the Data Field for ECC extension. 



Winchester Disk Controller Devices 



3-51 



o 
o 

o 
C/) 



© 



SET CPO 
(WRITE GATE) 



WRITE 27 BYTES 
OF 'OO' TO DISK 



WRITE: 

SYNC BYTE 

ID FIELD 

ID ORG BYTES 

TO DISK 



WRITE 13 BYTES 
OF '00' TO DISK 



WRITE: 

SYNC BYTE 

E5 DATA FIELD 

TO DISK 



WRITE '00' TO DISK 



RESET CPO 
(WRITE GATE) 



6 




* Abort upon loss of URDY or USEL, or receipt of UBSY (all commands). 
Abort upon receipt of FLT (all commands except Fault Clear). 



3-52 



Winchester Disk Controller Devices 







M 
FLAG SET 



NO 







FREEZE 
STATUS REGISTER 



( ABORT* J 



RESET TAG 3 

RESET USTAG 

FREEZE STATUS 

REGISTER 



o 
o 
o 
CO 



FLAG SET 


^ YES 




PULSE CP9 








><o 







RESET TAG 3 
RESET BCS 
PULSE BCR 



RESE T TAG 3 

RESET BCS PULSE BCR 




RESET USTAG 



YES 



RESET BDRQ 



PULSE BCR 
SET BDRQ 




(PULSE BCR ] 
RESET CIP J 



"Abort upon loss of URDY or USEL, or receipt of UBSY (all 
commands). 
Abort upon receipt of FLT(all commands except Fault Clear). 



Winchester Disk Controlier Devices 



3-53 



ELECTRICAL CHARACTERISTICS 

ABSOLUTE MAXIMUM RATINGS 

Vcc with respect to Vss (Ground) +7V 

Max Voltage on any Pin with 

respect to Vgs -0.5V to + 7V 

Operating Tennperature. . .0°C(32°F) to 70°C(158°F) 

Storage Temperature -55°C(-67°F=) 50 

+ 125°C(257°I=) 



NOTE: 

Maximum limits indicate where permanent device 
damage occurs. Continuous operation at these limits 
is not intended and should be limited to those con- 
ditions specified in the DC Electrical characteristics. 



DC Operating Characteristics T^ = 0°C to 70°C; Vgg = OV, Vqc = + 5V ± .25V 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


UNITS 


CONDITIONS 


l|L 


Input Leal<age 




10 


mA' 


V,N = Vcc 


loL 


Output Leal<age 




10 


mA 


Vqut = Vcc 


V,H 


input High Voltage 


2.0 




V 




V|L 


Input Low Voltage 




0.8 


V 




VOH 


Output High Voltage 


2.4 




V 


10 = 100/iA 


Vol 


Output Low Voltage 




0.4 


V 


10 = 1.6 mA 


'cc 


Supply Current 
FOR PINS 25, 26,27: 




200 


mA 


All Outputs Open 
See Note 1 


V,H 


input High Voltage 


Vcc 




V 




V,L 


Input Low Voltage 




Vss + 
<0.4V 


V 





AC Timing Characteristics T^ = 0°C to 70°C; Vss = OV, Vcc = +5V ±.25V 



X 



Ao,Ai,A2 STABLE 



-TSETI- 



X 



■V 



Thld' 



LP" 



■''SET2- 



^^ 



-Trc- 



1.' 



-Trdr- 



f*-TDACC -»-' 

< 



""j/^ 



1^ 



DATA VALID 



> 



HOST READ TIMING 



HOST READ TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


UNITS 


CONDITIONS 


*SET1 


ADDR, Set up to RE 


80 




nsec 




*SET2 


OS Set up to RE 







nsec 




<DACC 


Data Valid from RE 




375 


nsec 


Cl =100pF 


*RC 


Read Enable Pulse Width 


.375 


5.0 


/isec 




*DOH 


Data Hold from RE 




150 


nsec 




*HLD 


ADDR. CS, Hold from RE , 







nsec 




*RDR 


Read Recovery Time 


■500 




nsec 





3-54 



Winchester Disk Controller Devices 



X 



Aq, Ai,A2 stable 



-""■SETI- 



"'"SET2 ■ 



K 



THLDI.a 



Nc 



-TWE- 



\XXXXXXXxX^ 



-Tds- 



DATA MUST BE VALID 




o 

o 
en 

o 

C/) 

o 



HOST WRITE TIMING 



HOST WRITE TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


UNITS 


CONDITIONS 


«SETi 


ADDR, Set up to WE 


80 




nsec 




*SET2 


CS Set up to WE 







nsec 




*DS 


Data Bus Setup to WE 


100 




nsec 




*WE 


Write Enable Pulse Width 


200 




nsec 




*DH 


Data Bus Hold from We 


80 




nsec 




*HLDi 


CS Hold from WE 







nsec 




^HLDs 


ADDR Hold from WE 


30 




nsec 




<WER 


Write Recovery Time 


1.0 




fisec 





^^ 



WE 
(OUTPUT) 



>y<l TyvRB » J ^ 



■\ ^ 



■*j — — i 



Tdh- 



•Trr 



>-*v 



BUFFER WRITE TIMING 



BUFFER WRITE TIMING (READ SECTOR CMD) 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


'WRB 


WE Output Pulse Width 




4 




SC 


See Note 2 


tVWE 


Data Set up to WE 




4 




SC 


See Note 2 


tDH 


Data Hold from WE 




4 




SC 


See Note 2 


*RR 


WE Repetition Rate 




16 




SC 


See Note 2 


<WF 


WE Float from BCS 









nsec 





Winchester Disk Controller Devices 



3-55 



o 

o 
en 

o 

CO 

o 



RE - 
(OUTPUT) 



^i^i»— treb Tiyn 



V 



/ 



■i9 



yr 



Trf- 



■Tdoh 






t 



DATA MUST 
BE VALID 



■Trr. 



I 



X^^ 



BUFFER READ TIMING 
BUFFER READ TIMING (WRITE SECTOR CMD) 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


*REB 


RE output Pulse Width 




4 




SC 


See Note 2 


'RDS 


Data Setup to RE 


140 






nsec 




*RR 


RE Repetition Rate 




16 




SC 


See Note 2* 


*DOH 


Data Hold From RE 


80 






nsec 




*RF 


RE Float from BCS 









nsec 





-T 



-tt- 



T|S 



IP OR SEC —'I 
T|C 



II 



I 



-Trc- 






(READ) J|_. 

Toe A, ^ 

DATA ^ 



-Tew- 



y 



(WRITE) 



\ 



-■■"isw 



-^t- 



DISK R/W CONTROL TIMING 
DISK R/W CONTROL TIMING (SCLK = 9.677 MHZ) 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


•IS 


Index/Sector Pulse Width 


.2 


1.25 


3.0 


Msec 




»IC 


Index/Sector to CP1 High 




60 




SC 


See Note 3 


»RC 


CP1 Low from Read Data 




56 




SC 


See Note 3 


•CP 


CP1 Low to CP1 High 




12 




SC 


See Note 3 


•DC 


Last Read Data to CP1 Low 




16 




SC 


See Note 3 


•cw 


CPO High from Read Data 




60 




SC 


See Note 3 


•sw 


Index/Sector High to CPO 
High on FORMAT 






250 


nsec 





3-56 



Winchester Disk Controller Devices 



US3US0 ZZZX! 



VALID 






"TSG- 



USTAG 



X 



IIKZZZZZZ 



TSH 



X 



g 
o 
o 

CO 

o 



UNIT SELECT TIMING 



UNIT SELECT TIMING (SCLK = 9.677 MHZ) 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


<SG 


US3-US0 Setup to USTAG 


1.0 






fisec 




'CG 


CP9 Setup to USTAG 




4 




CLK 


See Note 4 


*UH 


CP9 Hold Time from 














USTAG 




4 




CLK 


See Note 4 


^SH 


US3-US0 Hold Time from 
USTAG 


1.0 






fxsec 





CP9-CP0 



zzzz>c 



2<ZZZ 



■TCT- 



TAG 1, 2 



y? 



•TqW' 



^ 



■Ttc- 



TAG 3 



A 



CP4, 6, 9 . 



X 



TCP- 



X 



CP TAG TIMING 



CP TAG TIMING 9SCLK = 9.677 MHZ) 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


tCT 


CP9-CP0 Set up to 
TAGS 1, 2, or 3 




5 




CLK 


See Note 4 


»6GW 


TAGS 1 & 2 Pulse Width 




4 




CLK 


See Note 4 


»TC 


CP9-CP0 Hold Time from 
TAG 1, 2 Low 




2 




CLK 


See Note 4 


*CP 


CP4, 6, 9 Pulse Width 
During TAG 3 True 




4 




CLK 


See Note 4 



Winchester Disk Controller Devices 



3-57 



READ DATA TIMING 



READ DATA TIMING 



SYMBOL 


CHARACTERISTICS 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


»RF 


RCLK Frequency 


1.0 


9.677 


10.1 


MHZ 




'RR 


Read Data Setup to 
RCLK Low 


35 






nsec 




'RH 


Read Data Hold Time 
from RCLK Low 









nsec 






WRITE DATA TIMING 



WRITE DATA TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


tSF 

'ws 


Servo Clock Frequency 

WD Valid from Servo 
Clock High 


1.0 


9.677 


10.1 
85 


MHZ 
nsec 


Cl = 15 pf. 
See Note 5 



3-58 



Winchester Disk Controller Devices 




BDRQ 



BRDY 



^ 



Trro ^- 



I Tbdbr I Tbrq 

»-• H 



a: 



Tbrdy 



■^ 




a 

o 
o 

CO 

a 



MISCELLANEOUS TIMING 



MISCELLANEOUS TIMING 



MISCELLANEOUS TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


tCF 


Master Clock Frequency 




2.0 


2.5 


MHZ 


50% Duty Cycle 


tMR 


Master Reset Pulse Width 


12 






/isec 


CLK Active 


tBCR 


BCR Pulse Width 




4 




CLK 


See Notes 4&7 


tBRQ 


BDRQ Reset from BRDY 


50 




600 


nsec 




tRS 


Rise of Fall Time 






15 


nsec 


See Note 1 


tBDBR 


BRDY High from 
BDRQ High 


4 








See Note 8 


tBRDY 


BRDY Pulse Width 


4 








See Note 8 



NOTES: 



1. 



It is recommended to buffer the line receiver stage with a TIL or Schottky TTL stage on pins 27, 28 and 
29. A current sink capability of-,48 mA with a 100 ohm pull-up resistor will provide both the required rise 
and fall times and also the required voltage swing. It is recommended to locate these buffers physically 
near the WD 1050 to minimize inductive ringing. 

2. Timing is a function of the Servo Clock (SCLK) frequency. The number of negative SCLK transitions plus 
400 nsec. SCLK periods is specified. (Disregard "TYP" in this case). 

3. Timing is a function of the Servo Clock (SCLK) frequency. The number of negative SCLK transitions plus 
400 nsec. max. is specified. (Disregard the "TYP" in this case). 

4. Timing is a function of the Master Clock (CLK) frequency. The number of CLK periods is specified. (Disregard 
the "TYP" in this case). 

5. WD Is an open drain output and requires an external IK ohm pull-up to Vqc- This pin is inverted relative 
to the SMD interface cable. It is recommended that this output go to the 'D' input of a 74S74 flip-flop that 
is clocked by the SCLK buffer described in Note 1. The 74S74 Q output may then connect to the interface 
line driver. It is recommended that the 74S74 be located physically near the Wd1050. 

6. All AC timing is measured at Vql = 0.8 V, Vqh = 2.0V. 

7. Certain occurrences of BCR can have variable pulse widths. Deactivation of BCR Is dependent upon the 
next occurance of INDX or SCTR for these instances. 

8. Timing is a function of the Master Clock (CLK) frequency. The number of CLK periods, plus 100 nsec. min. 
is specified. 



Winchester Disk Controller Devices 



3-59 



3-60 Winchester Disk Controiier Devices 



WESTERN DIGITAL 

CORPORATION 

WD1050 SMD Controller/Formatter Application Notes 



INTRODUCTION 

Prior to the introduction of 5V* and 8 inch Winchester 
disks drives in the late 1970's, minicomputers and 
mainframes were the only systems that utilized rigid 
disks. These drives vjere relatively expensive; 
sometimes as high as $200 per megabyte. They 
offered the minicomputer designer a fixed or 
removable drive with capacities from 10 to 300 
megabytes. Initially, there was no need for interface 
standards. IBM Corporation was the predominant 
leader in the marketplace, and anyone else who 
decided to build drives were IBM compatible units. 
But as competition increased, more and more com- 
panies began producing lower cost units with 
increased capacity. Minicomputer companies were 
being formed, offering complete systems that were 
non-IBM compatible. The disk drive race was on. 

In order to standardize a common interface and to 
prevent product obsolescence, Control Data Corpora- 
tion developed an intelligent interface called the 
Storage Module Device or SMD. This interface 
allowed a variety of drives to use the same hardware 
signals, even though their capacities and physical 
sizes differed. Variations of the SMD were also 
introduced. Some of these are the CMD (Cartridge 
Module Drive) and the MMD (Memory Module Drive). 
The SMD interface began to gain acceptance in the 
marketplace as competitive manufacturers offered 
"SMD-compatible" drives as well. The SMD was well 
on its way to becoming a defacto standard in the 
industry. Its longevity has been proved by over 10 
years worth of product based on this "intelligent" 
interface. 

With today's smaller diameter low cost drives, where 
does SMD stand? Oddly enough, the higher capacity 
5V4 and 8 inch Winchesters are reviving the SMD pro- 
tocol. Because the SMD interface offers several 
advantages over the ST506 type interface in the high 
capacity arena (such as parallel seek instead of serial 
step pulses), several manufacturers are planning to 
offer the SMD on their traditional small system disk 
drives. The SMD, however, is not a trivial interface 
when it comes down to designing a controller. 

A LOOK AT THE SMD 

Figure 1 illustrates the electrical signals of the SMD. 
Two separate cables are used: one for control and 



one for data. The control cable (commonly referred 
to as the "A" cable) is responsible for all head move- 
ment, status reportings and issuing commands. The 
data cable (or "B" cable) is used for reading and 
writing NRZ data to a particular sector on the drive. 
Note that all lines on both cables are differential 
signals; they require a differential driver/receiver at 
both ends. 

Primary control over the "A" cable is based upon a 
10 bit bus called the Tag Bus. These 10 lines send 
particular information to the driver and initiate a com- 
mand. Three Tag lines (Tag 1-3) are used to tell the 
drive what the bus contains during the strobing of the 
Tags. For example. Tag 1 tells the drive that the Tag 
bus contains a cylinder number that the head 
assemblies should be moved to for reading or writing. 
Tag 2 tells the drive the Head/Volume to select, while 
Tag 3 is used to initiate read or write commands and 
to perform special recovery routines. 

Drives are selected by separate UNIT SELECT lines 
on the "A" cable, which have their own strobe line 
called Unit Select Tag. Other signals on the "A" cable 
serve status reporting type functions. SEEK ERROR 
and ON CYLINDER are examples of status lines. 

The "B" cable is used to transmit serial, NRZ data 
to and from the drive. Associated with the R/W lines 
are clocks: Write Clock for write recovery and Read 
Clock for read recovery. Additional signals aid in 
determining the status of each drive on the bus. 

In a multiple drive configuration, the two cables are 
connected as shown in Figure 2. The "A" cable is 
daisy-chained; each drive is tied together in parallel 
with termination resistors on the last drive. The "B" 
cable is radial-connected; a separate cable from each 
drive connects to the controller. 

It is probably obvious by now that a great deal of con- 
trol is necessary to perform even a simple Read or 
Write operation on the SMD Bus. The drive controller 
must perform simultaneous operations on both 
cables, as well as monitoring status signals to deter- 
mine successful execution of operation. A typical 
SMD controller can consist of 150 SSI/MSI Integrated 
Circuits and a local microprocessor or bit-slice to per- 
form the necessary functions. SMD controller 
designers of today can take advantage of a new LSI 
chip that will reduce the number of l.C.'s to well under 
40. 



O 
o 
o 



Winchester Disk Controller Devices 



3-61 



o 
en 

o 

(fi 
D 





CONTROLLER 


A CABLE 


"-"," + " 


DRIVE 








UNIT SELECT TAG 


22,52 ^ 


I ONE TWISTED PAIR 




UNIT SELECT 20 


23,53 ^ 


UNIT SELECT 21 


24,54 ^ 


UNIT SELECT 22 


26, 56 ^ 


UNIT SELECT 23 


27, 57 ^ 


TAG 1 /2\ 


1.31 ^ 


TAG 2 A 


2,32 ^ 


TAG 3 A 


3, 33 ^ 


BITO A 


4,34 


BIT1 A 


5,35 ^ 


BIT 2 A 


6, 36 ^ 


BIT 3 A 


7.37 ^ 


BIT 4 A 


8,38 ^ 


BIT 5 A 


9,39 ^ 


BIT 6 A 


10. 40 ^ 


BIT 7 A 


11,41 


BITS A 


12, 42 ^ 


BIT 9 A 


13, 43 ^ 


OPEN CABLE DETECTOR 


14,44 


^ INDEX A 


18,48 


^ SECTOR A 


25,55 


^ FAULT A 


15,45 


^ SEEK ERROR A 


16,46 


^ ON CYLINDER A 


17,47 


^ UNIT READY A 


19,49 


^ ADDRESS MARK FOUND A A 


20,50 


^ WRITE PROTECTED A 


28,58 


PICK A A 


29 ^ 


HOLD A 


59 ; 


^ BUSY A 


21,51 


NOT USED (SPARE) 


30,60 



















NOTE: 60 Position 

30 Twisted pair-straight flat cable 
Maximum Length-100 ft. (30.48 meters) 

1 Special signal, not a balanced transmission signal 

2 Gated by unit selected 

3 Not interpreted, is Daisy chained, no driver connection within the LMD 

4 Not activated, is Daisy chained, always a logic zero output if unit is selected 

5 Not generated, is Daisy chained, no driver connection within the LMD 

Figure 1(A). Tag Bus I / O Interface ("A" Cable) 



3-62 



Winchester Disk Controlier Devices 





CONTROLLER 


•■B" CABLE 




DRIVE 








WRITE DATA 


8,20 






GROUND 


7 


WRITE CLOCK 


6,19 


GROUND 


18 


SERVO CLOCK 


2,14 


GROUND 1 


READ DATA 


3,16 


GROUND 


15 


READ CLOCK 


5,17 


GROUND 


4 


SEEK END 


10,23 


UNIT SELECTED 


22,9 


GROUND 


21 


INDEX 


12, 24 


GROUND 


11 


SECTOR 


13,26 


GROUND 


25 

















— 



NOTES: 

1. 26 conductor flat cable. 

Maximum Length-50 ft. (15.24 meters) 

2. No signals gated by "A" cable unit select 

Figure 1 (B). "B" Cable Interface 

NOTES: 

1. Maximum individual A cable lenghts = 100 feet (30.48 meters) 

2. Maximum individual B cable lengfits = 50 feet (15.24 meters) 



a 

o 
en 

o 

C/) 
D 







DAISY CHAINED SYSTEM 










SYSTEM 
GROUND 1 CONTROLLER 1 

A B B 


B B 




< 






V 




















II 


I— 1 


n 




J1 

n r 


J2 


J3 


J1 


J2 


J3 

n P 


J1 


J2 


n 


■■ i> ■■ 

J3 

n P 


J1 

n 


E 
R 
M 


J2 

r 


3 




1 


> — < 


2 


>——< 


3 


>-((-< 


(4 MAX) 





























NOTES: 

1. Termination of "A" cable lines are required at controller and the last unit of the Daisy chain or each unit 
in a radial configuration. 

2. Termination of "B" cable receiver lines are required at the controller and are on the unit' receiver cards. 

3. Maximum cumulative "A" cable length per controller = 100 feet (30.48 meters) maximum individual "B" cable 
lenght = 50 feet (15.24 meters). 

Figure 2. Daisy Chained System 



Winchester Disk Controller Devices 



3-63 



D 

-X 

O 
Ol 

o 

CO 



WD1050 SMD CONTROLLER CHIP 

Western Digital Corporation offers an LSI controller 
chip for the SMD protocol. This device, called the 
WD1050, has been designed to interface an SMD rigid 
disk drive to a 16- bit Host processor. A set of 
macrocommands allows the Host to request a 
specific operation such as seek, read, etc., In which 
all Tag and control lines on the drive interface per- 
form their appropriate signaling. By using this device, 
the designer is free to concentrate on operating 
system software intervention, rather than meeting 
electrical requirements of the drive protocol. Figure 
3 shows the Block Diagram of the WD1050. Data or 
commands are entered in 16-bits through the Data 
I/O Buffers. This information is stored in the Task File 
and tells the device parameters about a specific com- 
mand. This could be a cylinder address, a sector 
number to search for, a particular drive that should 
be selected, etc. After this information is loaded, a 
command is issued. The Control Unit instructs the 
various pins on the drive interface to generate their 
proper signals. Upon completion of a command, the 
WD1050 interrupts the Host and reports via the status 



register if any errors were encountered. The device 
is then ready for the next command. 

Figure 4 illustrates the Task File and its contents. The 
Host processor generates the three address lines 
shown, then performs a read or write operation to the 
selected 16-bit register. All registers can be read or 
written to with the exception of the Command/Status 
Register. Since both of these registers share a com- 
mon address location, a "write" will cause a com- 
mand to execute, while a "read" will cause the status 
to be fetched from the device. This memory mapped 
architecture allows the Host to randomly access any 
location in the Task File without disrupting or 
reloading the data in other registers. 

The Instruction Set of the WD1050 is shown in Figure 
5. Return to Zero, and Seek Cylinder commands are 
used for head movement, while the remaining 
commands are responsible for reading or writing data. 
Each Read/Write command also contains an 
"Implied Seek" feature. This allows the Host pro- 
cessor to issue a read or a write function even though 
the heads are sitting over the wrong cylinder. The 
WD1050 will perform an automatic seek operation 



DO- 
D15 



« 



DATA 

I/O 

BUFFER 



A0-A2 

CS 

RE 

WE 

BOS 

BCR 

BRDY 

BDRQ 

INTRO 



^ 



HOST/ 

BUFFER 

CONTROL 



STATUS 



TASK 
FILE 



COMPARATOR 



DATA 



CRC LOGIC 



CONTROL 
UNIT 



CONTROL 
PORT 



;V>: 



^ CPO- 
10 >cp9 



UNITSEL 
PORT 



^ 



USO- 
US3 



♦-•■ 



RDS 



RDH 



£7 



RC 
RD 



•WD 
SC 



V^ 



DRIVE 

CONTROL 

PORT 



TAG 1- 
TAG3 
INDEX 

• SECTOR 

• FAULT 
SKER 
ONCYL 

■URDY 

• WPROT 
UBUSY 

■USEL 

USTAG 
•ECC 



FIGURE 3. WD1050 BLOCK DIAGRAM 



3-64 



Winchester Disk Controller Devices 



before the actual read or write. Because of this, the 
head movement commands (Return to Zero and Seek 
Cylinders) are usually restricted for use in overlap 
seeks. This is the ability to perform seek operations 
on several drives simultaneously. 

After a command has finished execution, the WD1050 
will report to the Host through its Status Register 
(shown in Figure 6) how successful a command 
execution was. IVlany commands will not execute if 
certain conditions are not met. For example, a FAULT 
condition, shown by status bit 6, will prevent all com- 
mands except Fault Clear from executing. 
Read/ Write commands will not execute if the "On 
Cylinder" bit is false, either. In summary, the Host 
must examine the various bits to determine what 
action to take next. 

HOST SECTOR BUFFER 

Because of the high data rates used on the SMD pro- 
tocol (9.677 Mbits / sec), even a fast micro- processor 
will have trouble keeping up in a Programmed I / O 
environment. For this reason, the WD1050 has been 
designed to use a sector buffer. 

Figure 7 shows a Host Interface to the device using 
a low cost Static RAM and a binary counter. Since 
the WD1050 will be transferring data directly to the 
RAM, a transceiver will be needed to isolate the Host 
from the RAM/WD1050 logic. This transceiver, as 
shown in Figure 7, is disabled by Buffer Chip Select 
(BCS). Whenever BCS is active, the WD1050 is reading 
or writing to the RAM. During this condition, the Host 
cannot read status or any other registers. When the 
data transfer is over, the device disables BCS and 
enables Buffer Data Request (BDRQ). This tells the 
Host that the buffer is now available for use. If a read 
command had been issued, the sector buffer would 
have filled the data requested. 

During this process, the WD1050 takes control over 
Write Enable (WE) by making it an output. It places 
its first data word on the bus and strobes WE. 
This causes a write operation to the RAM and 
increments the binary counter that is tied to the 
RAM's address lines. Another WE strobe then 
occurs, increments the counter again, and the pro- 
cess continues until the sector is transferred. If a 
single sector operation was requested, the WD1050's 
use of the sector buffer is completed. However, multi- 
ple sectors may be transferred as an option within 
the command. In this case, the Buffer Ready (BRDY) 
input to the device is examined, if false, the WD1050 
assumes there is more RAM available and transfers 
the next sector of data. The BRDY signal is normally 
generated by a "carry" or overflow out of the binary 
counter. If BRDY has gone active but the device still 



has more sectors to transfer, BDRQ will be made 
active to allow the Host to unload the data in the 
RAM, making room for the additional sectors. The 
WD1050 will then resume its operation of finding a 
sector and writing the data to the buffer. After all the 
data has been transferred, the command will ter- 
minate. To complete the scheme, a signal called Buf- 
fer Counter Reset (BCR) is used to zero the counters 
before the Host or device starts a transfer. A BCR 
•pulse is generated whenever BCS makes a transition. 

By using this buffer scheme, the designer has the 
ability with one command to transfer the maximum 
number of sectors specified by the Sector Counter 
in the SDH Register. 

CONCLUSION 

Using the WD1050 as the basis for an SMD controller 
design, can reduce the complexity of the design effort 
considerably. However, challenges still remain in 
interfacing the device to maximize the efficiency of 
the interface. The buffer control signals, for example, 
can be changed to accomodate a DMA controller for 
higher throughput. ECC can be appended to the buf- 
fer for data correction purposes. A local micro- 
processor dedicated on the SMD controller board 
could even be used to emulate existing SMD / Host 
software routines. 

Regardless of the application, the WD1050 signifies 
a trend in the semiconductor industry to not only 
replace logic in a discrete design, but to offer com- 
plete functions in large scale integration. This device 
is certainly not the first to offer an LSI functional 
building block, and will not be the last. 



A2 


A1 


AO 


REGISTER SELECTED 




1 
1 
1 



1 

1 

1 







1 


Head Number/Sector Address 
Sector Count/Length/Unit Address 
16 Bit Cylinder Register 
Command Register (Write Only) 
Status Register (Read Only) 



Figure 4. WD1050 Task File 



O 
o 

Ol 

o 
CO 



Winchester Disk Controller Devices 



3-65 



COMMAND 


LSB 








COMMAND REGISTER BITS 










MSB 


15 14 


13 


12 


11 


10 9 8 7 6 5 


4 


3 


2 


1 





Fault Clear 


1 











10 





U 


s 


E 


L 


Return to Zero 


1 





1 


V 


L 1 


M 


U 


s 


E 


L 


Seek Cylinder 


1 


1 





V 


L 1 Z C H 


M 


u 


s 


E 


L 


Read ID Field 


1 


1 


1 


R 


L 1 Z C H 


M 


u 


s 


E 


L 


Read Sector 


1 1 








R 


L 1 Z C H 


M 


u 


s 


E 


L 


Write Sector 


1 1 





1 


R 


L 1 Z C H 


M 


u 


s 


E 


L 


Format 


1 1 


1 





R 


P 1 Z C H 


M 


u 


s 


E 


L 


Verify 


1 1 


1 


1 


R 


P 1 Z C H 


M 


u 


s 


E 


L 



FLAG SUMMARY 


V = Verify 


1 = Interrupt Enable 


R = CRC Enable 


Z = Volume/Head change 


L = Logical Sectoring 


C = Cylinder Address 


P = Programmable Sectors 


H = Head Selection 


= On Cylinder 


M = Marginal Data Recovery 


E = Priority Release/Early 


U = Unit Sel/Servo Minus 


L = Unit Deselect/Late 


S = Priority Sel/Servo Plus 



Figure 5. WD1050 Instruction Set 



BIT 


NAME 


DESCRIPTION 





ID Field Not Found 
(ID/NF) 


Set if the sync character preceding the ID Field or ID Field contents read 
from the disk do not match the respective Task File contents. 


1 


ID CRC Error (IDCE) 


Set if the CRC calculation on the ID Field read from the disk is in error. 


2 


Data Field Not Found 
(DFNF) 


Set if the Data Field sync pattern following the ID Field does not match 
the sync character. 


3 


Data Field CRC Error (DFCE) 


Set if the CRC Calculation on the Data Field read from the disk is in error. 


4 


Not Used 


This bit is not used; it is forced to a zero. 


5 


Buffer Data Request (BDRQ) 


Reflects the Buffer Data Request output. 


6 


Fault (FLT) 


Reflects the status of the Fault (FLT) input. 


7 


Buffer Chip Select (BCS) 


This bit is an inverted copy of the Buffer Chip Select (BCS) output. 


8 


Seek Error (SKER) 


Reflects the status of the Seek Error (SKER) input. 


9 


On Cylinder (OCYL) 


Reflects the status of the On Cylinder (OCYL) input. 


10 


Unit Ready (URDY) 


Reflects the status of the Unit Ready (URDY) input. 


11 


Write Protect (WPRT) 


Reflects the status of the Write Protect (WPRT). 


12 


Unit Selected (USEL) 


Reflects the status of the Unit Selected (USEL) input. 


13 


Unit Busy (UBSY) 


Reflects the status of the Unit Busy (UBSY) input. 


14 


CIP 


Set when a command is in progress. 


15 


Buffer Chip Select 
(BCS) 


This bit is an inverted copy of the Buffer Chip Select (BCS) output. 
This bit also appears in STATUS Bit 7. 



Figure 6. WD1050 Status Register 



3-66 



Winchester Disk Controiier Devices 



Do-Dl5 



HOST 
INTERFACE 



RD 
WR 



DATA REQ 



CHPSEL 
ADDR 






DATA BUS (16) 



1> 



RAM 
BUFFER 



r 



BINARY 
COUNTER 



D0-Di5 



BCR 
BRDY 



RE 
WE 

BDRQ 

CS 

A0-A2 



O 

o 



Figure 7. WD1050 Host Interface 



Winchester Disk Controiler Devices 



3-67 



3-68 Winchester Disk Controiler Devices 



WESTERN DIGITAL 

CORPORATION 

WD1100 Series Winchester Controller Chips 



DESCRIPTION 

The WD1100 Chip series provides a low cost alter- 
native for developing a Winchester Controller. These 
devices have been designed to read and convert an 
MFM data stream into 8-bit parallel bytes. During a 
write operation, parallel data is converted back into 
MFM to be written on the disk. Address Marks are 
generated and detected while CRC bytes can be 
appended and checked on the data stream. The 
WD1100 is fabricated in N-channel silicon gate 
technology and is available in a 20-pin Dual-ln-Line 
package. 

WD1 100-01 SER/PARALLEL CONVERTER 

WD1 100-02 MFM GENERATOR 

WD1 100-12 IMPROVED MFM GENERATOR 

WD1 100-03 AM DETECTOR 

WD1 100-04 CRC GENERATOR/CHECKER 

WD1 100-05 PAR/SERIAL CONVERTER 

WD1 100-06 ECC/CRC LOGIC 

WD1 100-07 HOST INTERFACE LOGIC 

WD110OO9 DATA SEPARATION SUPPORT LOGIC 



FEATURES 

SA1000/ST506 COMPATIBLE 
SINGLE 5V SUPPLY 
TRI-STATE DATA LINES 
5 M BITS/SEC TRANSFER RATE 
SIMPLIFIED INTERCONNECT 

APPLICATIONS 

Winchester Controllers for: 

SHUGART ASSOCIATES 

SEAGATE TECHNOLOGY 

QUANTUM CORP. 

TAN DON MAGNETICS 

MINISCRIBE 

RMS 

CMI . . . AND OTHERS 






o 
o 



CLK [Z ' 

NC C 2 

BCLR CZ 3 

TEST Q 4 

DOO Q 6 

D01 Q^ 6 

D02 Q^ 7 

D03 [^ 8 

D04 [^ 9 

vss C '» 



20 Z] Vcc 
'9 Z] EN 
'8 ^ NRZ 
" Z] ST 
16 ^ DOUT 
15 Z] BDONE 
14 ^ SHFCLK 
13 ^ D07 
12 ^ D06 
,, ~] DOS 



WD11 00-01 

SERIAUPARALLEL 
CONVERTOR 



URZ [Z ' 

SKPEN d 2 

WCLK [Z 3 

WCLK QZ 4 

RWC Q 5 

CS I 6 

DRQCLK [^ 7 

INTCLK [^ 8 

NC [^ 9 

vss iZ '<> 



'" ^ Vcc 

9 ^ AO 

8 m Al 

7 '^ MR 
6 ^ MFM 

5 ^ INTRO 

4 1^ DRQ 

3 ^ EARLY 

2 I] LATE 

, --] NOM 



WD1 100-02 

MFM GENERATOR 



NRZC 

SKPEN [Z 

WCLK [Z 

WCLK [Z 

RWC (Z 

CS [Z 



DRQCLK [Z 

INTCLK [Z 

2XDR [Z 

VssC 



'" Z] Vcc 

19 ;;:]Ao 
18 ;^Ai 
1? Z]f^ 

'6 ^ MFM 
'5 Z INTRQ 
" Zi DRQ 
" Z] EARLY 
12 ^ LATE 
" ^ NOM 



WD1100-12 

IMPROVED MFM 
GENERATOR 



RCLK C 

DIN [Z! 

RCLK I 

CLKIN I 

DOUT C 

NC [^ 

NC C 

TEST1 [Z 

ENDET [Z 

Vss C 



Z] Vcc 

Z] RST 
3 CP 
Z NC 

I AMDET 
Z] AMDET 
ZD QOUT 
Z NC 
^ DCLK 
1^ TEST 2 



WD1 100-03 

AM DETECTOR 



DOCK nz ^ 

SHFCLK r~ 3 

NC Q < 

NC ^ 5 

CWE [Z S 

DOCE [2 ? 

CRCiz CZ 5 

NC [Z 9 

Vss C '" 



ZDVcc 
Z] NC 

^ NC 
Z NO 
^ CRCOK 
Z] TIMCLK 
Z WCLK 
Z CRCOK 
^ SKPCLK 
^ DOUT 



WD11 00-04 

CRC 

GENERATOR/CHECKER 




WD1 100-05 

PARALLEL/SERIAL 
CONVERTER 



WD1 100-06 

ECC/CRC 

LOGIC 



RD6 L 

WR6 L 2 

RESET LZ ^ 

CSAEN L ' 

AMDET in * 

TIMCLK L * 
(— 7 
RCLK I — 

I — 8 

INDEX I — 

wmCZ ' 
VssC '° 



'' =1 Vcc 

'9 Z WCLK 

" Z] CS 

ZJ WAEN 

'^ Z] MODE 

'^ Z) RBS 

" Z] AMOUT 

'^ Z CSAC 

'^ J waTT 

" ^ LINDEX 



WD1 100-07 

HOST INTERFACE 

LOGIC 



Winchester Disk Controller Devices 



3-69 



3-70 Winchester Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD1100-01 Serial/Parallel Converter 






o 
o 



DESCRIPTION 

The WD110(W)1 Serial/Parallel Converter allows the 
user to convert NRZ (non-return to zero) data from a 
Winchester disk drive Into ft-blt parallel form. Addi- 
tional Inputs are provided to signal the start of the 
parallel process, as well as Byte Strobes to signify 
the end of the conversion. The device contains two 
sets of 8-bit registers; one register may be read (in 
parallel), while data is being shifted Into the other 
register. This double-buffering allows the Host to read 
data from the disk drive at one-eighth the actual data 
rate. 



The WD110OO1 Is implemented in NMOS silicon gate "*■ 
technology and Is available in a 20 pin plastic or 
ceramic duai-in-ilne package. 

FEATURES 

SINGLE +5V SUPPLY 
DOUBLE BUFFERING 
BYTE STROBE OUTPUTS 
5MBITS/SEC SHIFT RATE 
SERIAL IN/SERIAL-PARALLEL OUT 
20 PIN DIP PACKAGE 





v-^ 






CLK Q 


1 


20 


ZI 


vcc 


NO Q 


2 


19 


=] 


EN 


BOLR Q 


3 


18 


=] 


NRZ 


TEST Q 


4 


17 


Z] 


ST 


DOO Q 


5 


16 


Zl 


DOUT 


D01 [^ 


6 


15 


Z] 


BDONE 


D02 Q 


7 


14 


z 


SHFCLK 


D03 Ql 


8 


13 


Z] 


D07 


D04 [^ 


9 


12 


z 


D06 


vssd 


10 


11 


z 


DOS 



ST >- 



TEST >■ 



CLK »- 



8 

Bit 
Counter 



rC cp 



D Q 

P LATCH 

R 



i> 



-*■ BDONE 



6 Bit 
Shift Register 



7^ 



-< EN 



■^ bClr 



DOUT 



■*. SHFCLK 



8 Bit Register 



''ttttt TT 

DOO D01 D02 D03 D04 DOS D06 D07 



Figure 1. 
WD1 100-01 Pin Connections 



Figure 2. 
WD1 100-01 Block Diagram 



Winchester Disk Controller Devices 



3-71 



o 
o 



PIN 
NUMBER 


SYMBOL 


NAME 


FUNCTION 


1 

2 

3 

4 

5-9 
11-13 

10 

14 

15 

16 

17 

18 
19 
20 


CLK 
NC 


CLOCK 

NO CONNECTION 
BYTE CLEAR 


NRZ data is entered into the 8-bit shift register on the 
low-to-high transition of clock. 

No connection. This pin is to be left open by the user. 

When this line is at a logic 0, the BDONE (Pin 15) line 
is held reset. 

This pin must be left open by the user. 

8 bit parallel data outputs. 

Ground. 

Inverted copy of CLOCK (pin 1) which is active when EN 
(pin 19) is at a logic 1. 

This signal is forced to a logic 1 signifying 8 bits of data 
have been assembled. BDONE remains in a logic 1 state 
until reset by a logic on the BCLR (pin 3) line. 

Serial Data Output from the 8th stage of the internal shift 
register. DOUT is in a high impedance state whenever 
EN (pin 19) is at a logic 0. 

This line enables the byte counter and is used for syn- 
chronization. It must be held to a logic 1 prior to first 
data bit on the NRZ (pin 18) line. 

NRZ serial data is entered on this pin and clocked by 
the low to high transition of CLK (pin 1). 

When this signal is at a logic 0, DOUT, SHFCLK, 
and BDONE outputs are in a high impedance state. 

-f5V± 10% power supply input. 


BCLR 

TEST 
D00-D07 

Vss 
SHFCLK 

BDONE 

DOUT 

ST 

NRZ 

EN 

Vcc 


TEST INPUT 
DATAO-DATA 7 

GROUND 
SHIFT CLOCK 

BYTE DONE 
DATA OUT 


START 

NRZ DATA 

ENABLE 

Vcc 



DEVICE DESCRIPTION 

Prior to shifting data through the device, the 
WD1 100-01 must be synchronized to the data stream. 
The ST line (Pin 17 high) is used to hold the internal 
bit counter in a cleared state until valid data (NRZ) 
and clocks (CLK) are entered. The ST line is a syn- 
chronous input and therefore requires one full cycle 
of the CLK line (Pin 1) to occur in order to accept a ST 
condition. After this happens, the device is ready to 
perform serial to parallel conversions. 

Data is entered on the NRZ line and clocked into the 
8-bit shjft register on the low-to-high transition of CLK. 
The ST line must be set low during the low time of 
CLK. Data is accepted on low-to-high transition of the 
clock while the high-to-low transition of CLK 
increments the bit counter. After 8 data bits have been 
entered the final high-to-low transition of CLK sets 
an internal latch tied to the BDONE line (Pin 15). At 
the same time, the contents of the shift register are 
parallel loaded into an 8 bit register making the 
parallel data available on the D00-D07 ou tputs. 
BDONE will remain in a latched state until the BCLR 
is set to a logic 0, clearing off the BDONE signal. 
BCLR is a level triggered input and must be set 
back to a logic 1 before the next 8 bits are shifted 
through the register. BCLR has no effect on the serial 
shifting process. When the next 8 bits are received, 



BDONE will again be set and the operation continues. 

When interfacing to a microprocessor, BDONE is 
used to indicate a parallel byte is ready to be read. 
As the pr ocesso r reads the data out of the D00-D07 
lines, the BCLR line should be strobed to clear of 
BDONE in anticipation of the next assembled byte. 
An address decode signal generated at the host may 
be used for this purpose. During a power-up condi- 
tion, the state of BDO NE is indeterminant. It is recom- 
mended that BCLR be strobed low after power-up 
to insure that BDONE is cleared. 

The serial output line from the last stage of the shift 
register is available on the D OUT pin. A n inverted copy 
of CLK is available on the S HFCLK pin. Both 
DOUT (Pin 16) and SHFCLK (Pin 14) can be used 
to drive another shift register external to the device. 

The three signals BDONE, DOUT, and SHFCLK can 
be placed in a high impedance state by setting EN (Pin 
19) to a logic 0. Likewise, EN must be at a logic 1 in 
order for these signals to be active. 

The TEST pin is internally OR'ed with the ST li ne to 
inhibit the bit counter. It is recommended that TEST 
be left open by the user. An internal pull-up resistor is 
tied to this pin to satisfy the appropriate logic level 
required internally for proper device operation. 



3-72 



Winchester Disk Controlier Devices 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature 

under Bias 0°C (32°F) to 50°C (122°F) 

Voltage on any pin 

with respect to Vgs ■ • . .' - 0.2V to + 7.0V 

Power Dissipation 1 Watt 

STORAGE TEMPERATURE 

PLASTiC . . . -55°C (-67°F) to +125°C (257°F) 

CERAMIC . . -55°C (-67°F) to +150°C (302°F) 



NOTE: Maximum ratings indicate operation where 
permanent device damage may occur. Con- 
tinuous operations at these limits is not 
intended and should be limited to those con- 
ditions specified in the DC electrical 
characteristics. 






o 
o 



DC Electrical Characteristics Ta = 0°C (32°f=) to 50°C (122°F); Vqc = + 5V ± 10%, Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


V,L 


Input Low Voltage 


-0.2 




0.8 


V 




V|H 


Input High Voltage 


2.0 






V 




Vo 


Output Low Voltage 






0.4 


V 


Iql = 3.2mA 


VoH 


Output High Voltage 


2.4 






V 


loH = 200mA 


Vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




'cc 


Supply Current 






125 


mA 


All Outputs Open 


l|H 


Input High 






<10 


mA 


V|N = -4 to Vcc 


l|L 


Input Low 






<10 


mA 


V,N = .4 to Vcc 



AC Electrical Characteristics T^ = 0°C (32°F) to 50°C (122°F=), Vcc = 5V ± 10%, Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYP 


MAX 


UNITS 


CONDITION 


fcL 


CLK FREQUENCY 







5.25 


MHZ 






tLS 


ICLK to ST 









nsec 


ST = 


1 (min 200nsec) 


^HS 


tCLK to ST 









nsec 


ST = 


1 (min 200nsec) 


tos 


Data set-up to t CLK 


15 






nsec 






tvB 


BDONE valid from 1 CLK 


65 




140 


nsec 


EN = ■ 




tps 


BDONE reset from BCLR 






135 


nsec 


EN = 




^BW 


BCLR Pulse Width 


50 






nsec 


EN = ■ 




tsc 


t CLK to 1 SHFCLK 






90 


nsec 


EN = - 




tcs 
ho 


I CLK to t SHFCLK 






90 
55 


nsec 
nsec 


EN = ■ 
EN = 




Data delay from t SHFCLK 


tpo 


Enable to DOUT ACTIVE 






90 


nsec 






^DH 


Data Hold w.r.t. t CLK 


45 






nsec 






tcD 


t CLK to DOUT ACTIVE 






145 


nsec 






toF 


Enable to DOUT disable 






90 


nsec 







NOTE: 1. Typical Values are for Ta = 25°C (77°F) and Vcc = +5V±10% 



Winchester Disk Controller Devices 



3-73 






o 
o 



7 12 3 4 5 



CLK 
ST 



NRZ 




DOX ^ X Power-On DATA / byte n-1 

BDONE 



p><^ byte 1 or n 



BCLR 



SHFCLK 



EN 




DOUT "'_'_X"'_\)C1 



FIGURE 3. WD1100-01 FUNCTIONAL TIMING 



3-74 



Winchester Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 



WD1100-03 AM Detector 



o 
o 

■ 

o 

CO 



DESCRIPTION 

The WD1 100-03 Address Mark Detector provides an 
efficient means of detecting Address [Vlarl< Fieids in 
an MFM (NRZ) data stream. MFfvl (NRZ) clocl<s and 
data are fed to the device aiong with a window clock 
generated by an external data separator. The 
WD1 100-03 searches the data stream for a DATA = 
A1, CLK = OA pattern and produces an AM DET 
signal when the pattern has been found. NRZ data 
is an output from the device, which can be used to 
drive a serial/parallel converter. An uncommitted latch 
is also provided for by the data separator circuitry, 
if required. 



The WD1 100-03 Address Mark Detector is fabricated 
in NMOS silicon gate technology and is available in 
a 20 pin dual-in-line package. 

FEATURES 

• SINGLE -I-5V SUPPLY 

• 5 MBITS/SEC DATA RATE 

• DECODES A1 16 0Ai6 

• SYNCHRONOUS CLOCK/DATA OUTPUTS 

• 20 PIN DIP PACKAGE 



RCLK Q 

dTnQ 

RCLK Q 

CLK IN C 

DOUT C 

NC C 

NC Q 

TESfT C 

ENDET C 

Vss C 



Z] Vcc 

I RST 
^ CP 

I NC 

I AMDET 
Z] AMDET 

) QOUT 

I NC 

I DCLK 
"^ TEST 2 



+5V- 



CP 



rClk 



CLK IN >- 



RCLK >~ 



O R 



<♦— O 



D 
t> Q 



■♦" oQDf 



BBrr 

SHIFT REG 



.>. dSDt 



DETECT A1 
DETECT OA 



TEST1 

- DCLK 

- AMDET 
► AMDET 



TEST 2, 



8BIT 
SHIFT REG 



Figure 1. 
WD11 00-03 Pin Connections 



Figure 2. 
WD11 00-03 Block Diagram 



Winchester Disk Controller Devices 



3-75 



o 
o 

I 

o 



PIN 
NUMBER 


SYMBOL 


NAME 


FUNCTION 


1 
3 

2 

4 
5 

6,7,13,17 

8 
11 

9 

10 
12 
14 
15 

16 
18 
19 
20 


RCLK 
RCLK 

DIN 


READ CLOCK 
READ CLOCK 


Complimentary clock inputs used to clock DIN and CLK IN 
into the AM detector. 

MFM data pulses from the external Data Separator are con- 
nected on this line. 

MFM clock pulses from the external Data Separator are con- 
nected on this line. 

Data Output from the internal Data Shift register, synchronized 
with DCLK. 

To be left open by the user. 

To be left open by the user. 

A logic 1 on this line enables the detection logic to search 

or a data Al^g and clock. 

Ground. 


DATA INPUT 


CLKIN 


CLOCK INPUT 


DOUT 
NO 


DATA OUTPUT 
No Connection 


TEST1 
TEST 2 

ENDET 

Vss 
DCLK 


TEST1 
TEST 2 

ENABLE 
DETECTION 

Vss 

DATA CLOCK 


Clock output that is synchronized with DATA OUT (Pin 5). 

Signal output from the uncommitted latch. 

Complimentary Address Mark Detector output. These signals will 
go active when a Data = A^■^g Clock = OA-ig pattern is detected 
in the data stream. 


QOUT 
AMDET 

AMDET 
CP 
RST 
Vcc 


LATCH OUTPUT 


ADDRESS MARK 
DETECT 

ADDRESS MARK 
DbltCT 

CLOCK PULSE 


A low-to-high transition on this line will cause the QOUT (Pin 14) 
to be latched at a logic 0. 


RESET 
Vcc 


A logic on this line will cause the QOUT (Pin 14) signal to be 
set at a logic 1. 

-I-5V ± 10% power supply input. 



DEVICE DESCRIPTION 

Prior to shifting data through the device, the internal 
logic must be initialized. While the ENDET (Pin 9) line 
is at a l ogic 0, shi fting of d ata will be in hibited and 
AMDET, AMDET, CLK, and DATA OUT will remain 
inactive. 

When ENDET is at a log ic 1, shifting is enabled. NRZ 
data is entered on the DIN line (Pin 2 ) and shifted 
on the high-to-low transiti on of RCLK (Pin 1). NRZ 
clocks are entered on the CLK IN line, and shifted 
on the high-to-low transition of RCLK (Pin 3). The 
DOUT line (Pin 5) is tied to the last stage of the 
internal Data Shift register and will reflect informa- 
tion clocked into the DIN line delayed by 8 bits. 

While each bit is being shifted, a 16 bit comparator is 
continuously checking the parallel contents of the 
shift registers for the DATA = A1i6, CLK = OA is pat- 
tern. When this pattern is detected, AMDET will be 
set to a logic and AMDET will be set to a logic 1. 
AMDET and AMDET will remain latched until the de- 
vice is reinitialized by forcing ENDET to a logic 0. 



When an AM is detec ted, DC LK will begin to toggle. 
Data present on the DOUT line may then be clocked 
into an external serial / parallel converter. DCLK will 
remain inactive when ENDET is held at a logic 0. 

An uncommitted edge-triggered flip /flop has been 
provided to facilitate the detection of high frequency 
by the data separator, but may be used for any pur- 
pos e. The low-to-high transition of CP (P in 18) will set 
the QOUT (Pin 14) to a logic 0. QOUT maybe reset 
back to a logic 1 by a low level on the RST line 
(Pin 19). 



TEST 1 and TEST 2 are output lines. TEST 1 is an 
active l ow pulse when an Al-ie is detected, and 
TEST 2 is active low pulse when a GAig is de- 
tected. These signals are used for test points and 
therefore should be left open by the user if not 
required. 



3-76 



Winchester Disk Controller Devices 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature under 

bias 0°C (32°F) to 50°C (122°F) 

Voltage on any pin with 

respect to Vss -0.2 to + 7.0V 

Power Dissipation 1 Watt 



STORAGE TEMPERATURE 

PLASTIC -55°C to + 125°C 

CERAMIC -55°C to + 150°C 

NOTE: Maximum ratings indicate operation where 
permanent device damage may occur. Con- 
tinuous operations at these limits is not 
intended and should be limited to those con- 
ditions specified in the DC electrical 
characteristics. 



o 

o 

I 

o 

CO 



DC Electrical Characteristics T^ = 0°C (32°F) to 50°C (122°F), Vqc = +5V ± 10%, Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


VlL 


Input Low Voltage 


-0.2 




0.7 


V 




V,H 


Input High Voltage 


2.0 






V 




Vol 


Output Low Voltage 






0.4 


V 


Iql = 3.2 mA 


VoH 


Output High Voltage 


2.4 






V 


loH = -200 A 


Vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




'cc 


Supply Current 






125 


mA 


All Outputs Open 


l|H 


Current Input High 






10 


uA 


V,N = -4 to Vcc 


l|L 


Current Input Low 






10 


uA 


Vw = .4 to Vcc 



AC Electrical Characteristics Ta = 0°C (32°F) to 50°C (122°F), Vcc = +5V ± 10%, Vss = OV 



SYMBOL 


PARAMETER 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


tpc 


RCLK FREQUENCY 






5.25 


MHz 




tsT 


Data, CLKIN, RCLK Setup Time 


40 






nsec 




tHT 


Data, CLKIN. RCLK Hold Time 


40 






nsec 




tpD 


1 RCLK to t DCLK 






140 


nsec 




tEM 


ENDET set to AMDET, DOUT, 
DCLK 






100 


nsec 




tRA 


1 RCLK to t AMDET 






115 


nsec 




tpM 


\ RCLK to i AMDET 






125 


nsec 




tRO 


1 RCLK to DOUT 






135 


nsec 




tEA 


i ENDET to AMDET, DOUT, DCLK 






190 


nsec 




tRQ 


1 RST to t GOUT 






110 


nsec 




tpw 


Pulse width of RST 


50 






nsec 




tew 


CP Pulse width 


90 






nsec 




tcQ 


t CP to ; QOUT 






120 


nsec 





NOTE: 1. Typical Values are for Ta = 25°C and Vcc = +5V. 



Winchester Disk Controller Devices 



3-77 



o 
o 

I 

o 

C*9 



ENDET 

RCLK 
DIN 

RCLK 
CLKIN 

TEST 1 
TEST 2 

AMDET 

AMDET 
DOUT 

DCLK 




(AIDFT) 



u~Lri_n_r^' 



Figure 3. WD1 100-03 Functional Timing 



3-78 



Winchester Disk Controller Devices 



WESTERN DIGITAL 

COR. P ORATION 

WD1100-04 CRC Generator/Checker 



o 
o 

o 



DESCRIPTION 

The WDHOCHM CRC Generator / Checker is designed 
to generate a Cyclic Redundancy Checkword from a 
serial data stream, and to check a data stream 
against a known CRC word. Complimentary latched 
"CRCOK" outputs are provided to indicate CRC errors 
in check mode. Additional logic has been included 
to shift the CRC checkword out of the device by 
signals generated on other WD1100 family devices. 

The WD1100-04 is fabricated in NMOS silicon gate 
technology and is available in a 20 pin dual-in-line 
package. 



FEATURES 

• GENERATES /CHECKS CRC 

• SINGLE +5V SUPPLY 

• LATCHED ERROR OUTPUTS 

• X^6 + X12 + x^ 1(CCITT-16) 

• AUTOMATIC RESET 

• 20 PIN DIP PACKAGE 



DIN 
DOCK I 



SHFCLK [3 

NC [^ 

NC C 

CWE Q 

DOCE Q 

CRCIZ d 

NC \Z 

VSS C 



Zl vcc 

I NC 
I NC 
^ NC 
I CRCOK 
I TIMCLK 
I WCLK 
) CRCOK 
I SKPCLK 
I DOUT 



GRG12 >- 



DIN > a 



SHFCLK 



D 8 



CC Q 



'SKPCLK 



D POLYNOMIAL GEN q 

j^16^ X''2 + X^+ 1 



DOCE >- 



DOCK >- 



D Q 
Q 



[P^ 



DOLfr 



■♦- CWE 



^ CRCOK 

K q ) , CRCOK 



WCLK 



16 



■♦■ TIMCLK 



Figure 1. 
WD1 100-04 Pin Connections 



Figure 2. 
WD11 00-04 Block Diagram 



Winchester Disk Controller Devices 



3-79 



o 
o 

■ 

o 



PIN 
NUMBER 


SYMBOL 


NAME 


FUNCTION 


1 
2 

3 


DIN 




Active low serial Input data stream is used to 
generate/check the 2 byte CRC word. 

After a byte of data has been transfeived in, this 
input signal is used to latch the state of DOCE in 
an internal D flop with a high to low transition. 

The falling edge shifts data bits into the CRC 
aenerator/checker. It also transfers the CRC check 


DATA INPUT 


DOCK 


DATA OR CRC 
WORD CLOCK 


SHFCLK 


SHIFT CLOCK 


word to DOUT in the write mode (DDCE = LOW). 
The rising edge also activates the CRCOK lines in 
the read mode when no error is found. 


4,5 
6 


N.C. ^ 
CWE 


NO CONNECTION 


This active low output indicates that the CRC 
checkword is being output on the DOUT line. 
When CWE is high, data is being output on DOUT. 


CHECK WORD 
ENABLE 


7 


DOCE 


DATA OR CRC 
ENABLE 


Initially, this input line is held high to direct input 
data (pin 1) to the output data (pin 11). After the next 
to the last BYTE is transmitted but before the last 
BYTE occurs DOCE must be low to direct the 2 CRC 
check bytes to DOUT (pin 11). 


8 






DOCE must be maintained low for a minimum of 
2 byte times. DOCE is used only in the write mode. 

When this line is at a logic 0, the SKPCLK output 
line is held high and the CRC generator is held 
preset to hex "FFFF." 


CRCIZ 


CYCLIC 
REDUNDANCY 
CHECK INITIALIZE 


9 


N.C. 


NO CONNECTION 




10 
11 


Vss 


GROUND 


GROUND. 

In the write mode, this line outputs the unmodified 
data stream along with the 2 byte CRC word 
appended to the end of the stream. 


DOUT 


DATA OUTPUT 


12 


SKPCLK 


SKIP CLOCK 


The first high-to-low transition on DIN (pin 1) re- 
sets SKPCLK low and enables the CRC to e ther 
generate or check the CRC word. 


13 


CRCOK 


CYCLIC 
REDUNDANCY 
CHECK OKAY 


In the read mode, after the 2 byte CRC word is 
entered on DIN and no error has been detected, 
this line is set high to indicate no errors have 
occurred. This line will then remain high as long as 
DIN is maintained high. 


14 


WCLK 


WRITE CLOCK 


This input clock is divided by 16 to produce TIMCLK 
(pin 15) and has no effect on the rest of the internal 
circuitry. 


15 
16 


TIMCLK 


TIMING CLOCK 


See WCLK (pin 14). 

Complementary output version of CRCOK (pin 13). 


CRCOK 


CYCLIC 
REDUNDANCY 
CHECK OKAY 


17-19 


N.C. 


NO CONNECTION 




20 


Vcc 


Power Supply 


-f5v ± 10% power supply. 



3-80 



Winchester Disk Controlier Devices 



DEVICE DESCRIPTION 

Prior to shifting data through the device (either in the 
read or write modes) the CRC ge nerator/checker is 
initialized by strobing the CRCIZ (pin 8) low. This 
forces the SKPCLK (pin 12) line to the high state. The 
first low going transition on DIN (pin 1), namely the 
most significant bit of an address mark, resets the 
SKPCLK line. The WD1 100-04 has now been properly 
initialized and is ready t o genera te/check the CRC 
bytes. The CRCOK and CRCOK lines should be set 
to their inactive states. 

In the write mode , initia lly the DOCE (pin 7) is held 
high and pseudo DOCK is produced by supplying a 
string of zeros before the address mark. This ensures 
the proper state of the in ternal D flip flop to gate input 
data to the output line DOU T (pin 11). As shown in 
the block diagram the CWE (pin 6) will be set high. 
Somet ime between the next to the last and the last 
DOCK that indicates the end of the data stream, 
DOCE (pin 7) is lowered to ensure the smooth transi- 
tion of the 2 byte CRC checkword to the output line 
DOUT (pin 11). 

DOCE must be maintained low for a minimu m of 2 
byte times. After the CRC word is generated, DOUT 
will produce a string of zeroes (i.e., held high). This 
portion of the circuitry is dormant in the read m ode. 
After proper initialization, input data is entered on DIN 
(pin 1) along with the 2 byte CRC word for the read 



mode of operation. At the end of the data stream, if 
no errors were detected the CRCOK (pin 13) is set 
high. Accordingly the complimentary output (pin 16) 
is set lo w. Th ese output states will be maintained as 
long as DIN is held high and CRCIZ (pin 8) is not 
strobed. If the CRCOK lines do not become active, 
an error has been detected and a retry is in order. If 
successive re-tries fail, an error flag may be set to 
determine a further course of action as desired by 
the user. 

WCLK is divided by 16 to produce TIMCLK which may 
be used as a buffered step clock for SA1000 compati- 
ble drives. 

SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature under 

Bias 0°C (32°F) to 50°C (122°F) 

Voltage on any pin 

with respect to Vgs -0.2V to -t- 7.0V 

Power Dissipation 1 Watt 

STORAGE TEMPERATURE 

PLASTIC -55°C (-67°F) to + 125°C (257°F) 

CERAMIC . . . .-SS-'C (-67°F) to + 150°C (302°F) 

NOTE: Maximum ratings indicate operation where 
permanent device damage may occur. Con- 
tinuous operations at these limits is not 
intended and should be limited to those con- 
ditions specified in the DC electrical 
characteristics. 






o 
o 

o 



DC Electrical Characteristics T^ = 0°C (32°F) to 50°C (122°F); Vcc = +5V ± 10%, Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYP^ 


MAX 


UNIT 


CONDITIONS 


V|L 


Input Low Voltage 


-0.2 




0.8 


V 




V,H 


Input High Voltage 


2.0 






V 




Vol 


Output Low Voltage 






0.4 


V 


Iql = 3.2 mA 


VoH 


Output High Voltage 


2.4 






V 


loH = -200fiA 


Vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




'cc 


Supply Current 






125 


mA 


All Outputs Open 


l|H 


Current Input High 






<10 


uA 


V,N = -4 to Vcc 


l|L 


Current Input Low 






<10 


uA 


V,N = .4 to Vcc 



AC Electrical Characteristics Ta = 0°C (32°F) to 50°C (122°F); Vcc = 5V ± 10%, Vgs = OV 



SYMBOL 


PARAMETER 


MIN. 


TYP1 


MAX. 


UNITS 


CONDITION 


twT 


t WCLK to i TIMCLK 






140 


nsec 




tzs 


CRCIZ i to t SKPCLK 






120 


nsec 




tzK 


CRCIZ pulse width 


90 






nsec 




tss 


DOCE set up time w.r.t. 
i DOCK 


20 






nsec 




tsH 


DOCE hold time w.r.t. 


40 






nsec 




too 


i DOCK 






105 


nsec 


CWE set high 


DIN to DOUT delay 



Winchester Disk Controller Devices 



3-81 



o 
p 

o 



SYMBOL 


PARAMETER 


MIN. 


TYP^ 


MAX. 


UNITS 


CONDITION 


^DK 


i DIN to i SKPCLK 






120 


nsec 




^DW 


DIN P.W. to reset SKPCLK 


50 






nsec 




tie 


i DOCK to t CWE 






120 


nsec 




ho 


SHFCLK to DOUT 






150 


nsec 




^BC 


IDOCK to tCWE 






120 


nsec 




fsc 


SHFCLK frequency 






5.25 


MHz 




tsR 


t SHFCLK to t CRCOK 






85 


nsec 




he 


tSHFCLK to \ CRCOK 






90 


nsec 




t|N 


i DOCK to i DIN 






90 


nsec 





NOTE: 1. Typical Values are for Ta = 25°C (77° F) and Vqc = +5.0V 




CRCOK 



Figure 3. 
WD11 00-04 Write Mode 



CRCIZ 

SKPCLK - 
DIN 


—t^r- 




—1 l*-tzs 


-, 


— 1 1 


*-.tDK 


— L 





Figure 4. 
WD11 00-04 initialize 



3-82 



Winchester Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 



WD1100-05 Parallel/Serial Converter 



o 
o 

I 

o 
en 



DESCRIPTION 

The WD1 100-05 Parallel/Serial Converter allows the 
user to convert a byte of data to a serial stream when 
writing to a disk or any serial device. Parallel data is 
entered via the D0-D7 lines on the rising edge of 
DCLK. A synchronous BYTE counter is used to sig- 
nify that 8-bits of data have been shifted out and that 
the 8-bit latch is ready to be reloaded. The double 
buffering of the data permits another byte to be 
loaded while the previous byte is in the process of 
being shifted. 

The WD1 10005 is implemented in NMOS silicon gate 
technology and is available In a 20-pin plastic or 
ceramic dual-In-line package. 



FEATURES 



• SINGLE -h5V SUPPLY 




• DOUBLE BUFFERING 




• BYTE STROBE OUTPUTS 




• 5 M BITS/SEC SHIFT RATE 




• TRI-STATE OUTPUT CONTROL 


• PARALLEL IN/SERIAL OUT 




• 20 PIN DIP PACKAGE 






v^ 




DO Q 


1 20 


Zlvcc 


Did 


2 19 


ZlEN 


D2 Q 


3 18 


11^ NC 


D3 [^ 


4 17 


ZH TEST 


D4 Q 


5 16 


ZD BDONE 


D5|Z 


6 15 


m DOUT 


D6 1 


7 14 


1 SHFCLK 


D7[Z 


8 13 


=]LD 


SHFCLK [Z. 


9 12 


1 WCLK 


VssC 


10 11 


~1 DCLK 


Figure 1. 




WD110( 


3-05 Pin Connections 



^ 



-dD Q 

a err 



L 



TEST 



BYTE 
COUNTER qU 4— olc 



_y^ 



L 



a err shift 

REG 



SHFCLK 
SHFCLK 



m >- 



-►ld 



Figure 2. 
WD1100-05 Block Diagram 



Winchester Disk Controller Devices 



3-83 



o 



o 
cp 

o 
ai 



PIN NUMBER 


SYMBOL 


NAME 


FUNCTION 


1-8 


D0-D7 


DATA 0-DATA 7 


8-bit parallel data inputs (bit 7 = MSB). 


9 


SHFCLK 


SHIFT CLOCK 


Inverted copy of WCLK (pin 12) which is active when 
ENABLE (pin 19) Is at a logic 0. 


10 


Vss 


GROUND 


GROUND. 


11 

12 

13 
14 


DCLK 


DATA CLOCK 


Active low input signal resets the BDONE (pin 16) latch. 
The low-to-high (trailing edge) clocks the Input data Into 
the Internal 8-blt latch. 

The high-to-low (1) edge of this clock signal is used to 
shift the data out serially. The low-to-high (t) edge Is used 
to update the Internal byte counter (module 8). 

This active low signal indicates that the Byte Counter 
is being preset to 1. Normally left open by the user. 

Delayed copy of WCLK (pin 12) which is active when 
EN (pin 19) Is at a logic 0. 


WCLK 
LD 


WRITE CLOCK 


LOAD 


SHFCLK 


SHIFT CLOCK 


15 


DOUT 


DATA OUT 


Serial data output enabled by EN (pin 19). 


16 
17 


BDONE 


BYTE DONE 


This output signal is forced to a logic 1 whenever 8 
bits of data have been shifted out. BDONE remains in 
this state unless reset by the loading of another byte of 
data. 

This pin must be left open by the user. 


TEST 


TEST INPUT 


18 
19 


NC 
EN 


No Connection 
ENABLE 




This active low signal enables DOUT, SHFCLK, 
SHFCLK, and BDONE outputs. When high, these output 
signals are in a high impedance state. 


20 


Vcc 


Vcc 


-i-5 ± 10% power supply input. 



DEVICE DESCRIPTION 

Prior to loading the WD1 100-05, It is recommended 
that OOH (or FF) be loaded into the Input buffers to 
ensure that DOUT is at a fixed level. EN (pin 19) is 
set to a logic to enable the device outputs. 

Data is entered on the D0-D7 Input lines and is 
strobe d into th e data latches on the rising edge of 
DCLK (pin 11). DCLK also resets BDONE (pin 16). 
The first BDONE that comes up simply means that 
the WD1 10005 is ready to accept another byte of data 
and that the previous byte entered is in the process 
of being shifted out. If the BDONE is serviced prior 
to every 8th WRITE CLOCK pulse the output data will 
represent a contiguous block of the bytes entered. 
Due to the asynchronous nature of the WD1 100-05, 
the Input data will be available in serial form at the 
output anywhere from 8 to 16 write clock cycles later. 

Dat a is shi fted out on the hIgh-to-low (I) transition of 
the WC LK (pin 12). The low-to-high (t) transition of 
WCLK increments a byte counter which in turn sets 
the BDONE signal high after 8 bits of data have been 
shifted out. The low-to-high transition of BDONE also 
causes the loading of the data buffer into the shift 
register. The data buffer is now ready to be reloaded 
with the next byte. 

The loading of the next byte automatically clears the 
BDONE signal. The entire process as outlined above 
is repeated_BP0NE always needs to be serviced 
within 8 WCLK cycles unless the next byte to be 



transmitted is the same as the previous byte. 

Four signals, BDONE, DOUT, SHFCLK, and SHFCLK, 
can be placed in a high impedance state by setting 
EN (pin 19) to a logic 1. Likewise, EN must be at a 
logic In order for these signals to drive any exter- 
nal device. 



The TEST pin Is internally OR'ed with the counter 
output to produce the LD (pin 13) signal. This is 
used to inhibit the bit counter by extern al mea ns for 
test purposes. It is recommended that TEST be 
left open by the user. An internal pull-up resistor is 
tied to this pin to satisfy the appropriate logic level 
required for proper device operation. 

SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature 

under Bias 0°C (32°F) to 50°C (122°F) 

Voltage on any pin 

with respect to Vss -0.2V to +7.0V 

Power Dissipation 1 Watt 

STORAGE TEMPERATURE 

PLASTIC -SSOC (-67°F) to + 125°C (257°F) 

CERAMICS -55°C (-67°F) to + 150°C (302°F) 

NOTE: Maximum ratings indicate operation where per- 
manent device damage may occur. Continuous opera- 
tion at these limits is not intended and should be limited 
to those conditions specified in the DC electrical 
characteristics. 



3-84 



Winchester Disk Controller Devices 



DC Electrical Characteristics: Ta = 0°C (32°F) to 50°C (122°F), Vqc = ±5V ±10%, Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYP^ 


MAX 


UNIT 


CONDITION 


V|L 


Input Low Voltage 


-0.2 




0.8 


V 




V,H 


Input High Voltage 


2.0 






V 




Vol 


Output Low Voltage 






0.4 


V 


Iql = 3.2 mA 


VOH 


Output High Voltage 


2.4 






V 


loH = 200 mA 


Vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




'go 


Supply Current 






125 


mA 


All Ouputs Open 


l|H 


Current Input High 






<10 


mA 


V,N = -4 to Vcc 


IlL 


Current Input Low 






<10 


mA 


V,N = -4 to Vcc 



o 
o 

■ 

o 
en 



AC Electrical Characteristics: T^ = 0°C (32°F) to 50°C (122°F); Vcc = + 5 ± 10% Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYP^ 


MAX 


UNIT 


CONDITION 


^A/C 


WCLK frequency 






5.25 


MHZ 


50% duty cycle 


*DW 


DCLK pulse width 


50 






nsec 




<DS 


Data set-up w.r.t. t DCLK 


30 






nsec 




*DH 


Data hold time w.r.t. t DCLK 


50 






nsec 




*DB 


i DCLK to i BDONE 






160 


nsec 


EN = 


*D0 


i WCLK to DOUT 






130 


nsec 


EN = 


^SH 


1 WCLK to i SHFCLK 






75 


nsec 


EN = 


*HS 


t WCLK to t SHFCLK 






70 


nsec 


EN = 


*WB 


t WCLK to t BDONE 






180 


nsec 


EN = 


»ES 


1 EN to BDONE, DOUT 
SHFCLK ACTIVE 






90 


nsec 




'CL 


t WCLK to i LD 






150 


nsec 





NOTES: 1. Typical Values are for T^ = 25°C (77°F) and Vcc = + 5-OV 




WCLK 



DCLK 



Figure 3. 
WD1100-05 Functional Timing Diagram 



Winchester Disk Controller Devices 



3-85 



3-86 Winchester Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD1100-06 ECC/CRC Logic 






o 



FEATURES 

• 32-BIT COMPUTER SELECTED POLYNOMIAL 

• SINGLE BURST CORRECTION TO 8 BITS 

• MULTIPLE BURST DETECTION 

• PROGRAMMABLE CORRECTION/DETECTION SPAN 

• CRC OR ECC SOFTWARE SELECTABLE 



DATA TRANSFER RATES TO 5.25 M BITS/SEC 
SERIAL CHECK/SYNDROME BIT PROCESSING 
128, 256, 512 BYTE SECTOR SIZES 
SINGLE +5V SUPPLY 
TTL, MOS COMPATIBLE 
20 PIN DIP PACKAGE 



DESCRIPTION 

The WD1 100-06 ECC/CRC logic chip gives the user 
of the WD1100 series of chips easy ECC or CRC 
implementation. With proper software, it will provide 
single burst correction up to 8 bits and double burst 



detection. The computer selected polynomial has 
been optimized for Winchester 5 1/4" and 8" drives 
with sector sizes up to 512 bytes. 



R/w| 

RCPQ 
WOP I 

rdatCZ 



wdatI 
selQ 



ECCIZ [~ 
NCd 



ECCEN I 

VssC 



^Vcc 
IWBS 

]rbs 
Idcss 



EDOUT 



fpOUT 
]FBD 
]CSE 
I BS 



Irwcp 



SEL 



ECCIZ *- 
DCSS >■ 



R/W »- 



RCP »— 
WCP »— O 



RDAT •— O 

WDAT »— O 

RBS »^-0 

Wbs»— O 



MUX 



COMROL 



O-^ DOUT 



EDOUT 
D-»- CSE 

BS 



[>-•- ECCEN 
0-*- FBD 



-► RWCP 



SHIFT REGISTER 
Do Q3I 



-^ 



Figure 1. 
WD1 100-06 CONNECTIONS 



Figure 2. 
WD1 100-06 BLOCK DIAGRAM 



Winchester Disk Controller Devices 



3-87 



WD1 100-06 ECC/CRC DEVICE PIN DESCRIPTION 



PIN 
NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


1 

2 

3 

4 
5 
6 

7 

8 
9 

10 
11 

12 

13 

14 

15 
16 


READ/WRITE 


R/W 

RCP 
WCP 


Input line used to select the data, clock and CRC/ECC 
strobe during read/write operations. When low input 
signals WDAT, WCP, and WBS are selected. When high 
input signals RDAT, RCP, and RBS are selected. 

Input pulse used by the internal shift registers to 
compute the 4 syndrome bytes. 

Input pulse used by the internal shift registers to 
compute the 4 check bytes. 

Serial data input during a read operation. 

Serial data input during a write operation. 

This input is used to select either the CRC or the ECC 
polynomial for error detection/correction. SEL = ECC 
polynomial selected. SEL = 1 CRC polynomial selected. 

Input used to preset ail the internal shift registers. Out- 
put lines FBD, EDOUT, DOUT, and CSE will be in their 
inactive high states. The first low going edge of either 
RDAT or WDAT signals the activation of all internal 
circuitry. 

No connection. 

When low, the ECC/CRC process is enabled. When high, 
this output signal indicates that the process is disabled. 

Ground. 

Output clock pulse during read or write operations. The 
input clock pulses RCP and WCP are multiplexed on 
this output line for use by any support logic. 

The input signals RBS and WBS are gated with the 
appropriate clocks and multiplexed as an output on the 
byte sync line. Normally not used by the user. 

When high, this output indicates that the device is in 
the process of computing the check/syndrome bytes and 
that EDOUT and DOUT lines contain data information. 
When low, the device puts CRC or ECC check/syndrome 
bits on the output data lines. 

The feedback line to the shift registers is brought out as 
an output line for test purposes. Normally left open by 
the user. 

Output data line carries data or CRC/ECC information 
depending upon the state of DCSS. 

Unlatched output data line available 1 clock period earlier 


READ CLOCK 
PULSE 


WRITE CLOCK 
PULSE 


READ DATA 


RDAT 


WRITE DATA 
SELECT 


WDAT 
SEL 


ECC INITIALIZE 
NO CONNECTION 


ECCIZ 
N/C 


ECC ENABLE 
GROUND 


ECCEN 
VSS 


READ/WRITE 
CLOCK PULSE 


RWCP 

BS 

CSE 

FBD 


BYTE SYNC 


CLOCK SELECT 
ENABLE 


FEEDBACK 


DATA OUTPUT 


DOUT 


EARLY DATA 


EDOUT 


than DOUT. 



3-88 



Winchester Disk Controller Devices 



WD11 00-06 ECC/CRC PIN DESCRIPTION (CONTINUED) 



PIN 
NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


17 

18 
19 
20 


DATA/CHECK 
SYNDROME SELECT 


DCSS 

RBS 
WBS 
VCC 


Data or check/syndrome select input line. When high, 
data is output on the data lines; when low, CRC or check 
syndrome bits are output depending upon which 
poiynomiai selected. DCSS goes low sometime between 
the last and the next to the last data byte transferred 
to/from the disk provided all set-up and hold-times have 
been met. DCSS must stay low for at least 2-byte times 
when the CRC polynomial selected and it must stay low 
for at least 4 byte times if the ECC polynomial is selected. 

Input used to latch the state of DCSS during the read 
mode. 

Input used to latch the state of DCSS during the write 
mode. 

+ 5V±10% 


READ BYTE 


WRITE BYTE 
+ 5V 



DEVICE DESCRIPTION 

To ensure c orrect operation of the WD110OO6 device, 
the ECCIZ line is strobed to preset the poiynomiai 
generator shift register, and reset the Data/Check- 
Syndrome select flip-flop. The 32-bit shift register 
string is preset to avoid all zero check bytes. The 
DCSS line is held high and appropriate signals are 
then applied to the rest of the inputs. Since most disk 
media use an Address mark of A1 (or IV1.S.B. set), 
advantage is taken of this feature to start off the 
ECC/CRC calculation on the data/ID fields 
automatically. The first active low going edge on the 
inpu t data li nes releases the internal SET Fiip-Flop. 
The ECCEN output line is set low indicating that the 
internal circuitry is ready to begin the computation 
of the ECC/CRC bytes. Immediately following the 
Address mark, data is supplied in a serial fashion. 

Sometime before the last byte of data and after the 
next to the last byte of data is transferred through 
this device, the DCSS line is set low. Since data is 
generally serialized/deserialized before/after process- 
ing by the WD1 100-06 device, the byte-sync pulses 
can be easily obtained from those devices marking 
the byte boundaries. T he byte -sync pulses are inter- 
nally ANDED with the RWCP line to ensure 
the smooth transition of checks/syndrome bytes on 
the DOUT output line only after the last bit of data 
has been entered into the device. A one bit tim e delay 
through a D Flip-Flop has been added on the DOUT 
line to deglitch this output line. 

During a WRITE operation, the input data stream is 
divided by the polynomial X^^ + x^^ + x^^ + x^Q + 
Xi7 + xi° + X^ + 1 and the 32-bit remainder 
obtained is used as the 4 check syndrome bytes. If 
the syndrome is zero, no errors occurred. Otherwise, 
the non-zero syndrome is used by a software 
algorithm to compute the displacement and the error 
vector within the bad sector. To protect the integrity 



of the ID field only a CRC check should be performed 
over this field. No attempt ought to be made to cor- 
rect data in the ID field. The CRC polynomial 
implemented is the standard CCiTT QO^ + X^^ + x^ 
+ 1.) Although either polynomial may be used for 
both fields, the use of the CRC polynomial for the ID 
fields is recommended since it only requires 2 bytes 
instead of 4. 

POLYNOMIAL SELECTION 

For disk media, polynomial selection has a signifi- 
cant influence on data accuracy. Fire code 
polynomials have been widely used on OEM disk con- 
trollers, but provide less accuracy than properly 
selected computer generated codes. 

For fixed, guaranteed correction and detection spans, 
data accuracy may be highly dependent on 
polynomial selection. Some polynomials, fire codes 
for example, are particularly susceptible to miscor- 
rection on common disk type errors, while others, 
computer generated polynomials for example, can be 
selected to be less susceptible. Computer generated 
codes do not have the pattern sensitivity of the fire 
code and the miscorrection patterns are more ran- 
dom in nature. 

iVlore than 20,000 computer generated random 
polynomials of degree 32, each with 8 feedback temns, 
were evaluated in order to find the polynomial 
described in this specification. 

SELECTING THE CORRECTION SPAN 

The code described in this document can be used to 
correct up to 8-bits. 

Any correction span from 1 to 8 may be selected. 
However, for best data accuracy, the lowest correc- 
tion span should be used that meets the correction 
requirements for the disk drives supported. 



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Winchester Disk Controller Devices 



3-89 



o 
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I 

o 



For most Winchester media, a 5-bit correction span 
is adequate. 

Tlie correction span may liave to be longer if the drive 
uses a read/write modulation method that maps a 
single media bit in error into several decoded bits in 
error. Examples of read/write modulation methods of 
this type would be GCR and 2,7 code. 

PROPERTIES OF THE POLYNOMIAL 

The following polynomial was computer selected for 
insensitivity to short double bursts, good detection 
span and 8 feedback terms. 

Forward polynomial is: 

X32 + x28 + X26 + X19 + X^^ + X^° + X^ + X2 + 

0. 

Reciprocal polynomial is: 

X32 + x30 + X26 + X22 + X^^ + x^^ + X^ + X^ + 

XO. 
Properties* 

1. Maximum record length (r) = 526x8-bits (in- 
cluding check bits) 

2. Maximum correction span (b) = 8-bits 

3. Degree of polynomial (m) = 32 

4. Single burst detection span without correction = 
32 bits.(Detection span when the code is used for 
detection only) 

5. Single burst detection span with correction (d) - 
(Detection span when the code is used for 
correction) 

= 19 bits for b = 5 and r = 526x8 
= 14 bits for b = 8 and r = 526x8 
= 20 bits for b = 5 and r = 270x8 
= 14 bits for b = 8 and r + 270x8 

6. Double burst detection span without correction - 
(Double burst detection span when code is used 
for correction) 

= 3 bits for b = 5 and r = 526x8 
= 2 bits for b = 8 and r = 526x8 
= 4 bits for b = 5 and r = 270x8 
= 2 bits for b = 8 and r = 270x8 

7. Non-detection probability = 2.3E-10. 

8. Miscorrection probability - 

= 1.57 E-5 for b = 5 and r = 526x8 
= 1.25 E-4 for b = 8 and r = 526x8 
= 8.00 E-6 for b = 5 and r = 270x8 
= 6.40 E-5 for b = 8 and r = 270x8 

NOTE:* 

You should not use this polynomial for a record length 

of correction span beyond the maximum specific 

above. 



SOFTWARE REQUIREMENTS 

The software algorithm, developed by the user, uses 
the syndrome to detect an error, generate a correc- 
tion pattern and a displacement vector or to deter- 
mine if uncorrectable. In the correction algorithm, a 
simulated shift register is used to implement the 
reciprocal polynomial. The simulated shift register is 
loaded with the syndrome and shifted until a correc- 
table pattern is found or the error is determined to 
be uncorrectable. Both forward and reverse 
displacements are computed. 

Either the serial or the parallel algorithm may be 
implemented by the user. In almost all cases the 
serial software algorithm is the most applicable. Addi- 
tionally, 1K of table space is required if the parallel 
software algorithm is selected. It is assumed that the 
highest order bit of a byte is serialized and 
deserialized first. 

CORRECTION TIME PERFORMANCE 

All real time operations are performed with error cor- 
rection hardware. The software algorithms used get 
involved only after an error has been detected. 

The following correction times are for a serial type 
algorithm such as that used on the WD1001: 

a) Standard microprocessor = 30 to 60 milliseconds 

b) Bit slice = 6 to 12 milliseconds 

c) 8X300 (used on WD1001) = 15 to 30 milliseconds 

DATA ACCURACY 

ERR (Error Recovery Procedure) strategies have a 
significant influence on data accuracy. An ERP 
strategy requires data to be re-read before applying 
correction and results in much better data accuracy. 
The WD1001 employs such a strategy. This strategy 
reduces the possibility of passing undetected 
erroneous data by rereading until the error goes away, 
or until there has been a consistant error syndrome 
over two previous rereads. 

Another technique that can be used to give data a 
higher probability of recovery is write check: read back 
after write. Since write check affects performance, it 
should be optional. Alternate sector assignment and 
defect skipping are some of the other techniques that 
may be implemented by the user if so desired. 



3-90 



Winchester Disk Controller Devices 



SELF-CHECKING WITH MICROCODE 

Periodic microcode and/or software checl<ing is 
another approach that can be used to iimit the 
amount of undetected erroneous data transferred in 
case of an ECC circuit failure. Microcode or software 
diagnostics could be run on subsystem power up and 
during idle times. These diagnostics would force ECC 
errors and check for the proper syndrome and pro- 
per decoding of the syndrome by the correction 
routine of the operational microcode. 

To do this, simply use a long bit in the READ and 
WRITE commands to the disk. This bit can then be 
used to suppress the transfer of check/syndrome 
bytes on the output data line by letting the DCSS line 
stay high during ECC TIME. The complete procedure 
is summarized below. 

1. WRITE: Pass all data to the disk and generate 4 
check bytes at the end of the data field. 

2. READLONG: Do not generate the syndrome, 
instead copy the 4 check bytes as data and pass 
them unaltered to the Host. Now the Host may 
induce errors anywhere in the data stream as long 
as the induced error does not exceed the correc- 
tion span of the polynomial generator. 



3. WRITELONG: Write the data and check bytes sup- 
plied by the Host to the disk. Prevent WD1 100-06 
from generating check bits by not asserting DCSS 
during transfer. No check bytes will be recorded. 

4. READ: Read data and generate the syndrome in 
a normal manner. The software algorithm can now 
be invoked to correct the induced error. 

To aid in detection of certain hardware failures, it is 
desirable to have non-zero check bytes for an all zeros 
record. This feature has been incorporated into the 
circuit defined in this specification. 



Ambient Temperature under Bias 0°C (32°F) to 

50°C (122°F) 
Voltage on any pin with 

respect to Vss -0.2V to -f7.0V 

Power Dissipation 1 Watt 

Storage Temperature 

Plastic ...... .-55°C (-67°F) to + 125°C {257°F) 

Ceramic -55°C (-67°F) to -i- 150°C (302°F) 






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Winchester Disk Controller Devices 



3-91 



o 
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o 



SPECIFICATIONS NOTE: 

Maximum ratings indicate operation where perma- 
ABSOLUTE MAXIIVIUM RATINGS nent device damage may occur. Continuous opera- 

Ar„i,i«r.t T«rv,r,«r-,t..r« ■.r,^«r Dior. rtoo /oooc\ *^ tlons at tfiese llmlts Is not Intended and should be 

Ambient Temperature under Bias. .. .0"C (32"F) to ,. .... .. j-*- -x- ^ ■ *i. r^<-» 

50°C C\22°F) limited to those conditions specified in the DC 

Voltage on any pin with °P^''^t'"9 characteristics. 

respect to Vgs -0.2V to + 7.0V 

Power Dissipation 1 Watt 

Storage Temperature 

Plastic -55°C (-67°F) to + 125°C (257°F) 

Ceramic -55°C (-67°F) to + 150°C (302°F) 

DC Operating Characteristics T^ = 0°C (32°F)to 50°C (122°F), Vqc = +5V ± 10%, Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYPI 


MAX 


UNIT 


CONDITIONS 


V,L 


Input Low Voltage 


-0.2 




0.8 


V 




V,H 


Input High Voltage 


2.0 






V 




Vol 


Output Low Voltage 






0.4 


V 


loL = 3.2 mA 


VOH 


Output High Voltage 


2.4 






V 


loH = -200mA 


Vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




'cc 


Supply Current 




75 


150 


mA 


All Outputs Open 


l|H 


Current Input High 






<10 


uA 


V|N = -4 to Vcc 


l|L 


Current Input Low 






<10 


uA 


V|N = -4 to Vcc 



ECCIZ PULSE WIDTH 



R/W 



3( 



HIGH FOR READ 



LOW FOR WRITE 



X 



ECCIZ ^» ] \ *-^ 

-H h^ tiE 



ECCEN 



RDAT • 
WDAT 



RCP 
WCP 



tST 



tHT 



fCP 



AC Electrical Characteristics T^ = 0°C (32°F) to 50°C(122°F), Vcc = +5V ± 10%, Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYP^ 


MAX 


UNIT 


CONDITIONS 


fcp 


Clock Frequency 






5.25 


IVIHz 




tiz 


ECCIZ Pulse Width 


100 






nsec 




t|E 


ECCIZI to ECCEN t 






100 


nsec 




tsT 


R/WDAT Setup Time 


100 




1 Clock 
Period 


nsec 




tHT 


R/WDAT Hold Time 









nsec 





3-92 



Winchester Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD1100-07 Host Interface Logic 



a 



o 
o 

o 



FEATURES 

SINGLE +5V SUPPLY 
WAIT SIGNAL GENERATION 
TIMING CLOCK GENERATION 
INDEX PROPAGATION 
CARD ACCESS CONTROL 
COMPLIMENTS ECC ARCHITECTURE 
20 PIN DIP PACKAGE 



DESCRIPTION 

The WD1100-07 Host Interface Logic chip simplifies 
the design of a Winchester Hard Disk Controller using 
the WD1100 chip series. It does this by performing 
logic functions that would otherwise require con- 
siderable discrete logic. Additionally, there are signals 
provided for ECC implementation. 

The WD1100-07 is implemented in NMOS silicon gate 
technology and is available in a 20-pin plastic or 
ceramic Dual-in-Line package. 



























CONTROL 
LOGIC 










V 












WCL1 Q 

WCL2 [^ 

RESET L_ 

SACEN CI 


1 
2 
3 
4 
5 
6 
7 
8 
9 
10 


20 
19 
18 
17 
16 
15 
14 
13 
12 
11 


Hvcc 

13 WCLK 

i^cs 

^ WHEN 

Urcp 
IDrbs 




Cb ^^~ 


\j 










y 








-^ 16 


AMDET [Z 
TIMCLK CI 

rclkC 

INDEX I_l 
LINR Q 

VsslZ 


WCLK ^^— 






u 


nc^cT 1*- < 


Z\ AMOUT 
13 CSAC 












A 






D S 

> LATCH Q 
R 


_JWAIT 

I]lindex 




*« 




















I 








- 






BYTE COUNTER 

AND 

DELAY 






y 






AMDET >►— 


c 


3 


1^ AMUUI 


V 

















Figure 1. 
WD1100-07 PIN CONNECTIONS 



Figure 2. 
WD1100-07 BLOCK DIAGRAM 



Winchester Disk Controller Devices 



3-93 



PIN 
NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


1 
2 
3 
4 
5 

6 

7 

8 

9 

10 
11 

12 

13 

14 

15 

16 

17 

18 
19 

20 


WAIT CLEAR 1 


WCL1 


This input presets a WAIT latcli to a non-WAIT condi- 
tion on the failing edge. 

This input presets a WAIT latch to a non-WAIT condi- 
tion on the failing edge. 


WAIT CLEAR 2 


WCL2 


RESET 


RESET 


An input used to set TIMCLK & reset WAIT, AMOUT 
and RBS. 

This is an input signal that is used to enable card 
select for host access. 

An input that must go active when a DATA = A1(HEX) 
or clocks OA(HEX) pattern is detected in the data 
stream. 

An output used to provide reference timing signals to 
SA100 type drives. 

This input, the same as used to clock in data and clocks 
to the AM detector, is used to produce AMOUT. 

This input is provided by the drive once each revolution 
of the disk. 

An input used to reset LINDEX. 
Ground. 


SELECT ADDRESS 
ENABLE 


SACEN 


ADDRESS MARK 
DETECT 

TIMING CLOCK 

READ CLOCK 


AMDET 

TIMCLK 
RCLK 


INDEX PULSE 


INDEX 

LINR 

Vss 
LINDEX 


LINDEX RESET 
GROUND 
LATCHED INDEX 


An output that is INDEX delayed by one clock time. 

This output goes true when controller is internally 
accessing data or has not accepted data from the host 
during a WRITE. 

An output that is the result of CS qualified with 
SACEN. 


WAIT 

CARD SELECT 
ADDRESS 


WAIT 
CSAC 


ADDRESS MARK 
DELAYED OUTPUT 


AMOUT 

RBS 

RCP 


This output is a delayed version of AMDET. 

This output strobes once for each byte of READ data, 
initialized by AMDET. 

This output is delayed from RCLK through propagation. 
Not normally used. 

An input that is used to enable the internal WAIT 
circuitry. 

An input from host that selects controller. 

This input is used to produce TIMCLK on low to high 
transitions. 

+ 5V±10%. 


READ BYTE STROBE 
READ CLOCK PULSE 


WAIT ENABLE 


WAEN 

CS 
WCLK 

Vcc 


CARD SELECT 
WRITE CLOCK 

+ 5VDC 



DEVICE DESCRIPTION 



Upon power up or reset, WAIT, AMOUT, and RBS 
are reset and TIMCLK is set. This is the only interac- 
tive signal between the four sections of the chip. Each 
section will be described separately. 

Control Logic 



This secti on provides WAIT (pin 12) and CS AC (pin 
13). WAIT is set in its active low state when WAEN 
(pin 17) is active low by the failing edge of CS (pin 
18). WAIT is reset by the failing edge of either WCL1 



or WCL2 depending on whether in a read or write 
mode. CSAC (pi n 13) i s enabled by setting SACEN 
(pin 4) lo w afte r WAIT ha s been enabled. CSAC is 
reset by WCL1 or WCL2. 

Timing Clock 

TIMCLK (pin 6) is a divided by sixteen version of 
WCLK (pin 19). It is used with SA1000 type drives. 

Index Pulse 



Lindex (pin 11) is a delayed versi on of INDEX (pin 
8). It remains high until reset by LINR (pin 9). 



3-94 



Winchester Disk Controller Devices 



Read Byte Sync 

RBS (pin 15) will go true on the eigl ith nega tive go- 
ing transiti on o f RCLK (pin 7) after AMDET (pin 5) 
goes true. RBS will remain true for one clock cycle. 

Read Clock Pulse 

RCP (pin 16) is a delayed version of RCLK and is nor- 
mally left open by the user. 

Address Mark Delayed Output 



AMOUT (pin 14) is the same as AMDET delayed by 
two clock times. 

These circuits were developed to work with the other 
chips in the WD1100 series. They are used on the 
WD1001 the timing relationships must be observed. 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature 

under Bias 0°C (32°F) to 50°C (122°F) 

Voltage on any pin 

with respect to Vgs -0.2V to +7.0V 

Power Dissipation 1 Watt 

Storage Temperature 

Plastic . . . .-55°C (-67°F) to + 125°C (257°F) 
Ceramic . . .-55°C (-67° F) to + 150°C (302° F) 

NOTE: 

Maximum ratings indicate operation where perma- 
nent device damage may occur. Continuous opera- 
tion at these limits is not intended and should be 
limited to those conditions specified in the DC elec- 
trical characteristics. 



O 

o 
o 

■ 

o 



DC Electrical Characteristics Ta = 0°C (32°F) to 50°C (122°F); Vqc = +5V ±10%, Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYP1 


MAX 


UNIT 


CONDITIONS 


V,L 


Input Low Voltage 


-0.2 




0.8 


V 




V,H 


Input High Voltage 


2.0 






V 




Vol 


Output Low Voltage 






0.4 


V 


Iql = 3.2 mA 


VOH 


Output High Voltage 


2.4 






V 


loH = -200/iA 


Voc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




'go 


Supply Current 






125 


mA 


All Outputs Open 


l|H 


Current Input High 






<10 


uA 


V|N = -4 to Vcc 


IlL 


Current Input Low 






<10 


uA 


V,N = .4 to Vcc 



AC Electrical Characteristics Ta = 0°C (32°F) to 50°C (122°F); Vcc = 5V ±10%; Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYP^ 


MAX 


UNIT 


CONDITIONS 


^wc 


WCLK FREQUENCY 






5.25 


MHz 




tow 
tws 


CSi to WAITi 




50 
170 


160 
195 


nsec 
nsec 




WCL1lorWCL2Uo WAITt 


tsu 
tsc 


WAEN Setup Time 
SACENI to CSACt 


50 


5 


70 


nsec 
nsec 




WAIT TRUE 


tos 


WCL1lorWCL2ICSACI 




45 


155 


nsec 


WAIT TRUE 


w 


WCLKt to TIMCLKt 






250 


nsec 




tu 


index; to LINDEXt 




50 


100 


nsec 




^LW 


LINRi to LINDEXI 




30 


100 


nsec 




tpc 


RCLKI to RCPi 




30 


75 


nsec 




tRA 


AMDET Setup Time 




30 
2 CLOCK 


50 
2 CLOCK 


nsec 




^AM 






CYCLES 


CYCLES 

+ 45 


nsec 




AMDETI to AMOUTI 








8 CLOCK 


8 CLOCK 












CYCLES 


CYCLES 


nsec 




^BS 


RCLKI to RBSI 




+ 165 


90 


nsec 




tpB 


RBS Period 




1 CLOCK 
CYCLE 









■"NOTE: Typical Values are for Ta = 25°C (77°F) and Vcc = +5V 



Winchester Disk Controller Devices 



3-95 



WAEN 



CS 



WAIT 



tsu- 



♦cw 



1 



*ws- 



or WCL2 






u 
















SACEN 






tsc— ^ 


1 
1 


tcs-*J 


r* — 

1 





CSAC 



WCLK 



TIMCLK 



twT- 



i^— ^J fwc 



INDEX 



LINDEX 

Dnr 



tLI- 



tLW- 



u 



RCP 



RCLK 


tpc-»J, \^- 

1 

tRA -*J |-*- 




T_ 


1 — 1 1 — 1 _ 


', 








AMDET 








"4*AM-»- 














AMOUT 














RBS 




tBS 












1^ 


^ 


-^tRB*- 





3-96 



Winchester Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD1100-09 Data Separator Support Logic 



GENERAL DESCRIPTION 

The WD1100-9 Data Separator Support Logic, when 
used with the other chips in the WD1100 series, 
greatly reduces the external discrete logic required 
to design a Winchester hard disk data separator. The 
chip provides the pump signals to an external error 
amplifier, control signals to an internal bus and a 
special drive selection signal also to an internal bus. 



The WD1100-09 is fabricated in NMOS silicon gate 
technology and is available in a 20 pin plastic or 
ceramic package. 

FEATURES 

• SINGLE +5V SUPPLY 

• DRUN GENERATION 

• DATA SEPARATION CONTROL SIGNALS 

• 20 PIN DIP PACKAGE 



o 

o 

I 

o 



dataQ 


1 


refCI 


2 


dinC 


3 


080 CI 


4 


DRS1 [Z 


5 


hifrqCZ 


6 


DRS2CI 


7 


DRUNl_ 


8 


DOUTQ 


9 


VssC 


10 



-s-y 



20 
19 
18 
17 
16 
15 
14 
13 
12 
II 



Hvcc 

I] RGATE 
^DMR 
^DRS4 
m WRITE 
II]DRS3 

ZJds 

HJWDAT 
13 DOWN 

;;^up 



DRS1 



DRS2 



DRS3 



DRS4 



DIN 
OSC 



DMR 

DATA 

RGATE 

WDAT 

WRITE 

REF 




DRIVE 

SELECTED 

LOGIC 



DS 



PUMP 
LOGIC 



UP 
DOWN 



DATA 

SEPARATOR 

CONTROL 

LOGIC 



DRUN 
DOUT 
HIFRQ 



Figure 1. 
WD1100-09 Pin Connections 



Figure 2. 
WD1100-09 Blocl( Diagram 



Winchester Disk Controller Devices 



3-97 



o 
o 

o 

CO 



PIN 
NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


1 


READ DATA 


DATA 


Input that Is used in DRUN generation. 


2 


REFERENCE 


REF 


An Input that is 2 times the data rate that keeps the VCO 
on center frequency during non-read times. 


3 


DELAYED DATA IN 


DIN 


This input is a delayed version of DOUT. An extemal delay 
line is used. The signals are compared to provide pumps. 


4 

5,7, 
15,17 


OSCILLATOR 


OSC 


An input from the external VCO that is used in pump 

development. 

Input signals indicating which drive has been selected. 


DRIVE SELECT 1- 
DRIVE SELECT 4 


DRS1- 
DRS4 


6 
8 


HIGH FREQUENCY 


HI FRO 


Output to controller microprocessor that indicates 16 
ones or zeroes have been entered on the DATA line. 
Output that Indicates to the controller microprocessor the 
completion of 16 ones or zeroes on the data line. Used 
to switch from REF to DATA via firmware. 


DATA RUNNING 


DRUN 


9 


DATA OUT 


DOUT 


OutDut data line. Can be REF or DATA or WDATA deoen- 
ding on the condition of WRITE, DME and RGATE. 


10 


GROUND 


Vss 


Ground. 


11 


UP PUMP 


UP 


An output that Indicates REF is leading DATA. Goes to 
error amp. Open collector. 


12 


DOWN PUMP 


DOWN 


An output that indicates DATA is leading REF. Goes to 
error amp. Open collector. 


13 


WRITE DATA 


WDATA 


MFM Write data input. Output appears at DOUT. 


14 
16 
18 


DRIVE SELECTED 


DS 


An output that indicates that one of four drives have been 

selected. 

This Input is active during a write operation and enables 

WDAT. 


WRITE MODE 

DATA MASTER 
RESET 


WRITE 
DMR 


This input is used to provide time-out for DRUN and HIFRQ 
in the event that 16 ones or zeroes are not present. 


19 


READ GATE 


RGATE 


This input, usually provided by the controller microproces- 
sor, places chip in read mode. 


20 


+ 5VDC 


Vcc 


-f5VDC = 10%. 



DEVICE DESCRIPTION 

The WD1 100-09 is divided into three sections. Each 
section will be described separately. 

Drive Select Logic 



DS (pin 14) wi ll go active high if any input DSR1 
through DRS4 (pins, 5, 7, 15, 17) are active low. 

Pump Logic 

Internal logic causes the UP (pin 11) and the DOWN 
(pin 12) to be set, initially to their inactive states. DIN 
(pin 3) is the delayed data developed by passing DOUT 
through a delay line. OSC (pin 4) is the output of the 
data separator VCO. Whichever reaches the pump 
logic first will determine whether UP PUMP or DOWN 
PUMP is produced. These signals are then sent to 
an external error amplifier and used for VCO correc- 
tion. During a write, the DIN must be locked to a 
crystal oscillator clock and will hold the VCO on 
frequency. 



Data Separator Control Logic 

Read Mode 

In order to prevent the extemal VCO from locking onto 
a harmonic of its operating frequency, REF (pin 2) is 
provided with a signal twice t he data rate that is 
crystal controlled. With WRITE (pin 6) and RGATE 
(pin 19) inactive, this signal will appear at DOUT (pin 
9). This signal is applied to the pump logic (see above). 

The switching function is Initiated Immediately after 
RGATE goes true. DMR (pin 18) will be set active as 
a result of high frequency pulses applied to an exter- 
nal one shot whose pulse width is such that its out- 
put is a single stretched pulse. The high frequency 
pulses are applied to th e DATA (pin 1) line and aft er 
16 consecutive pulses, DRUN (pin 8) and HIFRQ 



3-98 



Winchester Disk Controller Devices 



(pin 6) go true. At this point REF is switched out and 
the DA TA stream is switched in and appears at POUT. 
DRUM is reset when RGATE goes inactive and HiFRQ 
goes inactive when DMR goes inactive. 

WRITE MODE 



When WRITE (pin 16) goes active, REF is switched 
out and WDAT (pin 13) will appear at DOUT. Since 
WDAT is a crystal controlled signal (usually the MFM 
write data); the VCO is held locked and will not drift. 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature 

under Bias 0°C (32°F) to 50°C (122°F) 

Voltage on any pin with 

respect to Vgs -0.2V to + 7.0V 

Power Dissipation 1 Watt 

STORAGE TEMPERATURE 

Plastic -55°C (-67°F) to + 125°C (257°F) 

Ceramic -55°C (-67°F) to + 150°C (302°F) 

NOTE: Maximum ratings indicate operation where 
permanent device damage may occur. Continuous 
operations at these limits is not intended and should 
be limited to those conditions specified in the DC 
Electrical Characteristics. 



o 
o 

I 

o 

CO 



DC Operating Characteristics T^ = 0°C (32°F) to 50°C (122°F), Vqc = +5V 10%, Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYpi 


MAX 


UNIT 


CONDITION 


VlL 


Input Low Voltage 


-0.2 




0.8 


V 




V,H 


Input High Voltage 


2.0 






V 




Vol 


Output Low Voltage 






0.4 


V 


Iql = 3.2mA 


VoH 


Output High Voltage 


2.4 






V 


loH = -200nA 


Vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




Ice 


Supply Current 






125 


mA 


All Outputs Open 


l|H 


Current Input High 






<10 


mA 


V,N = -4 to Vcc 


l|L 


Current Input Low 






<10 


mA 


V|N = -4 to Vcc 



NOTE: UP and DOWN are open collector outputs and provide 12mA Iql @ -SV. 



Winchester Disk Controller Devices 



3-99 



READ MODE 



DMR 



■€f- 



d™ __jiJijmrLJinjiJiJiJiJiJuiriTXJinJi^ 

tDD -*^ I-* ■ 



DRUM 

RGATE 
HIFRQ 

DOUT 
WRITE 



4ir 



tHD 






i_r 



-f ^ 



-REF- 



DATA- 



■^j-« REF 



JinnnnnnnjuinnnnnnnnnnnniminjlJiiiruiflrL^^ 



Ire 



WRITE MODE 
DMR 



DATA 



DRUM 



HIFRQ 



WRITE 



■REF- 



■DATA- 



DOUT 



TnjinnnnnnnjiJiJLrL_rL_rL_n_n_rLri 



AC Electrical Characteristics Ta = 0°C (32°F) to 50°C (122°F); Vqc = 5V ± 10%; Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYP^ 


MAX 


UNIT 


CONDITION 


^DD 


DATA to DRUM 






170 


nsec 




^DR 


RGATE to DRUN 






90 


nsec 




^HD 


DMR to HIFRQ 




2 TIMES 


90 


nsec 




tRE 


REF frequency 




DATA RATE 


10 


MHz 





3-700 



Winchester Disk Controiier Devices 



WESTERN DIGITAL 

CORPORATION 

WD1100-12 Improved MFM Generator 






o 

o 



to 



DESCRIPTION 

The WD1 100-12 Improved MFM Generator converts 
NRZ data into an MFM (Modified Frequency Modu- 
lated) data stream. The derived MFM signal contain- 
ing both clocks and data can then be used to record 
information on a Winchester Disk Drive utilizing this 
recording technique. In addition to an MFM output, 
the device generates first level Write Precompensa- 
tion signals for use with inner track densities. A 
unique feature of the WD1 100-12 is the ability to de- 
lete a clock pulse in the outgoing MFM stream in 
order to record Address Marks. 



The WD1 100-12 is fabricated in NMOS silicon gate 
technology and Is available in a 20-pin plastic or 
ceramic dual-in-line package. 

FEATURES 

• SINGLE +5V SUPPLY 

• 5M BIT/SEC DATA RATE 

• WRITE PRECOMPENSATION 

• ADDRESS MARK GENERATION 



NRzC 1 
SKPEN[^ 2 

wclkCI 





ZIdrq 
II]early 

I LATE 



RWC 



NRZ 



WCLK 



WCLK) 



4 BIT 

SHIFT 

REG. 



2XDR 



1 



WRITE 

PRECOMP 

GEN. 



MFM GEN 



SKPEN 



-►EARLY 

■NOM 

■LATE 



■MFM 



"SKIP" 
LOGIC 



WD1100-12 
Figure 2. Block Diagram MFM Generator 



DRQCLK »- 







<3 


D S C) 

► CP 
R 


y- 


— ► 






1 






INTCLK> 






■^^^1 








|C 


D 13 
►CP 
R 


















DECODE 
LOGIC 






. _ 






A1» 
CS> 






















MR» 








-^ 


1 


-J 





DRQ 



INTRQ 



Figure 1. 
WD1100-12 Pin Connections 



Figure 3. 
WD1100-12 Block Diagram Interrupt Control Logic 



Winchester Disk Controller Devices 



3-101 



PIN 








NUMBER 


SYMBOL 


NAME 


FUNCTION 


1 


NRZ 




NRZ data Input that is strobed into the MFM 


NON-RETURN-TO 






ZERO 


generator by WCLK(i). 


2 


SKPEN 


SKIP ENABLE 


This input arms the SKIP logic for recording 
Address Marks when set to a logic 1. 


3 


WCLK 


WRITE CLOCK 


Complimentary clock inputs. NRZ data is 
clocked into the MFM Generator on the high- 


4 






to-low transition of WCLK 
(pin 3). 


WCLK 


WRITE CLOCK 


5 


RWC 


REDUCED WRITE 


This signal when high, enables EARLY, LATE 


9 




CURRENT 
2 TIMES 


and NOM outputs. 

This input is used to latch EARLY, LATE, NOM 


2XDR 






DATA RATE 


and MFM outputs. 


10 


Vss 


Vss 


Ground. 


11 


NOM 


NOMINAL 


Output signal from the Write Precompensation 
Logic used to signify that data is to be written 
nominal. 


12 


LATE 


LATE 


Output signal from the Write Precompenstion 
Logic used to signify that data is to be shifted 
LATE before writing. 


13 


EARLY 


EARLY 


Output signal from the Write Precompensation 
Logic used to signify that data is to be shifted 
EARLY before writing 


16 


MFM 


MFM DATA 


This output contains the MFM encoded data 


6 


CS 




derived from the NRZ (pin 1) line. 

Low input signal used to enable the Address 


CHIP SELECT 


8 






decode logic. 

A low on this line will latch the INTRQ (pin 15) 


INTCLK 


INTERRUPT 


7 




REQUEST CLOCK 
DATA REQUEST 


at a logic 0. 

A low on this line will latch the DRQ (pin 14) at 


DRQCLK 


15 




CLOCK 
INTERRUPT 


a logic 0. 

This output is latched at a logic when INTCLK 


INTRQ 






REQUEST 


(pin 8) goes/ is low. 


14 


DRQ 


DATA REQUEST 


This output is latched at a logic when 


17 


MR 




DRQCLK (pin 7) goes/ is low. 

A low level on this line causes DRQ and INTRQ 


MASTER RESET 








to set at a logic 1. 


18,19 


Ao,Ai 


ADDRESS 0,1 


When CS is low and the address lines go high, 
INTRQ is cleared; if the address lines go low 
then DRQ gets cleared, (i.e. set at a logic 1). 


20 


Vcc 


Vcc 


+ 5V 2 10% power supply input. 



DEVICE DESCRIPTION 

The WD1 100-12 is divided into two sections: MFM 
Generator and Interrupt Logic. The MFM Generator 
converts NRZ data into MFM data and provides Write 
Precompensation signals. The Interrupt Logic is used 
specifically on the WD1000 Winchester Controller 
Board and may be used in similar designs to generate 
Interrupt signals. The two sections of the device are 
isolated and have no common input or output signals. 



Prior to entering data, the SKPEN line must be set 
to a logic to enable only clocks in the data stream. 
Data is entered on the NRZ line and strobed on the 
high-to-low transition of WCLK. The encoded NRZ 
data appears on the MFM (pin 16) output lagging by 
one clock cycle. 

Write Precompensation signals EARLY, LATE, and 
NOM are generated as each data or clock pulse 
becomes available at the input when RWC is logic 1. 



3-102 



Winchester Disk Controller Devices 





LAST DATA SENT 


SENDING 


TO BE SENT 
NEXT 


EARLY 


LATE 


NOM 


X 1 


1 





H 


L 


L 


X 


1 


1 


L 


H 


L 








1 


H 


L 


L 


1 








L 


H 


L 


ANY OTHER PATTERN 






L 


L 


H 



o 
o 



ro 



DEVICE DESCRIPTION (CONTINUED) 

The SKPEN signal is used to record a unique 
data/ clock pattern as an Address Mark, using Aiie 
data with OA-ie clock. This pattern is used for syn- 
chronization prior to data or ID fields that are read 
from the disk. 

When the SKPEN signal is set to a logic 1, the inter- 
nal skip logic is enabled. As long as zeroes are being 
shifted into the NRZ line, the device generates nor- 
mal MFM data. On receipt of the first non-zero bit 
(typically the MSB of the A1-,6 the skip logic begins 
to count WCLK cycles. When the MFM generator tries 
to produce a clock between data bits 2 and 3, the skip 
logic disables the MFM generator during that time. 
The result for A1i6 data is a clock pattern of OAie 
instead of 0Ei6- Although other data paterns may be 
used, the MSB of the pattern must be a 1 (80i6 or 
higher) in order to enable the skip logic at the proper 
time. After the skip logic has performed, it then 
disables itself and MFM data is recorded normally 
starting with the succeeding byte. To re-enable the 
skip logic again, the SKPEN line must be strobed. 

The In terrupt Logic is used to clear D ata Requests 
(PRO) and Interrupt Requests (INTRO) by selecting 
OS (pin 6) in combination with Aq and A-,. Th e MR 
(Ma ster Re set) signal is used to clear both DRQ 
and INRQ simultaneously. 



MR 


Ai 


Ao 


cs 


DRQ 


INTRO 





X 


X 


X 


H 


H 




X 


X 


1 


Qn 


Qn 













H 


Qn 




1 


1 





Qn 


H 




1 








Qn 


Qn 







1 





Qn 


Q 



X = Don't care 

Qn = remains at previous state 



DRQ an d INTRQ can be set to a logic only by a low 
level or DRQCLK and INTCLK respectively. The signal 
will remain at a logic un_til_cleared by a MR or pro- 
per address selection via 08, Ai, and Aq. 



Winchester Disk Controller Devices 



3-103 






O 

o 



ro 



NOTE: Maximum ratings indicate operation wlien 
permanent device damage may occur. Con- 
tinuous operation at these limits is not 
intended and should be limited to those 
conditions specified in the DC Electrical 
Characteristics. 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature 

under Bias 0°C (32°F) to 50°C (122°F) 

Voltage on any pin 

with respect to Vgs -0.2V to + 7.0V 

Power Dissipation 1 Watt 

STORAGE TEIVIPERATURE: 

PLASTIC. . . . .-55°C (-67°i=) to +125°C (257°F) 
CERAMIC. . . .-55°C (-67°F) to +150°C (302°F) 

DC Electrical Characteristics Ta = 0°C (32°F) to 50°C (122°F); Vqc = +5V ±10%; Vgs =0V 



SYMBOL 


PARAMTER 


MIN 


TYPi 


MAX 


UNIT 


CONDITION 


V,L 


Input Low Voltage 


-0.2 




0.8 


V 




V|H 


input High Voltage 


2.0 






V 




Vol 


Output Low Voltage 






0.4 


V 


loL = 3.2mA 


VoH 


Output High Voltage 


2.4 






V 


loH = -200f/A 


Vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




'cc 


Supply Current 






125 


mA 


All outputs open 


llH 


Current Input High 






<10 


mA 


V|N= .4 to Vcc 


l|L 


Current Input Low 






<10 


ixk 


V,N= .4 to Vcc 



AC Electrical Characteristics Ta= 0°C (32°F) to 50°C (122°F); Vcc = +5V ±10%; Vgs = OV 



SYMBOL 


PARAMTER 


MIN 


TYP^ 


MAX 


UNIT 


CONDITION 


tpR 


WCLK FREQUENCY 






5.25 


MHZ 




tos 


Data Setup w.r.t.lWCLK 


10 






nsec 


"Per Figure 4" 


^DH 


Data hold w.r.t.lWCLK 


25 






nsec 


"Per Figure 4" 


tjM 


t2XDR to t MFM 






115 


nsec 


"Per Figure 4" 


^MR 


Master reset pulse width 


50 






nsec 


"Per Figure 5" 


^MD 


iMR to tDRQ 






150 


nsec 


"Per Figure 5" 



3-104 



Winchester Disk Controller Devices 



SYMBOL 


PARAMTER 


MIN 


TYPI 


MAX 


UNIT 


CONDITION 


twi 


IMR to tINTRQ 






150 


nsec 


"Per Figure 5" 


^DQ 


DRQCLK pulse width 


50 






nsec 


"Per Figure 7" 


tlQ 


INTCLK pulse width 


50 






nsec 


"Per Figure 8" 


*DD 


iDRQCLK to DRQ 






120 


nsec 


"Per Figure 7" 


t|| 


4INTCLK to INTRQ 






120 


nsec 


"Per Figure 8" 


Ud 


lAX to tDRQ 






145 


nsec 


"Per Figure 6" 


tAI 


t AX to tINTRQ 






160 


nsec 




tcD 


iCS to tDRQ 






145 


nsec 


"Per Figure 6" 


tci 


ICS to tINTRQ 






180 


nsec 


"Per Figure 6" 


^RN 


tRWC to INOM 






145 


nsec 


"Per Figure 4" 


tTE 


t2XDR to tEARLY 






115 


nsec 


"Per Figure 4" 


tjN 


t2XDR to t NOM 






115 


nsec 


"Per Figure 4" 


tTL 


t2XDR to t LATE 






115 


nsec 


"Per Figure 4" 






o 
o 



ro 



NOTES: 1. Typical Values are for Ta = 25°C (77°F) and Vcc= +5.0V. 



WCLK 
NRZ 



MFM 







*i^ 



■A116- 



^ 



mmFiryiFic M m fi n f 

tTM-^ 



5^ jirimumJuiruiJuuiJimTiruinjinJvuiJii^^ 

1^ ' 



EARLY 
NOM 



LATE 



RWC 



U 



"ij LJ~lLJ 



tTL 



tRN- 



Figure 4. WD1100-12 MFM GENERATOR TIMING 



Winchester Disk Controller Devices 



3-105 



o 

o 



lO 



■HtMRt 
DR<5 



^MD 



iNTRQJJ 

Figure 5 



— HtDoK- 




Figure? 



CSorAX 
^CDOrtAD 



if=: 



DRQ — =S7-L._tci 



INTRQ 



I Figure 6 



-^'t,Q K- 




INTRQ 



Figure 8 



3-106 



Winchester Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD2010-05 Winchester Disk Controller 



o 

o 
o 

o 
en 



FEATURES 

• COMPATIBLE WITH MOST MICROPROCESSORS 
VIA AN 8-BIT DATA BUS 
DATA RATE OF 5 MBS 
MULTIPLE SECTOR READ AND WRITE 
COMMANDS 

FORMATTING AND SECTOR INTERLEAVE 
CAPABILITY 

SEEK COMBINED WITH READ AND WRITE 
COMMANDS 

SINGLE OR MULTIPLE SECTOR BUFFER USING 
FIFO OR RAM/COUNTER 
BUFFER ACCESS VIA PROGRAMMED I/O OR 
DMA 

32-BIT ECC OR 16-BIT CRC SELECTED BY 
SOFTWARE 

SECTOR LENGTH OF 128, 256, 512, 1024 BYTES 
SELECTED BY SOFTWARE 
PROGRAMMABLE RETRY ALGORITHM 
CAPABLE OF CORRECTING ERRORS WHEN A 
SECTOR BUFFER IS USED 

• 5 OR 11 BIT CORRECTION SPAN SELECTED BY 
PROGRAM 

DESCRIPTION 

The WD2010 Winchester Disk Controller is a single 
chip device designed for use with the Shugart 
Associates SA1000 and Seagate Technology ST506 
8" and 5.25" disk drives. The WD2010-05 is software 
compatible with the WD1010-05 and reads or writes 
at a rate of 5 Mbits. 

The WD2010 operates with an external buffer such 
as WD1510 128X9 FIFO memory or a combination of 
a 256X8 static RAM and an 8-bit resettable counter, 
or a DMA controller. Data bytes are transferred to and 
from the buffer every 1.6 ptsec. Transfers from the buf- 
fer to the CPU are made via programmed I/O or DMA. 

The WD2010 generates counter control signals to 
minimize external gating, and hand shake signals to 
control DMA operation for multiple sector transfers. 

A 32-blt ECC (Error Correction Code) polynomial or 
a 16-bit CRC are selectable. 

The WD2010 has three possible alternatives in handl- 
ing an error during a Read operation: 

A. It may be directed to correct the data in the Sec- 
tor Buffer automatically, providing the Host with 
good data. 

B. Supply the Host with the error location and pat- 
tern, allowing the Host to correct the error. 

C. Take no action other than setting the error flag 
and letting the Host do the entire error correction 
process. 



BCS 


1 


~r^^To 


=D vcc 


RCR 1 


2 


39 


I^ RCLK 


INTRQ 




3 


38 


1 RG 


SDHLE 




4 


37 


1 RD 


MR 




5 


36 


1 BDRQ 


RE 




6 


35 


1 BRDY 


WE 




7 


34 


1 DRUM 


CS 




8 


33 


1 RWC 


AO 




9 


32 


1 RC 


A1 




10 


31 


1 TKOOO 


A2 




11 


30 


I WF 


D7 




12 


29 


1 INDEX 


D6 




13 


28 


ZJ DRDY 


D5 




14 


27 


, 1 STEP 


D4 




15 


26 


1 niRIN 


D3 




16 


25 


I WCLK 


D2 




17 


24 


-, 1 WG 


D1 




18 


23 


1 FARIY 


DO 




19 


22 


. 1 LATE 


vss 




20 


21 


1 WD 



DIP PIN DESIGNATION 





B D K 


N D S 1 


W 




S tt R 


D R T R 


C 


D U W S 


W E D E 1 


L 


Y N 0. C 


F X Y P N 


K 




nnnnnnnnnnn 






39 38 37 36 35 


34 33 32 31 30 


29 




bdrqC 


40 




28 


ZiNC 


rdC 


41 
42 




27 
26 


13 WG 


rgC 


ID EARLY 


RCLKC 


43 




25 


_|LATE 


VccIZ 


44 




24 


Z]WD 


BCSL_ 


1 • 




23 


ZlVss 


bcrLI 


2 




22 


ZlDO 


INTRQ C 


3 




21 


=1D1 


SDHLE |_ 


4 




20 


Z]D2 


NClZ 


5 




19 


Z1D3 


NCEZ 


6 




18 


Z]D4 




X 7 8 9 10 11 


12 13 14 15 16 


17 




LJUJJUUUUUU 




M R W A 
R E E S 


A A D D D 
12 7 6 5 


N 




QUAD PIN DESIGNATION 



The WD2010 is a TTL compatible 40 pin DIP or 44 pin 
QUAD NMOS device requiring a single -I-5V supply. 



Winchester Disk Controiier Devices 



3-107 



PIN DESCRIPTION 



O 
lO 

O 



o 
en 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


1 
2 


BCS 
BCR 


BUFFER CHIP 
SELECT 






When asserted it enables reading or writing the 
external Sector Buffer as well as controlling bus 
switching. 

BCR is asserted prior to read and write 
functions and at the completion of a command. 
BCR is not used if the Sector Buffer is a FIFO. 


BUFFER 
COUNTER RESET 


3 
4 


INTRQ 


INTERRUPT 
REQUEST 






INTRQ is asserted upon completion of a com- 
mand and remains that way until the Status 
Register is read or a new command is written into 
the Command Register. This signal may be pro- 
grammed by a Read Command to occur with 
BDRQ and DRQ. 

SDHLE is asserted when the SDH Register is to 
be written into by the Host. (See Figure 3.) 


SDHLE 


SDH LATCH 
ENABLE 


5 
6 

7 
8 


MR 
RE 

WE 
CS 


MASTER RESET 


1 
I/O 

I/O 

1 


When asserted MR initializes all internal logic 
except Task File. 

Tri-state, bi-directional signal. RE is an input 
when reading the Task File, and an output when 
reading the Sector Buffer. 

Tri-state, bi-directional signal. Used as an input 
when writing to the WD2010 Task File. Used as 
an output when the WD2010 is writing to the Sec- 
tor Buffer. 

CS must be asserted to read from or write to the 
WD2010 Task File. 


READ ENABLE 


WRITE ENABLE 


CHIP SELECT 


9 

thru 

11 


AO 

thru 

A2 


ADDRESS 
thru 
ADDRESS 2 


1 


Provide the address of the register within the Task 
File that is to transmit or receive on the data bus. 


12 

thru 

19 


D7 

thru 

DO 


DATA 7 

thru 

DATAO 


I/O 


8-bit, tri-state, bi-directional bus used for the 
transfer of commands, status, and data. 


20 


Vss 


GROUND 




Ground 


21 

22 
23 


WD 


WRITE DATA 








WD is the MFM data to be written to the disk. The 
frequency is controlled internally by WCLK and 
should be stabilized further externally by a D flip 
flop clocked at twice the WCLK frequency. The 
output has an active puliup and pulldown that can 
sink e.Oma. 

This signal is used in the Write Precomoensation 
circuitry along with EARLY to control the delay 
of WD. 

This sianal is used in the Write Precompensation 
circuitry along with LATE to control the delay 
of WD. 


LATE 


LATE 


EARLY 


EARLY 


24 


WG 


WRITE GATE 





WG is asserted when valid data is to be written. 
It enables write current to the head and is 
immediately de-asserted if a Write Fault (WF) is 
detected. 


25 


WCLK 


WRITE CLOCK 


1 


A 5 MHz clock used internally to control WD. 


26 


DIRIN 


DIRECTION IN 





This signal determines the direction of the 
read/write heads when stepped. Asserted moves 
them in; de-asserted, out. 



3-108 



Winchester Disk Controller Devices 



PIN DESCRIPTION (cont.) 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


27 


STEP 


STEP PULSE 





This signal is used for pulsing the stepping motor. 
(See Stepping Rate Description.) 


28 


DRDY 


DRIVE READY 




DRDY must be asserted to execute any drive related 
commands. 


29 


INDEX 


INDEX PULSE 




The leading edge of this signal indicates that the 
index mark has been detected. 


30 


WF 


WRITE FAULT 




When asserted, indicates a write error at the drive. 
This halts all write, read, and stepping commands. 


31 


TKOOO 


TRACKOOO 




This signal is asserted when the read/write heads 
are positioned over track (cyl.OOO). It is used to 
verify proper completion of a restore command. 


32 


SC 


SEEK COMPLETE 




The leading edge of SC indicates that the drive has 
settled down after stepping. It is static tested if the 
rising edge has not been received within 10 revolu- 
tions after the stepping pulses. 


33 


RWC 


REDUCE WRITE 
CURRENT 





RWC can be programmed to reduce the write cur- 
rent starting at a selected cylinder. (See Write 
Precomp Cylinder Register.) 


34 


DRUM 


DATA RUN 


1 


DRUM informs the WD2010 when a field of all ones 
or zeros has been detected. (See Drive Interface.) 


35 


BRDY 


BUFFER READY 


1 


When asserted, the Sector Buffer is full or empty. 


36 


BDRQ 


BUFFER DATA 
REQUEST 





BDRQ represents the same state as DRQ (bit 3 of 
the Status Register). This signal is asserted when 
the Sector Buffer is to be read from or written to 
by the Host. BDRQ can be used for DMA or Pro- 
grammed I/O. If DRQ is used it must be polled by 
the Host during Programmed I/O. 


37 


RD 


READ DATA 


1 


MFM data and clocks are received from the drive. 
The clocks and data are separated internally. 


38 


RG 


READ GATE 





RG is asserted when a search for an address mark 
is initiated. It remains asserted until the end of the 
ID or data field. (See Drive Interface.) 


39 


RCLK 


READ CLOCK 


1 


This clock is generated by a VCO, phase locked to 
data read from the disk. 


40 


Vcc 


+ 5V 




+ 5 Volts 



•ARCHITECTURE 

The WD2010 provides the necessary interface con- 
trol between the Host processor and a 5.25" or 8" Win- 
chester disk drive. The controller is made up of seven 
major building blocks connected to the processor via 
a Host Interface on one side and a drive interface on 
the other. Figure 1 illustrates the major sections and 
how they relate to each other. 



The WD2010 timing is controlled by two clock input 
signals, RCLK and WCLK. RCLK is used for MFM 
decoding and is a 5 Mbit/sec data rate. WCLK is used 
for MFM encoding at the same rate as reading, PLA 
Controller, Host Interface, and Buffer Control. 



Winchester Disk Controller Devices 



3-109 



o 

O 

o 

I 

o 

CJl 



I/O BUFFERS 




TASK FILE 



i\ H 



t 



MAGNITUDE 
COMPARATOR 



BCR- 
BRDY- 
BDRO- 

BCS- 

VCC ■ 

vss- 



BUFFER 
IFC 



PLA 
CONTROLLER 



\H 



PARALLEL 

TO 

SERIAL 



MFM 
ENCODER 



WD 
WCLK 



SERIAL 

TO 

PARALLEL 



MFM 
DECODER 



SYNCHRONIZER 



AM DETECT 



DRIVE 
IFC 



PPL 
IFC 



•RCLK 



STEP 

DIRIN 

EARL Y 

LATE 

DRDY 

WF 

TKOOO 

INDEX 

SC 

RWC 

WG 

RG 

DRUN 



FIGURE 1. WD2010 BLOCK DIAGRAM 



Programmable Logic Array (PLA) Controller 

The Command Register, is tlie last of the Tasl< File 
Registers to be written into, and starts the PI_A con- 
trol. The PI_A controller, synchronized by WCLK, inter- 
prets the command, generates control signals, and 
operates in a hand shake mode when communicating 
with the MFM encoding block. 

Magnitude Comparator 

The magnitude (number of steps) and direction 
required to move the heads from their present cylinder 
to their desired cylinder is performed by an 11-bit com- 
parator. It compares the cylinder number recorded in 
the Task File (it's desired location) with the Present 
Cylinder Position Register recorded internally. From 
this, the direction and number of steps that must be 
performed to place the head on the desired track is 
calculated. 

A separate high speed equivalence comparator is 
used to compare ID field bytes when searching for 
a sector ID field. 

CRC and ECC Generator and Checker. 

The CRC mode of the operation, defined by the SDH 
(Sector Size, Head, drive select) Register (Bit 7 = 0), 



provides a means of verifying the accuracy of the data 
read from the disk but does not attempt to correct it. 

The CRC generator computes and checks cyclic 
redundancy check characters that are to be written 
to, and read from the disk following the ID and data 
fields. The polynomial used is X^^ + X^^ + x^ -f 1 . The 
CRC Register is preset to all one's before computa- 
tion starts. 

The ID field always has a 2-byte CRC character 
appended to it, while the data field may have either 
a 2-byte CRC (SDH 7 = 0) or a 4-byte ECC character 
(SDH 7 = 1). 

If the CRC character being generated while reading 
the data does not equal the one previously written, 
an error exists. If there is a CRC failure in the ID field, 
an ID not found is indicated by bit 4 of the Error 
Register being set. If the failure is in the data field, 
bit 6 of the Error Register is set. 

The ECC mode of operation (SDH 7 = 1) is only 
applicable to the data field. This feature built into the 
WD2010 provides the user with the ability to detect 
and correct errors in the data field automatically. 



3-110 



Winchester Disk Controller Devices 



A summary of the parameters to be considered when 
ECC is desired are: 

1. SDH Register bit 7. 

2. Read Command bit (T). 

3. Read and Write Command bit 1 (L). 

4. Compute Correction Command. 

5. Set Parameter Command. 

6. Error correction successful, bit 2 of the Status 
Register. 

7. Error occurred, bit of the Status Register. 

8. Uncorrectable error, bit 6 of the Error Register. 

The SDH register bit 7 must be equal to one to change 
from the CRC mode to the ECC mode. 

The T bit (bit 0) within the Read Command controls 
whether or not error correction is to be attempted. 

When T = and an error is detected, the WD2010 
tries up to 10 times to correct the error. If successful, 
bit 2 of the Status Register is set. The Host can inter- 
rogate the Status Register and detect that a problem 
does exist, but was corrected. If the error is not cor- 
rectable, bit 6 of the Error Register is set. The Host 
can read the data, even though errors do exist. 

When T = 1, and an error is detected, no attempt is 
made to correct it and bit of the Status Register 
and bit 6 of the Error Register is set. The user now 
has two choices: 

1 . Ignore the error and make no attempt to correct it. 

2. Use the Compute Correction Command to deter- 
mine the pattern and location of the error, and cor- 
rect it within the user's program. 

When the Compute Correction Command is 
implemented, it should be done before executing any 
command that can alter the content of the ECC 
Register. The Read, Write, Scan, and Format com- 
mands alter the syndrome and correction is impossi- 
ble. The Compute Correction Command determines 
that the error is uncorrectable, at which point the error 
bits in the Status Register and Error Register are set. 

Although ECC generation starts with the first bit of 
the F8 byte in the data ID field, the actual ECC bytes 
produced for the sector are the same as if the A1 byte 
was included. 

The ECC polynomial used is, 

X32 + x28 + X26 + X19 -t- X17 -f X^O H- X6 -f X2 -h 1 . 

For auto correction the external data buffer must be 
implemented with a static RAM and counter, not a 
FIFO memory. 

The Set Parameter Command is used to select a 5 
or 11-bit correction span. 

Read and Write Commands, with the L bit (bit 1) equal 
to one, are referred to as Readlong and Writelong 
Commands. With these commands, no ECC or CRC 
characters are generated or checked by the WD2010. 
In effect, the 4 ECC bytes are handled as an addi- 
tional 4 bytes of data which pass through the data 
buffer. 

With proper use of the Write, Readlong, Writelong, 



and Read commands, a diagnostic routine may be 
developed to test the accuracy of the error correc- 
tion process. 

MFM Encoding and Decoding 

The MFM encoder receives its data one byte at a time 
from an 8-Bit parallel-to-serial register, and with the 
frequency of WCLK, develops the MF M WD. De- 
pendi ng on the bit pattern of the data, EARLY or 
LATE may be asserted. External circuitry uses 
these signals to compensate for the shift caused by 
the influence one bit has over another. The WD2010 
examines three bits, the last one written, the one 
bein g written , a nd the next one to be written. From 
this, EARLY or LATE is asserted. Since the bit leav- 
ing the WD2010 has already occurred, it is too late 
to make it early, therefore the external delay circuit 
must be as follows. 



no 
one 
two 



EARLY (asserted) and LATE (de-asserted) 

delay 

EARLY (de-asserted) and LATE (de-asserted) 
unit delay 

EARLY (de-asserted) and LATE (asserted) 
units delay 

These signals are not dependent upon the Write 
Precomp Cylinder register (RWC). Figure 6 illustrates 
one method of using these signals. 

The MFM decode operates from RCLK, a bit rate 
clock generated from the external Data Separator. 
RCLK and WCLK need not be synchronized. 

Address Mark (AM) Detection 

An address mark is comprised of two unique bytes 
preceding both the ID field and the data field. The first 
byte is used for resynchronization. The second byte 
indicates whether it is an ID field or a data field. 

The first byte, A1 hex, normally has a clock pattern 
of OE hex. However, one clock pulse has been sup- 
pressed, making it QA hex. With this pattern, the 
detector knows it is looking at an address mark. It 
now examines the next byte to determine if it is an 
ID or data field. If bits 7 thru 2 are 1111X1XX, it is an 
ID field (bits 3, 1, and are the high order cyl.#bits). 
If the second byte is F8, it is a data field. 

Host Interface 

The primary interface between the Host processor 
and the WD2010 is an 8-bit bi-directional bus. This 
bus is used to transmit and receive data for both the 
WD2010 and the Sector Buffer. The Sector Buffer con- 
sists of either a FIFO memory, or a static RAM and 
counter. Since the WD2010 makes the bus active 
when accessing the Sector Buffer, a transceiver must 
be used to isolate the Host during this time. Figure 
2 illustrates a typical interface with a Sector Buffer, 
implemented with a RAM memory. Whenever the 
WD201(M)5 is not using the Sector Buffer.it turns con- 
trol of the Sector Buffer and dat a bus over to the Host 
by de-asserting its output term, BCS. This de-selects 
the Sector Buffer and switches the data bus 
transceivers. 



O 

o 



o 
en 



Winchester Disk Controller Devices 



3-111 



D 

ro 

o 



o 
en 



When the Host wants to access the Sector Buffer it 
produces an address of zero (AO thru A2 i^ 0). A 
decoder recognizing AO thru A2 + asserts a BCS 
of its own. The Host then asserts WE or RE for 
the counter, at the leading edge, the iocation within 
the Sector Buffer addressed by the counter is 
accessed, at the trailing edge the counter advances 
to the next count. The decoder asserts CS to the 
WD2010 any time the address does not equal zero 
(AO thru A2 # 0). 

During Write Sector commands the Host sets up data 
in the Task Fil e and issues the command. The 
WD2010 asserts BCR to zero the counter. It then 
generates a status to inform the Host it can load the 
Sector Buffer with the data to be written. When the 
counter reaches its maximum count, BRDY is 
asserted by the carry out of the counter. Informing 
the WD2010 that the Sector Buffer is full. (BRDY is 
asserted with a rising edge a nd is i gnore d if asserted 
before the WD2010 asserts BCR.) BCS is then as- 
serted, disconnecting the^ Host through the 
transceivers, and RE and WE become outputs from 
the WD2010 to allow access to the Sector Buffer. 
When the W D2010 is done using the Sector Buffer, 
it de-asserts BCS which again allows the Host to 
access this local bus. 



The Read Sector Command operates in a similar man- 
ner, except that the Sector Buffer is loaded by the 
WD2010 instead of the Host. 

When BDRQ is used, it can either be connected to 
a DMA controller or used for programmed I/O. In either 
case it signals that the WD2010 is ready to receive 
or transmit data. DRQ status bit, if used, must be 
polled by the Host, therefore is limited to programmed 
I/O. 

When INTRO is asserted, the Host is signaled that 
a command has terminated (either a normal termina- 
tion or an aborted command). In the case of the Read 
Command, INTRO can be programmed by bit 3 to be 
asserted upon termination as the other commands, 
or at the same time BDRO is asserted. In either case, 
INTRO remains asserted until the Host reads the 
Status Register to determine the result of the termina- 
tion, or writes a new command into the Command 
Register. 



The WD2010 asserts SDHLE to the Host whenever 
the SDH register is being written into. This mal<es it 
possible to store the same information in an exter- 
nal register for decoding. Figure 3 illustrates one 
method. 



RE 
WE 

DATA 
HOST 

SEL 
AO-2 






























RE 
WE 

D0-D7 
BCR 

WD2010 

BCS 
CS 

Ao-2 
BRDY 

BDRQ 

INTRQ 






















DATA BUS (8) 


















A 


1 










TRANSCEIVER 






































s 




















5" 


>CK J 

TC °X 




Ao °*™ 

A, RE 

I WE 
Ax CS 


- 
















D 

E 
C 
O 
D 

E 














1 










^ 








3 

1 








'/ 










3. . 


/ 














D C 

CP 
RST 




























DMA 
CONTROLLER 








1 




V 












1 








J 




L 








^ , 






















-A 



FIGURE 2. HOST INTERFACE 



3-112 



Winchester Disk Controlier Devices 



Drive Interface 

The drive side of the WD2010 controller requires 
three sections of external logic. These are interface/ 
Sector Buffers, data separator, and write precom- 
pensation. Figure 3A illustrates the drive interface. 

The control lines are buffered, single-ended, and 
resistor terminated at TTL levels. The data lines to 
and from the drive also require buffering, and are ter- 
minated v/ith RS-422 drivers. The interface specifica- 
tion for the drive can be found in the manufacturer's 
OEM manual. The WD2010 supplies TTL compatible 
signals, and interfaces with most driver devices. 

When the SDH Register is written into, the Head and 
Drive select signal s are la tched externally by the 
latch enable signal SDHLE. See Figure 3B. 

The data recovery circuits consist of a phase lock 
loop, data separator, and associated components. 
The WD2010 Interacts with the data separator through 
DRUM and RG. The block diagram of the data sep- 



arator circuit is illustrated in Figure 4. Data read from 
the drive is presented to the RD input of the WD2010, 
the reference multiplexor, and a retriggerable one 
shot. The RG is de-asserted when the WD2010 is not 
inspecting data. The PLL at this time should remain 
locked to the reference clock. 

When any Read or Write Command is initiated and 
a search for an address mark begins, DRUM is 
examined. The DRUM one-shot is set slightly longer 
than one bit time, allowing it to retrigger constantly 
on a field of all ones or all zeros. An internal counter 
times out to see that DRUM is asserted for 2 byte 
times. RG is asserted by the WD2010 switching the 
data separator to lock onto the incoming data stream. 
If DRUN is de-asserted prior to 7 byte times, RG is 
de-asserted and the process Is repeated. RG remains 
asserted until a non-zero, address mark is detected. 
It then de-asserts RG for two byte times (to allow the 
PLL to lock back on the reference clock) and starts 
the DRUN search over again. If an address mark is 



O 
to 

o 



o 
en 




WD 

EARLY 

LATE 

RWC 



STEP 

DIRIN 

DRDY 

WF 

TKOOO 

INDEX 

SC 

WG 





r. 








° ^ ° 

T Q 














D 

E 
C 
O 
D 

E 












V 

















HSELO 
HSEL1 
HSEL2 
DSELl 
DSEL2 
DSEL3 



DATA 
SEPARATOR 



WRITE 

PRECOMPENSATION 

AND 

SYCHRONIZATION 



INTERFACE/ 
BUFFER 




DISK 
DRIVE 



FIGURE 3A. DRIVE INTERFACE BLOCK DIAGRAM 



Winchester Disk Controller Devices 



3-113 



o 

o 



o 



detected, RG remains asserted and the command 
continues searching for the proper ID fieid. This 
sequence is iiiustrated in Figure 5. 

The Write Precompensation circuitry Is designed to 
reduce the shift in the data caused by the effect one 
bit has over another. The Write precom pensa tio n logi c 
is divided Into two areas: RWC and Early or Late 
writing of the bits. A block diagram of the Write 
Precomp circuit is iiiustrated In Figure 6. 

RWC is controlled by the Write Precomp Cylinder 



Register In the Task File. This register is written into 
by the Host. When a cylinder is called for that Is equal 
to, or greater than the content of this register, the 
write current will be reduced, thus lessening the effect 
one bit can have over another. 

Shift may also be caused by the bit pattern. With cer- 
tain combinations of ones and zeros some of the bits 
can drift far enough apart to become difficult to read 
witho ut error. This pheno menon can be minimized by 
using EARLY and LATE as described under MFM 
Encoder. 



cs 

WE 
AO' 

A1 ■ 
A2 



COMMAND-IN-PROGRESS 



-0O— o 
-tXD—0 




H^ 



SDHLE 



FIGURE 3B. LATCH ENABLE SIGNAL 







































250 MSEC 

RETRIGGERABLE 

ONE-SHOT 




DRUM 

RD 

WD2010 
RCLK 

RG 
WCLK 


5MBITS 




















MFM 






c 

K 




DATA 












1 ,. 






^ 




pharfX^ 
COM^X^ 


FtLTER 
AND 

vco 










L 














A 
B 


MUX 






H ^' 








y^ 


















1 


' 




















1 




r 


-r 2 


1 


10 MHZ 

osc 






L 


1 
















I 























FIGURE 4. DATA SEPARATOR CIRCUIT 



3-114 



Winchester Disk Controller Devices 




o 

o 



o 
en 



FIGURE 5. PLL CONTROL SEQUENCE FOR ID FIELD 



Winchester Disk Controller Devices 



3-115 



D 
lO 

o 



o 
01 



c 








TRANSFER 

DATA AND 

CHECK CRC/ECC 



DE-ASSERT 
RG 



FIGURE 5A. PLL CONTROL SEQUENCE FOR DATA FIELD 



3-116 



Winchester Disk Controller Devices 



WD 
EARLY 



D T Q 

C 
D H Q 



WD2010-05 = lOMHzOSC 




^ 



o 

O 

o 
o 

CJ1 



FIGURE 6. WRITE PRECOMPENSATION CIRCUIT 



TASK FILE 

The Task File is a bank of nine, 8-bit registers used 
to hold status information indicating the success or 
failure of an operation, as well as the parameters 
under which the drive is to operate. They are 
addressed by AO through A2 lines. AO through A2 = 
is unused by the WD2010 and when received, puts 
its bus in the tri-stated condition isolating it from the 
bus. 

ERROR REGISTER (A2 thru AO = 1 READ) 

This register contains specific error status pertain- 
ing to the completion of a command. These bits are 
defined as follows: 



7 


6 


5 


4 


3 


2 


1 





BB 


CRC/ECC 





ID 





AC 


TK 


DM 



BIT 7 - BAD BLOCK DETECT 

This bit is set when an ID field has been encountered 
that contains a Bad Block Mark. It is used for bad 
sector mapping. 

BIT 6 - CRC/ECC DATA FIELD ERROR 

CRC mode of operation (SDH 7 = 0): this bit is set 
when a CRC error occurs in the data field. When Retry 
is enabled, ten more attempts are made to read the 
sector correctly. If none of these attempts are suc- 
cessful, bit zero in the Status Register is set also. If 
one of the attempts is successful, this bit remains 
set to inform the Host that a marginal condition 
exists. However, the zero status bit is not set. No 
attempt is made to correct the error. 



ADDRESS 


TASK FILE 


A2 


A1 


AO 


READ ONLY WRITE ONLY 











BUS TRI-STATED 








1 


Error Register Write Precomp Cylinder 





1 





Sector Count 





1 


1 


Sector Number 


1 








Cylinder Low 


1 





1 


Cylinder High 


1 


1 





SDH Register 


1 


1 


1 


Status Register Command Register 


NOTE: These registers are not cleared by MR being asserted 



Winchester Disk Controlier Devices 



3-117 



D 
lo 

o 

o 

I 

o 
en 



ECC mode of operation (SDH 7 = 1). This bit is set 
when the first non-zero syndrome is detected. When 
Retry is enabled, up to ten attempts are made to cor- 
rect the error. If successful, this bit remains on. 
However, bit 2 of the Status Register is set to inform 
the Host that the error has been corrected. If unsuc- 
cessful, this bit remains on and bit zero of the Status 
Register Is set also. When Retry is disabled no 
attempt is made to correct the error. 

The data may be read even if errors do exist. 

Note: If the Long Mode bit is set in the Read or Write 
command, no error checl<ing is performed. 

Bit 5-Reserved 

Not used, forced to zero. 

Bit 4-ID Not Found 

This bit is set to Indicate that the correct cylinder, 
head, sector, or size parameter could not be found, 
or a CRC error occurred on the ID Held. This bit is 
set on the first failure and remains set even if the error 
is recovered on a retry. When recovery is unsuc- 
cessful, the Error Status bit is set also. 

For a Scan ID Command with retry enabled (T = 0), 
the Error Status bit is set after ten unsuccessful 
attempts have been made to find the correct ID. With 
Retry disabled (T = 1) only two attempts are made 
before setting the Error Status. 

For a Read and Write Command with Retry enabled 
(T = 0), ten attempts are made to find the correct ID 
field. If there Is still an error on the tenth try, an auto- 
scan and auto-seek are performed. Then, ten more 
tries are made before setting the Error Status. When 
the Retry is disabled (T = 1) only two tries are made, 
and no auto-scan or auto-seei< operations are 
performed. 

Bit 3-Reserved 

Not used, forced to zero. 

Bit 2-At}orted Command 

The command is aborted and this bit set if, DRDY has 
not been asserted, WF is asserted, or the command 
issued had an undefined command code. 

Bit 1 -Track Zero Error 

This bit is set during a Restore Command when 
TKOOO input has not Indicated that the head has 
reached track zero by 2047 steps. 

Bit 0- Data Address Mark Not Found 

This bit is set during a Read Sector Command if the 
Data Address Mark Is not found following the proper 
sector ID. 

WRITE PRECOMP CYLINDER (A2 thru AO = 1 write) 

This register is used to define the cylinder number 
where the RWC output signal is to be asserted. 



7 


6 


5 


4 


3 


2 


1 





CYLINDER NUMBER ^ 4 



The value 00-FF loaded into this register is internally 
multiplied by four to specify the actual cylinder 
where RWC is to be asserted. Thus a value of 9C 
Hex causes the RWC to be asserted on cylinder 270 
Hex, 9D Hex on cylinder 274 Hex, etc. RWC is 
asserted when the present cylinder is equal to, or 
greater than the value of this register. For example, 
the ST506 requires precomp 80 Hex (128 dec.) and 
above. Therefore, the write precomp cylinder should 
be loaded with 20 Hex (32 dec). 

A value of FF Hex causes RWC to remain de-asserted, 
regardless of the cylinder number values. 

SECTOR COUNT (A2 thru AO = 2) 

in a muiipie sector operation, this register contains 
the number of sectors involved with Read Seector, 
Write Sector, and Format commands. 



7 


6 


5 


4 


3 


2 


1 





NUMBER OF SECTORS 



The value written into this register is decremented 
by one after each sector is transferred to or from the 
Sector Buffer. A zero represents a 256 sector transfer, 
a 1 = one sector, etc. This register is disregarded 
when a single sector command is specified. 

SECTOR NUMBER (A2 thru AO = 3) 

This reigister holds the number of the desired sector. 



7 


6 


5 


4 


3 


2 


1 





SECTOR NUMBER 



This is the starting sector in a multiple sector com- 
mand. It is incremented by one after each sector has 
been transferred to or form the Sector Buffer. The 
register can contain any value from to 255. 

This register also specifies the minimum GAP 3 
length, minus 3, during a Format Command. 

CYLINDER NUMBER LOW (A2 thru AO = 4) 

This register holds the least significant 8 bits of the 
desired cylinder number. 



7 


6 


5 


4 


3 


2 


1 





LS BYTE OF CYL NUMBER 



It is used in conjunction with the Cylinder Number 
High Register to specify a range of to 2047. 

CYLINDER NUMBER HIGH (A2 thru AO = 5) 

This register contains the three most significant bits 
of the desired cylinder number. 



7 


6 


5 


4 


3 


2 


1 





X 


X 


X 


X 


X 


# 


# 


# 



3-118 



Winchester Disk Controller Devices 



These registers determine where the R/W heads are 
to be positioned. The Host writes the desired cylinder 
number into these registers. Internal to the WD2010 
is another pair of registers pointing to where the 
heads are presently located. When any command, 
other than a Restore, is executed these registers are 
compared. The difference between them results in 
DIRIN and STEP signaling the drive how many 
cylinders to move the heads and in which direction. 

The Present Cylinder Position Register is updated to 
equal the cylinder Number Register at the comple- 
tion of the seek. 

When a Restore Command is executed, the Present 
Cylinder Position Register is reset to zero, while DIRIN 
and STEP move the heads to track zero. 

SDH REGISTER (A2 thru AO = 6) 

This register contains the desired sector size, drive 
number, and head number parameters. 



A SCAN ID Command reads the cylinder number from 
the track on which the heads are presently located, 
and writes this into the Present Cylinder Position 
Register. 

When a different drive is selected just prior to a Read, 
Format, Write, or Seek command, the WD2010 issues 
^n auto-scan ID command. This updates the Present 
Cylinder Position Register to reflect the position of 
the heads on this drive. 



D 

ro 

o 



U1 




6 


5 


SECTOR SIZE 








256 





1 


512 


1 





1024 


1 


1 


128 



NOTE: 

Drive select and head select lines must be generated 
externally. Figure 3 represents one method of achiev- 
ing this. 

As shown below, the SDH byte written in the ID field 
during the Format Command is not the same as the 
contents of the SDH Register. 

Bit 7 - One selects the ECC mode for the data field. 
Zero selects the CRC mode for the data field. 



7 


6 5 


4 3 


2 1 


BAD B. 


SIZE 





HEAD 



STATUS REGISTER (A2 thru AO = 7 READ) 

The Status Register is used to inform the Host of cer- 
tain events performed by the WD2010 as well as repor- 
ting status from the drive control lines. Reading the 
Status Register de-asserts INTRQ. 



DRIVE # 



DSEL1 
DSEL2 
DSEL3 
DSEL4 



2 


1 





HEAD# 











HSELO 








1 


HSEL1 





1 





HSEL2 





1 


1 


HSEL3 


1 








HSEL4 


1 





1 


HSEL5 


1 


1 





HSEL6 


1 


1 


1 


HSEL7 



7 


6 


5 


4 


3 


2 


1 





BSY 


RDY 


WF 


SC 


DRQ 


DWC 


CIP 


ERR 



Bit 7 - Busy 

BUSY is asserted when a command is written into 
the Command Register and, except for the Read Com- 
mand, it is de-asserted at the end of the comand. 
When executing a Read Sector Command, BUSY is 
de-asserted when the Sector Buffer is full. Commands 
should not be loaded into the Command Register 
when this bit is set. When the BUSY bit is set, no 
other bits in the Status or Error Register are valid. 



Winchester Disk Controller Devices 



3-119 



o 

lo 

o 

o 
o 



Bit 6 - Ready 

This bit reflects tfie status of DRDY. When this bit 
equals zero, the command is aborted and the status 
of this bit is latched. 

Bit 5 - Write Fauit 

This bit reflects the status of WF. When this bit equals 
one, the command is aborted, INTRQ is asserted, and 
the status of this bit Is latched. 

Bit 4 - Seel< Complete 

This bit reflects the status of SC. When a seek or 
implied seek has been initiated by a command, it 
pauses until the seek is complete. This bit is latched 
after an "aborted command" error. 

Bit 3 - Data Request 

DRQ reflects the same status as BDRQ. It is asserted 
when the data Sector Buffer must be written into, or 
read from. DRQ and BDRQ remain asserted until 
BRDY indicates that the Sector Buffer has been filled 
or emptied, depending upon the command. DRQ is 
used during Program Interrrupt and must be inter- 
rogated by the Host to determine that the WD2010 
is ready. BDRQ operates through a DMA controller 
for data transfers. 

Bit 2 - Data Was Corrected 

When a one, this bit indicates an error has been 
detected during the ECC mode of operation and the 
data in the Sector Buffer has been corrected. This pro- 
vides the user with an indication that there may be 
a marginal condition within the drive before the errors 
become uncorrectable. This bit is forced to zero when 
not in the ECC mode of operation. 



Bit 1 - Command in Progress (CiP) 

When this bit is set, a command is being excuted and 
a new command should not be loaded. Although a 
command is being executed the Sector Buffer is still 
available for access by the Host. When WD2010 is 
no longer busy, (bit 7 = 0) the Status Register can 
be read. An attempt to read the other registers results 
in reading the status. 

Bit - Error 

This bit indicates that a non-recoverable error has 
occurred. When the Host reads the status and finds 
this bit set, it must then read the Error Register to 
determine what type of error it was. 

COIVIIVIAND REGISTER (A2 thru AO = 7 write) 

The command to be executed is written into this 
register. 



1 



COMMAND 



The command asserts BUSY and CIP, and begins to 
execute as soon as it is written into this register. 
Therefore, all necessary information should be loaded 
into the Task File prior to entering the command. Any 
attempt to write into these registers is ignored until 
the command has terminated, as indicated by the CIP 
status. INTRQ is de-asserted if it is still active at the 
time the command is written. 



COIVIIVIAND SUMMARY: 




















BIT 


COMMAND 


7 


6 


5 


4 


3 


2 


1 





RESTORE 











1 


R3 


R2 


R1 


RO, 


SEEK 





1 


1 


1 


R3 


R2 


R1 


RO 


READ SECTOR 








1 





1 


M 


L 


T 


WRITE SECTOR 








1 


1 





M 


L 


T 


SCAN ID 





1 

















T 


WRITE FORMAT 





1 





1 














COMPUTE CORRECTION 














1 











SET PARAMETER 























s 



stepping Rate Field R3-R0 

For 5 MHz WCLK: 
R3-R0 = 0000-35;iSec 
0001-. 5msec 
0010-1.0msec 
0011-1. 5nsec 
0100-2.0msec 
0101-2.5msec 
0110-3.0msec 
0111-3.5msec 
1000-4.0msec 
1001-4.5msec 



1010-5.0msec 
1011 -5.5msec 
1100-6.0msec 
11 01 -6.5msec 
1110-3.2fisec 
1111-16/^sec 
STEP PULSE WIDTH = 
1.6fisec at 3.2fisec rate 
8.0/isec at all others. 



3-120 



Winchester Disk Controlier Devices 



I - Interrupt Control 

I = INTRQ occurs with BDRQ/DRQ 
indicating the Sector Buffer is full (valid 
only when M = 0). 

I = 1 INTRQ occurs when the command is 
completed and the Host has read the 
Sector Buffer. 

M - Multiple Sector Flag 

M = Transfer one sector (the sector count is 
ignored) 

IVI = 1 Transfers multiple sectors 

L - Long Mode 

L = Normal mode, normal CRC or ECC func- 
tions are performed. 

L = 1 Long mode, no CRC or ECC bytes are 
developed or error checking performed 
on the data field. The WD2010 appends 
the four additional bytes supplied by the 
Host or disk to the data field. 

T - Retry Flag 

T = Enable Retry 

T = 1 Disable Retry 

S - Error Correction Span 

S = 5-bit span 
S = 1 11-bit span 

RESTORE COMMAND 

The Restore command is used to position the 
read/write heads over track zero. It is usually issued 
by the Host when a drive has just been turned on. 

The stepping rate used for the restore is determined 
by SC. The WD2010 issues a Step pulse and then 
waits for the leading edge of SC before starting 
another step. If the leading edge of SC is not seen 
within 10 revolutions (index pulses) the WD2010 swit- 
ches to sensing the level of SC. If after 2047 Stepp- 
ing pulses TKOOO is not asserted, the WD2010 sets 
the Track Zero error bit, asserts INTRQ and terminates 
the operation. An interrupt also occurs if WRITE 
FAULT is asserted or DRDY is de-asserted during 
execution. 

The stepping rate field is stored in an internal register 
for future use by commands with implied seeks. 

SEEK COMMAND 

By not testing SC, the Seek Command is capable of 
overlapping seeks on multiple drives. R3 through RO 
controls the stepping rate, as well as being written 
into an internal register for use by those commands 
with implied seek capability. 



c 



3 



RESET INTRQ, 

ERRORS, 
SET BUSY, CIP 



o 

to 

o 



en 



RESET RWC 

SET DIRECTION 

= OUT 

STORE STEP RATE 




FIGURE 7. RESTORE COMMAND 



Winchester Disk Controller Devices 



3-121 



D 
lO 

o 



o 

U1 



c 



YES 



SET ABORTED 
COMMAND BIT 



RESET INTRO. 

ERRORS, 

SET BUSY, CIP 

STORE STEP RATE 



SET 
DIRECTION 



DELAY 

ACCORDING TO 

RATE FIELD 



1 






FIGURE 8. SEEK COMMAND 



3-122 



Winchester Disk Controller Devices 



The direction and number of step pulses needed are 
calculated by comparing the contents of the cylinder 
number in the Task File to the present cylinder posi- 
tion number stored internally. After all the steps have 
been issued, the present position cylinder number is 
updated, INTRQ asserted and the command ter- 
minated, if DRDY is de-asserted or WF is asserted 
during the execution of the command, INTRQ is 
asserted, and the command aborts setting the AC 
error. 

If an implied seek is performed, the stepping rate for 
all but the last step is controlled by R3 through RO. 
On the last step the seek continues until the leading 
edge of SC is detected. 

READ SECTOR 

The Read Sector command is used to transfer one 
or more sectors of data from the disk to the Sector 
Buffer. Upon receipt of this command, the WD2010 
compares the cylinder number in the Task File with 
the Present Cylinder Position Register. From this, the 
direction and number of steps required for the seek 
are calculated. As stated in the Seek Command, if 
an implied seek is performed, the stepping rate for 
all but the last step is controlled by R3 through RO. 
On the last step the seek continues until the leading 
edge of SC is detected. 

If the WD2010 detects a change in the drive number 
since the last Read Command, an Auto Scan ID is 
performed. This updates the Present Cylinder Posi- 
tion Register to reflect the current drive before the 
seek begins. 

After the WD2010 senses SC (with or without an 
implied seek) it must find an ID field with the correct 
cylinder, head, sector size, and CRC. With Retry 
enabled (T = 0), ten attempts are made to find the 
correct ID field. If there is still an error on the tenth 
try, an auto-scan and auto-seek are performed. Then, 
ten more tries are made before setting the ID Not 
Found Error. When Retry is disabled (V = ^) only two 
tries are made, and no auto-scan or auto-seek opera- 
tions are performed. 

When the Data Address Mark is found the WD2010 
is ready to transfer data into the Sector Buffer (if after 
successfully reading the correct ID field the Data 
Address Mark is not found a DAM error is set). When 
the disk has filled the Sector Buffer, the WD2010 
asserts BDRQ and DRQ and then checks the I flag. 
If the flag is 0, INTRQ is asserted also, signaling the 
Host to read the content of the Sector Buffer. If the 
I flag is 1, INTRQ occurs after the Host has read the 
Sector Buffer and terminated the command. 

An optional M flag can be set for multiple sector 
transfers. When M = 0, one sector is transferred and 
the sector count is ignored. When M = 1, multiple 
sectors are enabled. After each sector is transferred, 
the WD2010 decrements the sector count and 
increments the sector number. The next logical sec- 
tor is transferred, regardless of the interleave. Sec- 
tors are numberd by a byte in the ID field during the 
Format Command. 



For the WD2010 to make multiple sector transfers to 
the Sector Buffer, the BRDY signal must toggle from 
low to high for each sector. The sector transfers con- 
tinue until the sector count equals zero. If the sector 
count is not zero ( indication more sectors are to be 
read) and the Sector Buffer is full, BDRQ is asserted 
and the Host must unload the Sector Buffer. Once 
this occurs, the Sector Buffer is free to accept the 
next sector. 

WF and DRDY are monitored throughout the com- 
mand. If WF becomes asserted, or DRDY de-asserted, 
the command terminates and the AC error flag is set. 
For a description of the error checking procedure on 
the data field see the explanation under CRC and ECC 
Generator and Checker. Both the Read and Write 
commands feature a simulated completion to ease 
programming. BDRQ, DRQ, and INTRQ are generated 
in a normal manner upon detecting an error condi- 
tion. This allows the same program flow for suc- 
cessful or unsuccessful completion of a command. 

When M = (Single Sector Read) 

(1) Host: Sets up parameters; issues Read 

Sector command. 

(2) 2010: Finds se ctor specified: asserts 

BCR and BCS. Sector Buffer data 
transfer via W E. 

(3) 2010: Asserts BCR de-asserts BCS. 

(4) 2010: Asserts BDRQ and DRQ flag. 

(5) 2010: If 1 bit = then (8). 

(6) Host: Reads contents of Sector Buffer 

(by asserting RE). 

(7) 2010: Waits for BRDY the asserts 

INTRQ; End. 

(8) 2010: Asserts INTRQ. 

(9) Host: Reads contents of Sector Buffer 

(by asserting RE);End. 

When M = 1 (Multiple Sector Read) 

(1) Host: Sets up parameters; issues Read 

Sector command. 

(2) 2010: Find s se ctor specified: asserts 

BCR and BCS. Sector Buffer data 
transfer via W E. 

(3) 2010: Asserts BCR; de-asserts BCS. 

(4) 2010: Asserts BDRQ and DRQ flag. 

(5) Host: Reads contents of Sector Buffer 

(by asserting RE). 

(6) Sector Indicates data has been transfer- 
Buffer: red by asserting BRDY. 

(7) 2010: When BRDY is asserted, 

decrements sector count; 
increments sector number, go to 
(9) if sector count = 0. 

(8) 2010: Go to Step (2). 

(9) 2010: Asserts INTRQ; End. 



O 
lo 

o 



U1 



Winchester Disk Controller Devices 



3-123 



c 



READ SECTOR 



3 



DE-ASSERT: 

INTRQ, ERRORS 

ASSERT 

BSY, CIP 




<D 



ASSERT 
AC 



*lf T bit of command = 1 then dashed path is taken 

after 2 index pulses. 
* If T bit of command = 1 then test is for 2 Index 

Pulses. 



© 



O 




SEARCH FOR 
ID FIELD 



SET 
ID NOT FOUND 



© 





FIGURE 9. READ COMMAND 



3-724 



Winchester Disk Controller Devices 




TRANSFER 

SECTOR TO 

BUFFER 



INCREMENT SECTOR* 

DECREMENT SECTOR 

COUNT 





ASSERT BAD 

BLOCK BIT 

(BIT 7 ERROR REG) 







SET DAM NOT FOUND 

(BITOERRORREG ) 

DE-ASSERT BCS 

PULSE BCR 



NOTEt 




SET ERROR IN 

STATUS REGISTER 

(BITO) 



& 



Q 




O 

O 



O 

cn 



CORRECT ERROR, 

SET DWG IN 

STATUS REGISTER (BIT 2) 




tIfT bit Of command = 1 then dashed path is taken 
' * If T bit of command = then test is for 2 Index 
Pulses. 




ASSERT INTRQ 



c 






FIGURE 9. READ COMMAND (Continued) 



Winchester Disk Controller Devices 



3-125 



D 
ro 

o 

o 

o 
en 



WRITE SECTOR 

The Write Sector Command is used to write one or 
more sectors of data from the Sector Buffer to the 
disk. Upon receipt of this command, the WD2010 com- 
pares the cylinder number in the Task File with the 
present position cylinder number. From this, the direc- 
tion and number of steps required for the seek are 
calculated. As stated in the Seek Command, if an 
implied seek is performed, the stepping rate is con- 
trolled by R3 through RO. After the last step the 
WD2010 waits until the leading edge of SC Is received. 

If the WD2010 detects a change in the drive number 
since the last Write Command, an auto-Scan ID takes 
place. This updates the Present Cylinder Position 
Register to reflect the current drive before the seek 
begins. 

After the WD2010 senses SC (with or without an 
implied seek), BDRQ and DRQ signals are asserted 
and the Host proceeds filling the Sector Buffer. When 
BRDY is asserted, a search for an ID with the 
specified cylinder, head, sector size, and CRC is 
initiated. If the ID is not found and Retry is enabled 
(T = 0), ten attempts are made to find the correct ID 
field. If there is still an error on the tenth try, an auto- 
scan and auto-seek is performed. Then ten more tries 
are made before setting the Error Status bit. (The ID 
Not Found error is set on the first failure). When Retry 
is disabled (T = 1). Only two tries are made and no 
auto-scan or auto-seek operations are performed. 

When the correct ID is found, WG is asserted and 
data is written to the disk. When SDH 7 bit is zero, 
WD2010 generates a two byte CRC character to be 
appended to the data. When SDH 7 bit is one, four 
ECC bytes replaces the CRC character. When the L 
bit within the Write Command is one, the polynomial 
generation of the data is inhibited, and neither CRC 
or ECO bytes are generated. Instead, four bytes of 
data supplied by the Host is written. 

During a multiple sector write operation (M flag = 
1), the sector number is incremented and sector count 
decremented. If BRDY is asserted after the first sec- 
tor is read from the Sector Buffer, WD2010 continues 
to read data from the Sector Buffer for the next sec- 
tor. If BRDY is de- asserted, WD2010 asserts BDRQ 
and waits for the Host to place data in the Sector 
Buffer. 



Summary of a write sector operation: 

(1) Host: Sets up parameters; issues write 
sector command. 
Asserts BDRQ and DRQ. 
Loads Sector Buffer with data (by 
asserting WE). 

Waits for leading edge of BRDY. 
Finds specified ID field, write to 
sector. 

If M = 0, assert INTRQ; End. 
Increments sector number, 
decrements sector count. 
If sector count = 0, assert INTRQ; 
End. 
Go to (2). 



The Scan ID Command is used to update the head, 
sector size, sector number, and cylinder registers. 

When the first ID field is encountered, the ID infor- 
mation is loaded into the SDH cylinder, and sector 
number registers in the Task File. The Present Posi- 
tion Cylinder Register is also updated. If this is an 
Auto- Scan caused by a change in drive numbers, only 
the present position cylinder number is altered. 

If the ID field is not found and Retry is enabled (T =0), 
ten attempts are made to read it. If Retry is disabled 
(T = 1), only two tries are made. There is no implied 
seek in this command and the Sector Buffer remains 
unchanged. When DRDY is de-asserted or WF 
asserted the command aborts and the appropriate 
error flags are asserted. 



(2) 


2010: 


(3) 


Host: 


(4) 


2010: 


(5) 


2010: 


(6) 


2010: 


(7) 


2010: 


(8) 


2010: 


(9) 


2010: 


SCAN ID 





3-126 



Winchester Disk Controller Devices 




RESTORE AND 
ASSERT ID 
NOT FOUND 



DE-ASSERT 
WG.BCS' 
PULSE BCH 



ASSERT INTRO 

DE-ASSERT BSY. CIP. BOS | 
PULSE BCB 




o 

lo 

o 



o 

U1 



'If retries disabled then dashed 
path is taken after 2 Index Pulses. 



FIGURE 10. WRITE COMMAND 



Winchester Disk Controller Devices 



3-127 



I SCAN ID j 



DE-ASSERT: INTRQ, 

ERRORS 
ASSERT: CIP, BSY 




DRIVE 
READY 



c 



ASSERT INTRQ, AC 
DE-ASSERT BSY, CIP 



3 



SEARCH FOR 
ANY ID FIELD 




UPDATE SDH, 
CYL, SECTOR. 
CYL POS, REG'S 


1 
^ 


f 




( PULSE BCR N. 

ASSERT ERROR, INTRQ, \ 
IDNF J 

^DE-ASSERT BSY, CIP^ 




*lf retries are disabled, path 
is tal<en after 2 index pulses. 



ASSERT BAD BLOCK BIT, 
ERROR BIT 



FIGURE 11. SCAN ID COMMAND 



3-128 



Winchester Disk Controller Devices 



FORMAT 

The Format Command is used to format one track 
using the Tasl< File and Sector Buffer. During this 
command the Sector Buffer contains additional 
parameter Information Instead of data. Figure 12 
shows the contents of the Sector Buffer for a 32 sec- 
tor track format with an Interleave factor of two. 

Each sector requires a two byte sequence. The first 
byte designates if a Bad Block Mark Is to be re- 
corded in the ID field. A 00 is normal; an 80 Hex is a 
Bad Block Mark. In the example of Figure 12, sector 
04 gets a Bad Block Mark recorded. The second 
byte indicates the logical sector number to be re- 
corded. Using this scheme, sectors can be recorded 
in any interleave factor desired. The rest of the Sec- 
tor Buffer is filled with any value, BRDY is asserted, 
and the WD2010 begins formatting the track. 

The Sector Count Register holds the total number of 
sectors to be formatted, while the Sector Number 
Register holds the number of bytes, minus three, to 



be used for Gap 1 and Gap 3. For instance, if the 
Sector Count value is 2 and the Sector Number 
value is 3, then 2 sectors are written and 6 bytes of 
4E Hex are written for Gap 1 and Gap 3. The data 
fields are filled with FF Hex, and the CRC or ECC is 
generated as specified by the related coding. 

The Gap 3 value is determined by the drive motor 
speed variation, data sector length, and the interleave 
factor. The Interleave factor is only important when 
1:1 Interleave is used. The formula for determining the 
minimum Gap 3 is: 

Gap3 = 2XMXS + K 

M = motor speed variation (e.g. .03 for ± 3%) 

S = sector length In bytes 

K = 18 for an Interleave factor of 1 

K = for any other Interleave factor 

When WF Is asserted or DRDY de-asserted the com- 
mand terminates and the AC error Is asserted. Figure 
13 shows the format that is written on the disk. 



O 

o 



o 

U1 











DATA 










ADDR 





1 


2 


3 


4 


5 


6 


7 


00 


00 


00 


00 


10 


00 


01 


00 


11 


08 


00 


02 


00 


12 


00 


03 


00 


13 


10 


80 


04 


00 


14 


00 


05 


00 


15 


18 


00 


06 


00 


16 


00 


07 


00 


17 


20 


00 


08 


00 


18 


00 


09 


00 


19 


28 


00 


OA 


00 


1A 


00 


OB 


00 


IB 


30 


00 


OC 


00 


1C 


00 


OD 


00 


ID 


38 


00 


OE 


00 


IE 


00 


OF 


00 


IF 


40 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FO 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 



FIGURE 12. FORMAT COMMAND BUFFER CONTENTS 



Winchester Disk Controller Devices 



3-129 



o 

lo 

o 



o 









- RE 




;tor 






INDEX 






=IELD 








■ data FIELD - 






r 


' 




1 


' 






, 


\ GAP4 


GAP1 
4E 
(1) 


14 BYTES 
■GO' 


A 

1 


1 

D 

E 
N 

T 


C L 
Y 
L W 


H 
E 
A 
D 


S 
E 
C 


C 
R 
C 
1 


C 
R 
C 
2 


3 BYTES 
00' 


12 BYTES 
■00' 


A 

1 


F 
8 


USER DATA 


2CRC 

OR 
4ECC 


2 BYTES 
'00' 


GAP3 
4E 
(1) 




1 1 

.....LA} 


: 1 ! 






' I I 








1 ' 1 

1 ! ' 




• 1 
1 1 
1 1 












mm//////////////, 


'2 




'//'////UJ/M 
















1 
1 






■> 


3 


> el 7 











































FIGURE 13. FORMAT 



ID FIELD 
A1 = 



A1 Hex with 
OA Hex clock 



IDENT = Bits 3,1,0 = Cylinder High 
FE = 0-255 Cylinders 
FF = 256-511 Cylinders 
FC = 512-767 Cylinders 
FD = 768-1023 Cylinders 
F6 = 1024-1279 Cylinders 
F7 = 1280-1535 Cylinders 
F4 = 1536-1791 Cylinders 
F5 = 1792-2047 Cylinders 

HEAD = Bits 0,1,2 = Head Number 
Bits 3,4 = 
Bits 5,6 = Sector Size 

00 = 256 

01 = 512 

10 = 1024 

11 = 128 

Bit 7 = Bad Block IVIark 

Sec# = Logical Sector Number 



DATA FIELD 

A1 = A1 hex with OA hex clock 
F8 = Data Address Mark; Normal Clock 
USER = Data Field 128 to 1024 Bytes 
NOTES: 

1 . GAP 1 and 3 length determined by Sector Number 
Register contents during formatting. 

2. The decision to assert RG is made 2 bytes after 
the start of DRUN. 

3. RG de-asserted: 

• If DRUN does not last until A1 

• When any part of ID does not match the one 
expected. 

• After CRC If correct ID has been read. 

4. Write splice recorded on disk by asserting WG. 

5. RG is suppressed until after write splice. 

6 . Not a proper A1 or F8, set DAIVI error. 

7 . Sector size as stated in ID field, plus two for CRC 
or 4 for ECC. 



3-130 



Winchester Disk Controller Devices 



c 



DE-ASSERT 

INTRO, ERRORS 

ASSERT CIP.BSY. 

BDRQ 




SET ABORTED 
COMMAND BIT 
AND ERROR BIT 



c 



ASSERT INTRO 

DE-ASSERT WG BCS 

BSY CIP 

PULSE BCR 




FIGURE 14. FORMAT COMMAND 



Winchester Disk Controller Devices 



3-131 



D 

o 
o 
o 

CJ1 



COMPUTE CORRECTION 

The Compute Correction Command determines tlie 
location and pattern of a single burst error, but does 
not correct it. The Host, using the data provided by 
the WD2010, must perform the actual correction. The 
Compute Correction Command is used following a 
data field ECC Error. The command initiating the read 
operation must specify no Retry. (T = 1). 

The Compute Correction Command first writes the 
four syndrome bytes from the internal ECC Register 
to the Sector Buffer then the ECC Register is clocked. 
With each clock, a counter is incremented and the 
pattern examined. If the pattern is correctable, the pro- 
cedure is stopped and the count and patten are writ- 
ten to the Sector Buffer, following the syndrome. The 
process is also stopped if the count exceeds the sec- 
tor size before a correctable pattern is found. 

When the command terminates the Sector Buffer con- 
tains the following data: 

Syndrome MSB 

Syndrome 

Syndrome 

Syndrome 

Error Pattern Offset 

Error Pattern Offset 

Error Pattern 

Error Pattern 

Error Pattern LSB 

As an example, when the Error Pattern Offset is zero 
the following procedure may correct the error. The 
first data byte of the sector is eclusive OR'ed with 
the MSB of the Error Pattern. , the second byte of data 
with the second byte of the Error Pattern, and the third 
byte of data with the LSB of the Error Pattern. 

If the Sector Buffer count exceeds the sector size, 
or the burst is greater than that selected buy the Set 
Parameter Command, the ECC/CRC error (bit 6) and 
the Error Status bit (bit 0) is set. 

The WD2010 defaults to a 5-bit correction span if a 
Set Parameter Command has not been executed 
since the last MR. 

SET PARAMETER 

This command selects the correction span to be used 
by the error correction process. A 5-bit span is 
selected when bit zero of the command equals 0, and 
11-bit span when 1. The WD2010 defaults to a five bit 
span following a Master Reset. 

ELECTRICAL CHARACTERISTICS 

MAXIMUM RATINGS 

Vcc with respect to Vss (Ground) + 7V 

Max Voltage on any Pin with 

respect to Vgs -0.5V to + 7V 

Operating Temperature. .0°C(32°F) to 70 °C(158 °F) 
Storage Temperature. .-55°C(-67 °F) to + 125 °C 
(257°F) 



( 

( 












COMPUTE 
CORRECTION 


) 




' 


ASSERT BCl 
PULSE BCR 






WRITE 4 

SYNDROME 

BYTES TO 

SECTOR BUFFER 




, 


COMPUTE 

CORRECTION 

PATTERN 


<^CORRECTABLE^> 


NO 










' 


YES 


ASSERT ERROR 
(BITO STATUS REG.) 

AND ECC ERROR 
(BIT 6 ERROR REG.) 














1 


WRITE TWO 

OFFSET BYTES 

TO SECTOR 

BUFFER 




, 




WRITE THREE 

ERROR PATTERN 

BYTES TO SECTOR 

BUFFER 






DE-ASSERT gCS 

ASSERT BDRO 

PULSE BCR 


^/leac 

C EDG 

^^^^BR 








)ING\. 


NO 




DY^/^ 
YES 






PULSE BCR 
ASSERT INTRQ 
DE-ASSERT BSY 


) 













FIGURE 15. COMPUTE CORRECTION COMMAND 



3-132 



Winchester Disk Controller Devices 



NOTE: 

Maximum limits indicate where permanent device 
damage occurs. Continuous operation at these limits 



is not intended and should be limited to those con- 
ditions specified in the DC Operating characteristics. 



DC Operating Characteristics TA = °C (32°F) to 70°C(158°F); Vss = OV, Vcc = +5V ±.25V 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


UNIT 


CONDITION 


IlL 


Input Leakage 




± 10 


hA 


V,N = -4 to Vcc 


Iql 


Output Leakage 
(Instate & Open Drain) 




± 10 


mA 


Vqut = .4 to Vcc 


V|H 


Input High Voltage 


2.0 




V 




V|L 


Input Low Voltage 




0.8 


V 




VOH 


Output High Voltage 


2.4 




V 


lo = -IOOmA 


Vol 


Output Low Voltage 




0.4 


V 


lo = 1.6mA 


Vol 


Output Low Voltage (Pins 21-23) 




0.45 


V 


lo = 6.0mA 
See Note 10 


'cc 


Supply Current 

For Pins 25, 34, 37, 39: 




220 


mA 


All Outputs Open 


V,H 


Input High Voltage 


4.6 




V 




VIL 


Input Low Voltage 




0.5 


V 




TRS 


Rise and Fall Time 




30 


nsec 


.9V to 4.2V 


CIN 


Input Capacitance 




15 


PF 





o 

o 



o 



ADDRESS 



CS 



-Xi^ 



p* Tase — 

^'^— TCSE- 



Ao,Ai.A2 STABLE 



^i: 



■Tre- 






X 



Thld- 



Jp^ 



>r 



-Trdr^ 



•Tdoh, 



> 



HOST READ TIMING 
HOST READ TIMING WD2010-05 WC = 5 MHz 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


UNIT 


CONDITION 


Use 


Address Setup to RE 


100 




nsec 




^DAC 


Data Valid from RE 




350 


nsec 




tRE 


Read Enable Pulse Width 


.4 


10 


pisec 




toOH 


Data Hold from RE 


20 


200 


nsec 




^HLD 


Address CS hold from RE 







nsec 




tpDR 


Read Recovery time 


300 




nsec 




tcSE 


CS Setup to RE 







nsec 


See Note 8 



Winchester Disk Controller Devices 



3-133 



ADDR 



CS 



X 



Aq, A,, Aj STABLE 



X 



^^ 



*AHW 



*SEW-»^ 



P- 



■tWER" 



■tCHW 



WE 



^^ 



■'we- 



-^ 



■'ds- 






j= 



^LEW 



tzi 



'lew 



HOST WRITE TIMING 



HOST WRITE TIMING WD2010-05 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


UNIT 


CONDITION 


^sew 


Address CS Setup to WE 





10 


ptsec 




bs 


Data Bus Setup to WE 


.2 


10 


fisec 




twE 


Write Enable Pulse Width 


.2 


10 


/isec 




bh 


Data Bus Hold from WE 


10 




nsec 




Uhw 


Address Hold from WE 


30 




nsec 




^WER 


Write Recovery Time 


1.0 




fiSec 


See Note 1 


tcHW 


CS Hold Time from WE 









See Note 9 


^LEW 


SDHLE Propagation Delay 


20 


150 


nsec 





"^ 



WE 

(OUTPUT) 






\ b!*- 'WRB --^ 
'VWE-*- 



DBO-7 



K 



DATA VALID 



I I 



> 



X 



— idi: 



♦WF 



'HWE 



-^ DATA VALID N— ^ If 



-'rr 



BUFFER WRITE TIMING 
BUFFER WRITE TIMING (READ SECTOR CMD) WD2010-05 WC = SMHz 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


twEV 


WE float to WE Valid 







100 


nsec 


Cl = 50 pf 


^WRB 


WE Output Pulse Widtfi 


300 


400 


500 


nsec 


See Note 4 


WWE 


Data Valid from WE 






150 


nsec 




tHWE 


Data Hold from WE 


60 




200 


nsec 




^RR 


WE Repetition Rate 


1.2 


1.6 


2.0 


/isec 




twF 


WE Float from BCS 







100 


nsec 


Cl = 50 pf 



3-134 



Winchester Disk Controller Devices 



BCS 



*REV- 



RE 

(OUTPUT) 



.^ 



\ i^ <REB ^y i 

I t-*»RDS*1 I I 



\ ^ 



■iV 



I tRF 



"EXEZEHX: 



<HRE 



DATA MUST 
BE VALID 



H*- 



RR »>| 



DATA MUST 
BE VALID 



>^,SEE 



o 

to 

o 



o 
en 



BUFFER READ TIMING 



BUFFER READ TIMING (WRITE SECTOR CMD) WD2010-05 WC = 5MHz 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


^REV 


RE float to RE Valid 







100 


nsec 


Cl = 50 pf 


^REB 


RE Output Pulse Width 


300 


400 


500 


nsec 


See Note 4 


^RDS 


Data Setup to RE 


140 






nsec 




^RR 


RE Repetition Rate 


1.2 


1.6 


2.0 


fisec 




tRF 


RE Float from BCS 






100 


nsec 


Cl = 50 pf 


^HRE 


Data Hold from RE 









nsec 





1 1 

I"* — tRD — •n 


/ 


1 

|-«-<X1-»4*tX2*^ 


RCLK ^1 > ^1 > 

I-* tRCF ►! 


_^ ^ 




^l^tDRN»5(^ 



READ DATA TIMING 
READ DATA TIMING WD2010-05WC = 5 MHz 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


^RCP 


RCLK Pulse Width 


95 




2000 


nsec 


50% Duty Cycle 


txi 


RD from RCLK Transition 







tRCP 


nsec 




tx2 


RD to RCLK Transition 


20 




^RCP 


nsec 




^RD 


RD Pulse Width 


40 




tRCP 


nsec 




^DRN 


DRUN Pulse Width 


30 






nsec 




tRCF 


RCLK Frequency 


.250 


5 


5.25 


MHz 


See Note 6 



Winchester Disk Controlier Devices 



3-135 



D 

o 



o 

U1 



tWD— »^ h*— 






- 


i f V 


\ 


i -^ ^-^^^ 






WCLK /| T f\ 

^ tWCF ►! 


\ 


1 


_7f \ 

1 

-♦l |-* — ^ELW 
1 1 

1 

f " 


^■A / 




bAMLY 




i 



WRITE DATA TIMING 
WRITE DATA TIMING WD2010-05WC = 5 MHz 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


^WC 


WCLK Pulse Width 


95 




2000 


nsec 


50% Duty Cycle 


^WD 


Propagation Delay 
WCLK to WD 


10 




65 


nsec 




^WLE 


WCLK to Leading 
EARLY/LATE 


10 




65 


nsec 




^ELW 


WCLK to Trailing 
EARLY/LATE 


10 




65 


nsec 




Wf 


WCLK Frequency 


.250 


5 


5.25 


MHz 


See Note 6 



3-136 



Winchester Disk Controller Devices 



BRDY 
BDRQ 



A 



r^BRY ■ 



I 



^ 



^L 



>= 



.*BCR. 



^ 



yK—t sTP--\_ 



yl^*-tiDx-*^^ 




MISCELLANEOUS TIMING 
MISCELLANEOUS TIMING WD2010-05 



MISCELLANEOUS TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


^RQ 
^BCR 


BDRQ Reset from BRDY 


20 
1.4 


1.6 


200 
1.8 


nsec 
fisec 




Buffer Counter Reset 




Pulse Width 












tsTP 


Step Pulse Width 


1.4 
7.8 


1.6 
8.0 


8.2 
8.2 


^jsec 


See Note 2 


t|DX 


Index Pulse Width 


500 






nsec 




^MR 


IVIaster Reset Pulse 


24 






WC 


See Note 3 


^BRY 


BRDY Pulse Width 


400 






nsec 


See Note 5 


*MRB 


MR Trailing to BCR 





3.2 


6.4 


/isec 




^MRW 


MR Trailing to Host Write 


6.4 






fisec 





o 

o 

-X 

O 
I 

o 

01 



NOTES: 

1. AC timing measured at Vqh = 2.0V, Vql = 0.8V, 
Cl = 50 pf. 

2. 1.6 fisec. is typical pulse for a step rate of 32 
jisec/step. 8.0 /isec typical pulse for all other step 
rates. Last step pulse at 3.2 /isec/step rate up to 
8.2 fisec. 

3. 24 WCLK periods (4.8 ^isec at 5.0 MHz) 

4. 2 WCLK ± 100 ns. 

5. The true to false transition of BRDY should not 
come sooner than 2 WCLK from true to false tran- 
sition of BDRQ. 

6. tRCF = twCF±15%- 



7. 2 WCLK ± 50 ns. 

8. RE may precede CS if CS plus RE meets the 
tpE width. 

9. WE may precede CS if CS plus RE meets the 
twE width. 

10. It may be desirable to connect a 1 K Q pullup 
resistor to pins 21-23. 



Winchester Disk Controller Devices 



3-137 



3-138 Winchester Disk Controller Devices 



WESTERN DIGITAL 

CORPORATION 

WD10C20-05 Self-Adjusting Data Separator 



FEATURES 

• PROCESSES ALL SENSITIVE READ/WRITE DATA 
SIGNALS 

• CMOS TECHNOLOGY 

• DESIGNED FOR ST506/ST412 AND WD1010/ 
WD2010 INTERFACE 

• HIGHLY STABLE LC TYPE VOLTAGE 
CONTROLLED OSCILLATOR 

• SELF ADJUSTING VCO COMPENSATES FOR 
COMPONENT, TEMPERATURE, VOLTAGE, AND 
AGING VARIATIONS 

• FREQUENCY DETECTION ON CRYSTAL 
REFERENCE AND DATA SYNCHRONIZATION 
FIELD, ELIMINATES 180 DEGREE LOCK DUE TO 
DRIVE ASYMMETRY, AND ELIMINATES 
HARMONIC LOCK FROM WRITE SPLICES 

• ZERO PHASE STARTUP PROVIDES FASTER, 
MORE PREDICATABLE LOCK ACQUISITION 

• LOCKS TO CRYSTAL REFERENCE WHILE IDLE 

• DUAL GAIN: HIGH FOR FASTER ACQUISITION 

LOW FOR MORE JITTER 
REJECTION WHILE TRACKING 

• EXTERNAL PUMP CURRENT CONTROL 

• AVAILABLE IN 28-PIN DIP OR QSM PACKAGE 

• INTEGRATED CRYSTAL OSCILLATOR 

• ACCOMMODATES OTHER DATA RATES 
THROUGH SELECTION OF EXTERNAL 
COMPONENTS 



ADJUST 

vss 

WGATE 

RGATE 

WPCEN 

LATE 



EARLY 

WDATA 

WCLK 

XTALIN 

XTALOUT 

DRUM 

DRUNRC 

RMFM 



1 • 


^J 


28 


2 




27 


3 




26 


A 




25 


5 




24 


6 




23 


7 




22 


8 




21 


9 




20 


10 




19 


1 1 




18 


12 




17 


13 




16 


14 




15 



IPUMP 
VCOOUT 
VCOIN 
PUMP 

vcc 

RCLK 

RDATA 

TLATE 

THALFWIN 

TEARLYZP 

DLYDR 

TNOMINAL 

WMFM 

TFULLWIN 



R 
V C 
C L 
C K 



VCOIN □ 26 
VCOOUT □ 2 7 
IPUMP r~| 28 
ADJUST 

Vss 

WGATE tZ 
RGATE tZ 



n nn n n n n 

25 24 23 22 21 20 19 



1 • 

2 

3 

4 



5 6 7 8 9 10 11 

u u u u uu u 



D DLYDR 
Z3 TNOMINAL 
D WMFM 
15 Zi TFULLWIN 
14 pi RMFM 
1 3 □ DRUNRC 
12 tD DRUN 



L E W W X X 

A A D C T T 

T R A L A A 

E L T K L L 

Y A 10 

N U 

T 

PIN DESIGNATION 



O 

o 
O 

O 



Winchester Disk Support Devices 



4-1 



o 
O 
ro 
o 



DESCRIPTION 

The WD10C20-05 is an LSI device implemented in 3 
micron high-speed CMOS, designed to be compati- 
ble with the WD1010 and WD2010 Winchester Disk 
Controllers and ST506/ST412 disk drives. In a typical 
application, it handles all sensitive read/write signals 
between a WD1010/WD2010 and the data 
drivers/receivers. Read data corresponds to previous 
write data, with added phase, frequency, and write 
splice noise. The WD10C2(H)5 removes these sources 
of noise and presents a clean, digital read signal to 
the WD1010/WD2010. 

While reading, the WD10C20-05 performs phase- 
locked loop data synchronization on data read from 
the drive. An on-board Sync Field detector 
automatically switches the PLL from the stable 
crystal reference to the read data. Zero-phase star- 
tup results when the VCO is halted and restarted in 
phase with the data to eliminate initial acquisition in 
the wrong frequency direction. Frequency-phase 
detection is used at the beginning of the Sync Field 
to quickly and reliably acquire lock to the data. Use 
of this technique eliminates susceptibility to har- 
monics and asymmetry. The WD10C20-05 then swit- 
ches to phase-only detection to complete the phase 
acquisition before the end of the Synch Field and to 
enable tracking of random IV1FM read data. When 
switching to phase detection, the WD10C20-05 
reduces the error amplifier gain for better rejection 
of drive jitter. A precisely aligned detector samples 
the data at twice the underlying data rate to remove 
the phase jitter. The regenerated signal, along with 
a fixed-phase synchronous clock, are output to the 
WD1010/WD2010 digital circuits. 



While writing, the WD10C20-05 conditions the write 
data to the drive. IVIFM data from the WD1010/WD2010 
is precisely clocked, with a signal at twice the data 
frequency, to minimize digital phase noise. If 
precompensation is enabled, early, nominal, and late 
taps on an external delay line are multiplexed through 
matched delay paths to produce synchronized, 
precompensated write data, which is sent directly to 
the drive's write circuits. 

The WD10C2(H)5 is designed to work at the 5 Mbit/sec 
data rate of the ST506/ST412 interface. Other data 
rates may be accommodated through the proper 
selection of external components. 

NOTE: To assure reliable operation of the 
WD10C20-05, it is recommended that the 
WD10C20-05 KIT, number 77-000014 be used. 
If the user elects to not use the kit, the exter- 
nal components as shown in Figure 1, must 
be selected from the parts listed in the 
WD10C2O05 Application Note. The placement 
of these components must conform to the 
layout illustrated in the Application Note. (The 
Application Note is available through your 
Western Digital field representative.) 



4-2 



Winchester Disk Support Devices 



+ 12 



L101 

FERRITE BEAD 



" I 1 



R102 



T.A.S. 

-^A^ — f 

R104 



IN 
U102 
VCC 12 
24 



GND 6° 
DELAY 
LINE 96 



Ky 



12 19 



10 21 



6 20 

• 



WD-tOIO 
WD2010 



-i * s- 



U101 
WD10C20 



TEARLYZP 

TNOMINAL VCOOUT 

TLATE 

THALFWIN 

TFULLWIN 



RDATA 

DRUM 

RCLK 

WCLK 

RGATE 

WGATE 

WPCEN 

LATE 

EARLY 

WDATA 



7 



m: 



i 



CR102 

■-►11-4 



t — \w 



H— « 



, C112 < R107 



V 



R105 

-VsAr 



D 



*RWC CONNNECTS TO WPCEN IF REDUCED WRITE CURRENT IS TO START AT THE 
SAME TIME AS WRITE PRECOMP. THE WD1002S-WX2 USES LS/DIR/WPC. 



FIGURE 1. EXTERNAL COMPONENTS 



V 



V 



O 

o 
O 

O 



Winchester Disk Support Devices 



4-3 



^ 




DRUN 






















RMFM ^ 


D 
















\ 


o 
O 




SYNC FIELD 
DETECTOR 






POWER-ON 
RESET 




SELF-ADJUST 
CIRCUIT 


ADJUST _ 


lO 

o 


































t " 




PUMP ^ 




v 


RGATE 






' 


1 












1 










1 » 








STEERING 
CONTROL 








CHARGE 
PUMPS 






FILTER 






V- 


WGATE 


















? 


WCLK 






t 






'r 








\ 


\ 








ZERO PHASE 
STARTUP 




h 






f. J. 




1 










vco 


VCOOUT 




s. 


WDATA ^ 




T 


' 




















\ 


' 
















t ° 




CRYSTAL 
OSCILLATOR 
AND CLOCK 
GENERATOR 




PLL MUX 




i, 




PHASE 
FREQUENCY 
DETECTOR 






\ 




VCOIN ^ 




















' 


' 




1 


1 










1 


1 


1 








WRITE 

DATA 

CONDITIONER 














WPCEN 












' 






PRECOMPENSATION 
MUX 










/ 


EARLY 


WMFM 




>— 


► 

LATE 


















RDATA 






\ i 


1 i 












DLYDR 






\. 






' 


r 










DELAY 

AND 
PULSE 
FORMER 


TEARLYZP 






TNOMINAL 








TLATE 


















READ DATA 
DETECTOR 








THALFWIN 
































RCLK 











FIGURE 2. WD10C20 BLOCK DIAGRAM 



4-4 



Winchester Disk Support Devices 



PIN DESCRIPTION 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


1 


ADJUST 


ADJUST 





Provides self calibration of the PLL 


2 


VSS 


GROUND 






3 


WGATE 


WRITE GATE 


1 


WGATE is asserted when the controller writes on the 
disk 


4 


RGATE 


READ GATE 


1 


RGATE is asserted when the controller intends to read 
from the disk. RGATE causes the WD10C20-05 to 
remain locked onto the incoming data stream. 


5 

6 

7 


WPCEN 


WRITE 

PRECOMP 

ENABLE 


1 

1 
1 


WPCEN is asserted to enable the EARLY and 
LATE signals from the controller. WPCEN may be 
connected to the Reduce Write Current (RWC) 
available from the WD1010/WD2010 if Write Precomp 
is to occur at the same time as the Reduced Write 
Current, or to an independent source if they start at 
different times. 

Asserted by the Controller to delay the writing of a 
bit to the disk. 

Asserted by the Controller to advance the writing of 
a bit to the disk. 


LATE 


LATE 


EARLY 


EARLY 


8 


WDATA 


WRITE DATA 


1 


Non-Synchronized and Non-Precompensated MFM 
data from the controller to be written on the disk via 
WMFM. 


9 


WCLK 


WRITE CLOCK 





WCLK is equal to XTALIN -r- 2 and is used by the con- 
troller to generate the data to be written. 


10 


XTALIN 


XTALIN 


1 


XTALIN is a crystal controlled oscillator input used 
by a number of internal control functions. Divided by 
2 it develops WCLK. XTALIN may also be driven by 
an external driver in which case XTALOUT is left open. 
The input level of this pin is not TTL and must be 
guaranteed by the clock source. 


11 


XTALOUT 


XTALOUT 





XTALOUT is the crystal controlled oscillator output. 
When an external frequency source is used, this pin 
is left open. 


12 


DRUN 


DATA RUN 





DRUN is a signal that discriminates between frequen- 
cies on RMFM. It goes low for low frequencies and 
high for high frequencies. Its nominal threshold is set 
to 1-3/8 bit times using DRUNRC. DRUN remains 
asserted for a continuous stream of one's or zero's, 
ie: Sync Field. 


13 


DRUNRC 


DRUNRC 


1 


Connected to an external RC circuit for the genera- 
tion of DRUN. 


14 


RMFM 


READ MFM 
DATA 


1 


MFM Data received from the drive. A nominal 4K ohm 
internal pullup resistor allows tri-state multiplexing 
of the driver's data receivers. 


15 


TFULLWIN 


TFULLWINDOW 


1 


Delay line tap for generating full window RMFM 
pulses. 


16 


WMFM 


WRITE MFM 
DATA 





Preconditioned WDATA ready to be written on the 
disk. WMFM is held low when WGATE is low. 


17 


TNOMINAL 


TNOMINAL 


1 


Delay line tap for uncompensated write data. 



Winchester Disk Support Devices 



4-5 



PIN DESCRIPTION (Continued) 



D 

O 
O 
ro 
o 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


18 


DYLDR 


DELAY LINE 
DRIVER 





Drives an external delay line. 

\ 


19 


TEARLYZP 


TEARLY ZERO 
PHASE TIMING 


1 


Delay line tap for early precompensated write data and 
for zero phase startup of the VCO. 


20 


THALFWIN 


THALFWINDOW 


1 


Delay line tap for generating the enable phase delay 
when in phase detection mode. 


21 


TLATE 


TLATE 


1 


Delay line tap for late precompensated write data. 


22 


RDATA 


READ DATA 





RDATA is RMFM synchronized to RCLK. The clock is 
removed from the RMFM by the controller. 


23 


RCLK 


READ CLOCK 





RCLK is equal to one half of VCO and is synchronized 
to RDATA during a read operation and to WCLK while 
in an idle state. 


24 


VCC 


POWER SUPPLY 


1 


+ 5V Power Supply. 


25 


PUMP 


PUMP 


I/O 


Charge PUMP to the PLL filter. Also a voltage input 
to the self-adjust sensing circuitry. 


26 


VCOIN 


VOLTAGE 
CONTROL 
OSCILUTOR 
INPUT 


1 


Input to the VCO gain stage. VCOIN is clamped low, 
and then released during zero phase startup. 


27 


VCOOUT 


VOLTAGE 
CONTROL 
OSCILUTOR 
OUTPUT 





Output from the VCO gain stage. 


28 


IPUMP 


IPUMP 


1 


An external resistor connected to IPUMP establishes 
the magnitude of the charge pump current and 
ADJUST current. 



ARCHITECTURE 

The WD10C20-05, with the necessay external com- 
ponents, provides the data interface between the 
WD1010 or WD2010 and an ST506/ST412 compatible 
drive. There are eight major functional sections within 
the WD10C20-05: 

• Synchronized Field Detector 

• Steering Control 

• Phase-locl<ed Loop (PLL) 

Phase-frequency Detector 

Charge Pumps 

Filter 

Voltage Controller Oscillator (VCO) 

Zero Phase Startup Circuit 

Self Adjustment Circuit 

• Read Data Detector 

• Crystal Oscillator 

• Write Data Conditioner 

• Delay And Pulse Former 

• Power-on Reset 

SYNCHRONIZATION FIELD DETECTOR 

The Synchronization Field Detector discriminates bet- 
ween the OO's of a Synchronization Field and the low 



frequency data immediately preceding these fields. 
The criterion used is pulse period discrimination on 
the RMFM data. The external resistor and capacitor 
connected to DRUNRC sets the nominal detection 
threshold of 1-3/8 bit times. DRUN goes low for long 
periods and high for short periods. 

STEERING CONTROL 

This logic controls the sequencing of events when 
the WD10C2OO5 is switching between read, write and 
idle modes. When switching, the Steering Control 
disables the Phase-Frequency Detector and Charge 
Pumps, switches the MUX source, invol<es zero-phase 
startup, selects the velocity locl< mode of the Phase- 
Frequency Detector, and high gain on the Charge 
Pump. After the zero-phase startup is complete, the 
Phase-Frequency Detector and Charge pumps are 
enabled. If the device is in read or write mode, after 
four byte times the Steering Control switches to phase 
detection, and the charge pumps are set to low gain. 

PHASE-LOCKED LOOP 

Phase-Frequency Detector 

The Phase-Frequency Detector operates in one of two 
modes: velocity locl< mode or phase-only detection. 



4-6 



Winchester Disk Support Devices 



Velocity lock mode is used for acquisition when the 
PLL is switched to read or write data or when the PLL 
is following the reference crystal oscillator. 

The Steering Control logic switches to the Phase-only 
mode when frequency and phase acquisition is nearly 
complete. Internal delay paths have been carefully 
matched to minimize introduction of a phase en-or due 
to switching. The phase-only mode must be used to 
lock to the MFM following the Sync Field, since that 
contains the three MFM frequencies. 

In either mode, the Phase-Frequency detector con- 
verts a phase difference between the VCO and the 
input to a pulse width equal to the phase difference. 
The polarity of the phase error determines whether 
a signal is directed to the pump up or pump down 
circuitry in the Charge Pump section. 

Charge Pumps 

The Charge Pump circuit converts the widths received 
from the Phase-Frequency Detector to proportional 
amounts of charge, into or out of the filter. The gain 
of the Charge Pumps is set by the input current of 
the IPUMP signal. This current is set by an external 
resistor connected to the VCC. 

Filter 

The Filter converts the current pulses from the Charge 
Pumps to a voltage ouptut to the VCO. It also pefomns 
the sample-and-hold function necessary for an edge 
locked PLL, and is also necessary during the zero 
phase startup period. As shown in Figure 1, one of 
the filter's capacitors (C110) is also part of the VCO's 
series resonant oscillator. 

The filter must meet the specific requirements of 
acquisition time, capture range, and jitter ejection, 
and within the context of its effect on VCO opera- 
tion. The filter functions to block high frequency 
signals due to RMFM read data jitter, and passes the 
low frequency signals of the RMFM. 

Voltage Controlled OscillatOF 

The VCO is a series resonant LC oscillator. The active 
gain element that provides the energy to sustain 
oscillation is within the WD10C20-05, between the 
VCOIN and VCOOUT pins. An inexpensive varactor 
controls and tunes the VCO. The filter connects to 
the anode of the varactor and provides the voltage 
for loop operation of the PLL. Higher voltages at the 
VCO input correspond to lower frequencies, and lower 
voltages correspond to higher frequencies. The self- 
adjustment circuit connects to the cathode of the 
varactor. The voltage bias at this point detemnines the 
location of the VCO's V-F characteristic curve, and 
is set for a favorable VCO input voltage at the nominal 
frequency of the VCO. 

Zero Phase Startup Circuit 

The VCOIN connects to the Zero Phase Startup Cir- 
cuit, which contains the logic necessary to turn a 
clamp on or off. This clamp, in turn, enables or 



disables the VCO gain stage. When the WD10C20-05 
changes the PLL input signal, the clamp is turned on ^ 
for a minimum of one input data period. This stops ^ 
the VCO gain and removes the AC energy from the 2 
passive VCO components. The VCO is now in a ^ 
known state, and the time between the release of the ^ 
clamp and the time the first edge of the VCO reaches o 
the Phase Frequency Detector can be predicted. This 
event is made to coincide with the arrival of a data 
pulse by the delay between TEARLYZP and 
THALFWIN. 

Self Adjustment Circuit 

The Self Adjustment Circuit (SAC) serves to slowly 
maintain the VCO's input voltage near the sense level. 
It performs compensation for component variations 
In much the same way as manual adjustments, as 
well as dynamic variations such as temperature, 
voltage and aging. Another advantage of this circuit 
is the heavy RC filtering of the + 12 volt supply. The 
SAC tunes the VCO so that its nominal output fre- 
quency of twice the data rate corresponds to an input 
voltage favorable to the Charge Pumps. This voltage 
is approximately half of the VCC, and centers the cap- 
ture range. The PUMP signal connects to an internal 
comparator and senses the VCO input voltage to 
determine whether it is above or below the threshold 
voltage (VSENSE). 

The comparator is sampled at a low frequency derived 
from the crystal. The output is used as the up / down 
control to a six-bit counter. At power-on, this counter 
is set to half scale. The least significant two bits are 
for noise immunity only. The most significant four bits 
connect to a digital-to-analog converter (DAC) that 
controls the current-sinking ability of the ADJUST 
signal. To convert the ADJUST signal current to a 
voltage, it is connected externally through a resistor 
to the -1- 12V. To filter the DAC steps and transients, 
the ADJUST is connected to two capacitors. A resistor 
from the ADJUST signal to the cathode of the VCO 
varactor completes the circuit. Refer to Figure 1. 

READ DATA DETECTOR 

The Read Data Detector produces RCLK and RDATA. 
RCLK is a square wave equal to one half of the VCO 
frequency. During data tracking, RCLK mirrors the 
slowly varying frequency of the RMFM. RDATA is a 
regenerated form of the RMFM, with the jitter 
removed and one-half bit-time pulse widths, and is 
exactly synchronous with RCLK. RCLK edges occur 
nominally in the center of RDATA to allow sufficient 
setup and hold time for the digital circuits in the 
WD1010/WD2010 using these signals. 

CRYSTAL OSCILLATOR 

The Crystal Oscillator is designed to operate in the 
parallel resonant mode, with an external crystal and 
two capacitors. It generates the WCLK signal used 
externally. Internally, various divisions of it are used 
by the Write Data Conditioner, PLL, and SAC. 



Winchester Disk Support Devices 



4-7 



o 

o 

o 

lo 
o 



When an externally generated clock is desired, the 
crystal and capacitors are omitted. The XTALIN pin 
Is connected to the clock source, and XTALOUT is 
left disconnected. The input levels of XTALIN are not 
TTL and must be guaranteed by the clock source. 

WRITE DATA CONDITIONER 

The Write Data Condit ioner sa mple s and precisely 
synchronizes WDATA, EARLY, and LATE on the 
leading and trailing edges of WCLK. When WGATE 
Is asserted, the DLYDR signal is a direct derivative 
of WDATA and is connected to the input of the delay 
line. It returns to the WD10C20-05 via the TEARLYZP, 
TNOMINAL, and TLATE input signals. When WPCEN 
is de- asserted, WMFM follows th e TNOM INA L signa l. 
When WPCEN is asserted, the EARLY and LATE 
signals select the TEARLYZP and TLATE inputs, 
respectively. The differential delay between 
TEARLYZP and TNOMINAL at the delay line defines 
the amount of early precompensation, and similarly, 
the differential delay between TNOMINAL to TLATE 
defines the amount of late precompensation. 

When WGATE is asserted, one of the initial MFM 
pulses Is suppressed to create an interval of two bit 
times. This ensures that DRUN will go low at the 
beginning of a Sync Field preceding a data field, so 
that zero phase startup and velocity lock are executed 
properly. When WGATE is de-asserted. WMFM is held 
low. 



DELAY AND PULSE FORMER 

The Delay And Pulse Former includes the external 
delay line as well as logic internal to the WD10C2(K)5. 
In response to rising edges, it produces positive 
pulses slightly longer than one detection window, 
which is half of one bit time. The taps are also used 
for write precompensation, zero-phase startup, and 
defining the enable window for phase detection. 
Depending on the mode of operation, its input is 
either RMFM, synchronized WDATA, or WCLK. 

POWER-ON RESET 

This integrated function is used to reliably set flip- 
flops to a predictable state during the application of 
the VCC. It is used by the Steering Control and SAC 
sections. 

DATA SEPARATOR CIRCUIT PERFORMANCE 
SPECIFICATIONS 

The following specifications apply when the external 
components are selected as specified and operate 
within the following ranges: 

Vcc = -f 5V ± .25V with < 100 mV ripple, to 30 KHz 
+ 12V= + 12V ± 1.2V with < 200 mV ripple, to 30 

KHz 
Temperature = 0° to 70°C (32° to 158°F) 



PHASE-LOCKED LOOP: 

• Acquisition Time < 12.8 usee (16 usee 

• Capture Range > ± 2.2% ( ± 1 % drive 

• Jitter Rejection >40 db at 2.5 MHz 

• Damping Factor min .7 typ. 1 max 1.4 

min .5 typ. .7 max 1.1 

• KD Error Amplifier min 2 mA 

Gain typ 6 mA 

max 10 mA 
min 1 mA 
typ 4.3 mA 
max 6.8 mA 

• Error Amplifier max 2:1 

Balance Ratio 



Ko VCO Gain 



min 4.5% per volt 
typ 5% per volt 
max 7.5% per volt 



from DRUN high) 
± .1 % crystal Osc.) 

Velocity Lock 
Phase Detection 
Velocity Lock 
Operating Range 
VSENSE ± 1060 mv 
Phase Detection 
Operating Range 
VSENSE ± 950 mV 
Phase Detection 
Operating Range 
VSENSE ± 950 mV 
Phase: ± 5 to 
± 40 nsec 



FREQUENCY DETECTOR 

DRUN must be high in response to RMFM rising edge 
to rising edge periods less than 250 nsec. DRUN must 
be low for periods greater than 300 nsec. 
CRYSTAL OSCILLATOR 

The operational frequency must be within ± .1% of 

10 MHz. 

PHASE DETECTOR/CHARGE PUMPS 

Phase Decision Points 



While in the phase detection mode, the phase dif- 
ference from null (zero pump current) to the decision 
points must be no less than ±40 nsec. 

VCO GAIN 

Over the VCO input voltage range, VSENSE nominal 
± 1060 mV, the VCO gain must be within the range 
of 4.5% to 7.5% per volt. There must be no interrup- 
tions in its characteristic V-F curve over the input 
voltage range. 



4-8 



Winchester Disk Support Devices 



WD10C20-05 ELECTRICAL CHARCTERISTICS 

MAXIMUM RATINGS 

Vcc with respect to Vss +5.5 Volts 

Max Voltage range on any pin -0.5V to 0.5V > Vqc 

(except ADJUST) with respect to Vss 

Max Voltage Range on ADJUST with respect to Vss ■0-5V to + 13.2V 

Operating Temperature 0°C(32°F) to 70°C(158°F) 

Storage Temperature -65°C(-85°F) to 150°C(302°F) 

NOTE 

Maximum limits indicate where permanent device damage occurs. Con- 
tinuous operation at these limits is not intended and should be limited 
to those conditions specified in the DC Operating Characteristics 

DC OPERATING CHARACTERISTICS 
Ta = 0°C (32°F) to 70°C (158°F) 
Vcc = +5V ±.25V 

Input signals: 

TEARLYZP, TNOMINAL, TL ATE, THALFW IN, TFULLWIN, RGATE, 

WGATE, WPCEN, WDATA, EARLY, LATE, RMFM 



O 

_^ 

o 
O 
to 
o 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


V|H 


Voltage Input High 
Voltage Input Low 


3.0 




.8 


V 
V 





Input signals: 

TEARLYZP, TNOMINAL, TLATE, THALFWIN, TFULLWIN, 

RGATE, WGATE, XTALIN, VCOIN (Clamp off) 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


'in 


Input leakage 






±10 


mA 


V,N -- 


= GND to Vcc 


Input signals: \A 
















fDATA, EARLY, LATE 




SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


llH 
IlL 


Current Input High 
Current Input Low 






+ 10 

-4 


mA 

mA 


V|H -- 
V|L = 


= 3.4 V* 
= .45 V* 


Input signal: WPCEN 


SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


llH 
IlL 


Current Input High 
Current Input Low 






+ 10 
-2 


mA 


V,H -- 
V|L = 


r 3.4 V* 
-- .4 V* 



*These inputs may or may not have an internal pullup resistor. 
In either case, if I|h and I,l meet these specs, the inputs will be driven correctly. 



Winchester Disk Support Devices 



4-9 



o 

o 

o 

o 



Input signal: RMFM 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


l|H 

l|L 


Current Input High 

Current Input Low 








-2.5 


mA 

mA 


V|H = 3.4 V 

V|L = .4 V 

Internal pullup resistor 



Input signal: XTALIN 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


V|H 


Voltage Input High 
Voltage Input Low 


3.6 




.6 


V 
V 





Output signals: WCLK**, WMFM, DLYDR 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


VOH 

Vol 

Trise 

"•"fall 


Voltage Output High 

Voltage Output Low 
Rise Time .8 to 2.0 V 
Fall Time 2.0 to .8 V 


2.4 




.4 
10 
10 


V 

V 
nsec 
nsec 


loH = -1 mA 
Iql = 4 mA 
CL = 30 pf 
CL = 30 pf 



Output signal: WCLK* 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


VoH 

Vol 
Trise 

TpALL 


Voltage Output High 

Voltage Output Low 
Rise Time .9 to 4.2 V 
Fall Time 4.2 to .9 V 


4.6 




.2 

30 
30 


V 

V 
nsec 
nsec 


loH = -100 /tA 
Iql = 1 rnA 
CL = 30 pf 
CL = 30 pf 



**WCLK has two requirements. It must be able to drive special WD1010 / WD2010 inputs, 
as well as a buffer at TTL levels. In any application, the total capacitance of the 
WD1010/ WD2010, buffer, and PC board, must not be more than 30 pf. The total input 
current of the WD1010/ WD2010 and buffer at the different input voltages must not 
exceed the above specification. 

Output signals: RCLK, RDATA, DRUM 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


VoH 

Vol 
Trise 

TpALL 


Voltage Output High 

Voltage Output Low 
Rise Time .9 to 4.2 V 
Fall Time 4.2 to .9 V 


4.65 




.2 
30 
30 


V 

V 
nsec 
nsec 


loH = -20 liA 
ioL = 20 /lA 
CL = 20 pf 
CL = 20 pf 



4-70 



Winchester Disk Support Devices 



Self Adjust, Pump, and Power 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


Vs 


VSENSE Threshold 




2.4 




V 




'a 


ACQUISITION PUMP Current 




±6 




mA 


3.57Kon IPUMP*** 


It 


TRACKING PUMP Current 




±4.5 




mA 


3.57K on IPUMP*** 


'jMX 


ADJUST Max Current 


.4 


.6 


1.0 


mA 


3.57K on IPUMP*** 


'jMN 


ADJUST Min Current 






±10 


mA 




'cc 


Power Supply Current 




40 




mA 


3.57K on IPUMP, 5MHz 



o 
O 

o 



***Depending upon the application, there are specific requirements upon the pump currents and their relation- 
ship to VSENSE. This document is written for 5 Mbit/sec, WD1010/WD2010, ST506/ST412 drive. 

AC OPERATING CHARACTERISTICS 

Timing on signals RDATA, RCLK, WCLK, and DRUN are measured at the voltage halfway between the 
WD1010/WD2010's VIH and VIL: 2.55 Volts. All other signals are measured from the 1.4 volt transition. All timing 
is measured with the load capacitance, CL = 50 pf. 



RMFM 




- t2 






/ 

H 


\ 



FIGURE 3. DISK DRIVE READ DATA, PULSE FORMING 
TABLE 1. DISK DRIVE READ DATA, PULSE FORMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


t2 


RMFM Pulse Width High 
RMFM Pulse Width Low 


20 
25 




150 


nsec 
nsec 





WCLK 
EARLY 

Due 




-4— 

1 


--K-'9-H 


DC 


X 


y X 


-H '7 l^ 


-f.l- 


-H ' 




-H'Bf— 

1^.7-H 1 




1-^ '8 h H'Bt^ 

1 / \ 







FIGURE 4. WRITE SETUP/OLD 
TABLE 2. WRITE SETUP/HOLD 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


t7 


Hold Time 
Setup Time 
WCLK Pulse Width 


5 

20 
95 




105 


nsec 
nsec 
nsec 




Setup and Hold time is independent of the application of the WD10C20-05. 



Winchester Disk Support Devices 



4-11 



o 

o 

ro 
o 




FIGURE 5. DRUN 



TABLE 3. DRUN 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


tii 


DRUN Low Pulse Width 


30 






nsec 


* 



'No requirement on DRUN pulse widtli high. 







"\ 


H '14 >\- ti5 ^ 




Rr\\< / \ 


/ 


/ \ / 

tl9 — H h — 


J 


RRATA / 

tie H " — 

tl9 " 


\_ 

h — 


/ \ 

" ti6 4- ti7- 

— H ti8 1- 



FIGURE 6. RCLK, RDATA TIMING 
TABLE 4. RCLK, RDATA TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


tl4 


RCLK High Pulse Width 


93 




108 


nsec 




tl5 


RCLK Low Pulse Width 


93 




108 


nsec 




tl6 


RDATA High Pulse Width 


93 




108 


nsec 




tl7 


RDATA Low Pulse Width 


93 




108 


nsec 




tl8 


RCLK Edge to RDATA 
Rising Edge 


30 






nsec 


Max is implicit in tigmin 


tl9 


RDATA Rising Edge To 
RCLK Edge 


30 






nsec 


Max Is implicit in tigmin 



ti4 and ti5 each define an MFM detection window. The rising edge of RDATA must occur within the window. 
ti4 + ti5 = the current bit cell time. 



4-12 



Winchester Disk Support Devices 



TFULLWIN 
DLYDR 












h — 


<20 - 


—*\ 


\ 


/ 






~\ 



FIGURE 7. DLYDR, TFULLWIN TIMING 
TABLE 5. DLYDR, TFULLWIN TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


^20 


DLYDR Shutoff Time 


12 




36 


nsec 





PACKAGE DIAGRAMS 







28 LEAD PLASTIC PH 




" nr " '7 T 



JJ u u u u u u 



4318i381 

■ I .0201.005 




/^P 



.3ia±381 

I I 020 t 005 
.508±.127 




28 LEAD PLASTIC QUAD JH 



Winchester Disk Support Devices 



4-13 



4-14 Winchester Disk Support Devices 



WESTERN DIGITAL 

CORPORATION 

WD1014 Error Detection/Support Logic Device 

FEATURES 



32-BlT ECC POLYNOMIAL 

BURST CORRECTION TO 11-BITS 

MULTIPLE ERROR BURST DETECTION 

DATA TRANSFER RATE OF 5-MBITS/SECOND 

PROCESSES CHECK/SYNDROME BITS IN 2-BIT 
SERIAL FASHION 



128, 256, 512, & 1024 BYTE 



SECTOR SIZES 
DATA FIELDS 

SUPPORT READ/WRITE SHORT/LONG 
FEATURES 

ON-CHIP STORAGE OF SYNDROME/CHECK 
BYTES 

8-bit i/o data bus 

software addressable registers & 
i:atches 

on-chip logic for external buffer 

CONTROL 

40 PIN, DUAL-IN-LINE, N-MOS DEVICE 
TTL, MOS COM RATABILITY 
SINGLE SOURCE +5 VDC SUPPLY 



DSB1 I 

HD/FDI 

A0| 

D7I 

D6[ 

D5l 

D4( 

D3[ 

D2| 

D1| 

DP I 

HSC ] 

HBCI 

A2I 

Al l 

CSO l 

CS1 I 

BCS j 

LLBJ 

vssi 



, ^ 40 


2 


39 


3 


38 


4 


37 


5 


36 


6 


35 


7 


34 


8 


33 


9 


32 


10 


31 


11 


30 


12 


29 


13 


28 


14 


27 


15 


26 


16 


25 


17 


24 


18 


23 


19 


22 


20 


21 



vcc 

DSB2 

SDH2 

SDH1 

SDHO 

INTRQ 

MR 

SC128 

CMR 

DRQ 

WAUP 

cInc 

SBEF 
1 WE 
IRE 
I CLK 
I HDC S 
I RCS 
I BCR 
I LUB 



o 

o 
4^ 



PIN DESIGNATION 



DESCRIPTION 

The WD1014 EDS logic chip provides the WD1002-05 
Winchester Floppy Disk Controller (WFC) board with 
ECC and support logic. The EDS chip is a single chip 
device specifically designed to add error correction 
capabilities to a 5.25" and 8" Winchester disk drive. 
It also contains three 8-bit registers, three counters, 
and several latches that enhance the capability of the 
WFC on-board Control Processor (CP) chip WD1015 
for control functions in real time operation. The EDS 
40-pin device replaces approximately 35 standard TTL 
packages consisting of shift registers, flip-flops, and 
logic gates. 

The ECC polynomial selected is the same as the one 
implemented in the WD1 100-06 ECC/CRC logic 



except that the current design is a 2-bit serial 
implementation of the polynomial for faster operation. 
The ECC polynomial selected is a computer 
generated code optimized for sector sizes of 128, 256, 
512, and 1024 byte data fields. The four ECC bytes 
appended by this chip enable corection of a single 
burst of up to 11 bits. It can also simultaneously 
detect a single burst of up to 20 bits and a double 
burst of up to 4 bits. The computer generated code 
has been selected over a comparable fire code since 
the fire codes suffer from pattern sensitivity problem. 

The WD1014 EDS device is fabricated using N- 
channel silicone gate technology, and is available in 
a 40-pin, ceramic, dual-in-line package. 



Winchester Disk Support Devices 



4-15 



PIN DESCRIPTION 



PIN 
NUMBER 


MNEMONIC 


PIN NAME 


FUNCTION 


1 

2 

3 

4 

Thru 

11 

12 

13 

14 
15 

16 
17 

18 

19 

20 
21 

22 
23 

24 

25 

26 
27 

28 
29 


DSB1 

HD/FD 

AO 

D7 

thru 

DO 

HSC 

HBC 

A2 
A1 

CSO 
CS1 

BCS 

LLB 

Vss 
LUB 

BCR 
RCS 


DRIVE SELECT BIT 1 


This output is encoded with DSB2 to select one of 
three Winchester Drives or one of four floppy drives 
depending upon the state of HD/FD. 

When high, hard disk drives are selected and when 
low, floppy disk drives are selected. 

This input along with CSO = 1 and CSI = is 
used to address the WD 1014 registers. 

8-bit bi-directional data bus. Data is output only when 
the check / syndrome register or the command 
register is read. 

This output when low, enables the WFC status onto 
the data lines making them available to the Host pro- 
cessor, if WAUP = 0. 

This output when low, enables the Host to com- 
municate to the WFC and set up all task files, if WAUP 
=: and HSC = 1. 

These 2 inputs along with CSO = 1 and CSI = 
are used to address the WD1014 registers. 

CSO = 1 and CSI = selects the WD1014, for 
other combinations see the chart under task files. 

This input line indicates that an external device wants 
to access the buffer. The ECC check / syndrome com- 
putation is also enabled at this time. 

The rising edge of this output line is used to load the 
lower byte of address into the external buffer counter. 

Ground. 

The rising edge of this output line Is used to load the 
upper byte of address into the external buffer counter. 

This input indicates that an external device wants to 
reset the external buffer counters. The internal 
overflow counters are also cleared. 

This output line is used to select external RAM when 
BCS is active low or when the CP or the Host is 
accessing the RAM. This output is disabled when 
SBEF = 1. 

This output line is used to enable the WD1010 when 
the Host is accessing its task files except the Error, 
Status and Command registers. 

The rising edge of CLK is used to shift the ECC 
polynomial and the falling edge is used to count 
exactly 4 shifts. 

Strobes used in conjunction with CSO = 1, CSI 
= 0, A2-A0 to access registers. 

Output signal used to indicate the sector buffer has 
been filled or emptied. 

The rising edge of this output signal increments an 
external address counter. This output is enabled only 
if the RAM is being accessed and SBEF =0. 


HARD OR FLOPPY 
DISK SELECT 

ADDRESS BIT 

DATA 7 

thru 

DATAO 


HOST STATUS 
CONTROL 


HOST BUS CONTROL 

ADDRESS BIT 2 
ADDRESS BIT 1 

CHIP SELECT BIT 
CHIP SELECT BIT 1 

BUFFER CHIP SELECT 


LOAD LOWER BYTE 

GROUND 

LOAD UPPER BYTE 


BUFFER COUNTER 
RESET 


RAM CHIP SELECT 


HDCS 

CLK 

RE 
WE 

SBEF 


HARD DISK CHIP 
SELECT 

CLOCK 


READ ENABLE 
WRITE ENABLE 

SECTOR BUFFER 
EMPTY OR FULL 


CINC 


COUNTER INCREMENT 



4-16 



Winchester Disk Support Devices 



PIN DESCRIPTION 



PIN 








NUMBER 


MNEMONIC 


PIN NAME 


FUNCTION 


30 


WAUP 


WAKEUP 


This output signal is made active by the Host issu- 
ing a command and filling the sector buffer. It 
indicates that a command is being executed by the 
CP on the WFC board. The Host now cannot com- 
municate with the WFC until the command has been 
completed. MR also sets WAUP. 


31 


DRQ 


DATA REQUEST 


The data request line is activated whenever the sec- 
tor buffer contains data to be read by the Host, or is 
awaiting data to be loaded by the Host. This line is 
reset whenever the sector buffer has been filled or 
emptied. 


32 


CMR 


COUNTER MASTER 


This output signal resets the external address 






RESET 


counters whenever a MR or a command has been 
issued by the Host, or when BCS is asserted. 


33 


SCI 28 


SECTOR COUNT OF 


This input signal is used in conjunction with the SDH 


34 


MR 


128 BYTES 


register to indicate that the buffer has overflowed. 
Used to initialize internal logic. All internal buffer 


MASTER RESET 








overflow counters are reset, the DRQ and INTRQ flip- 








flops are cleared and BUSY is set. 


35 


INTRQ 


INTERRUPT REQUEST 


This output line is activated whenever a command has 
been completed. It is reset to the inactive state when 
the status register is read, or a new command is 
loaded via the DAL lines, or MR is asserted. 


36 


SDH2 


DRIVE SELECT, AND 


The 3 least significant bits of the internal SDH register 


37 


SDH1 


HEAD SELECT BITS 


are available as outputs. The SDH register is updated 


38 


SDSH2 




whenever the Host writes to it. 


39 


DSB2 


DRIVE SELECT BIT 2 


This output is encoded with DSB1 to select one of 
three Winchester Drives or one of four floppy drives 
depending upon the state of HD/FD. 


40 


Vcc 


POWER SUPPLY 


+ 5V Power Source 



TASK FILES 

WAKE UP, CS1, CSO, A2-A0, RE and WE are used to select various registers as shown below: 



WAKE UP 


CS1 


CSO 


A2A0 


EFFECT 


X 

1 
1 
X 


1 
1 
1 





1 




1 




X 
X 
X 
X 
X 


Idle - Nothing selected. 
Host to WFC and WD1010 files. 
CP to WD1010+ RAM access. 
CP to WD1014. 
Illegal condition. 



Winchester Disk Support Devices 



4-17 



o 
o 

4^ 



A2 


A1 


AO 


WD1014 REGISTERS 


WD1010 REGISTERS 


RE 


WE 


RE 


WE 











1 




1 




0+ CHECK/ 
SYN bytes* 

SLEEP 


+ CHECK bytes* 

Set ECC 
+ LLB2 


RAM 

Error Req.** 
Sector Count 


RAM 

Write Precomp 
Sector Count 




1 
1 
1 


1 




1 


1 



1 




Clear OVF/CNTRS 
Clear Mult Mode 


0+LUB2 
Set DRQ 
Set Read Latch 
Set Mult Mode 


Sector Number 
Cylinder Low 
Cylinder High 
S.D.H. 


Sector Number 
Cylinder Low 
Cylinder High 
S.D.H. 


1 


1 


1 


+ Command' 


+ Error Reg.* 


Status Reg.** 


Command Reg.** 



*Data bus contains valid information. Except as 
indicated in ** the Host and onboard CP(WD1015) 
can access the registers in the WD1010. The registers 
in theWD1014can only be accessed by theWD1015. 
For the registers not referred to in *, the data bus 
need not contain valid information. 



**The Host does not access these registers in the 
WD1010 (or WD2797). The content of these registers 
must be off loaded to an intermediate register for 
access by the Host. 













BITS 










COMMAND 


7 


6 


5 


4 




3 


2 


1 





READ 








1 







1 


M 


L 





WRITE 








1 


1 







M 


L 





FORMAT 





1 





1 

















COMMAND CODES 

For the implementation of parts of the controls, the 
following command codes are pertinent: 

The control logic only decodes bits 7-4 and uses bit 
1 (long bit) in its internal logic. The rest of the com- 
mand codes and bits are not used by the WD1014. 

For a complete description of the commands or the 
task files refer to the WD1002-05 WFC data sheet. 

WD1014 ARCHITECTURE 

The WD1014 Chip was specifically designed for the 
WFC board to extend the capabilities of the Control 
Processor (WD1015) to handle real time functions. As 
designed, the WD1014 is not a stand alone general 
purpose device unless, of course, almost all of the 



protocol described can be used in any new designs. 

The WD1014 consists of a 2 bit serial polynomial 
generator (that produces 4 bytes of check/syndrome) 
an 8 bit data buffer and deserializer, two 8 bit 
registers, namely a Command/Error register and a 
SDH register, and control logic consisting of 3 
counters, 6 latches, and a host of combinatorial logic. 
The addressable registers and latches are accessed 
as shown in the block diagram below. 

Each major functional block will be described essen- 
tially independent of one another. Some overlap and 
references to the WFC board are unavoidable and, 
in fact, they aid in presenting a clearer picture of the 
device. 



4-18 



Winchester Disk Support Devices 



bDD 



DATA 
BUFFER 



DESERIALIZER 



POLYNOMIAL 

GENERATOR 

CHECKER 

EVEN 

ODD 



SCHO-2 
DSB1-2 



o 

o 



MR . 

CSO. 

CS1 • 
AC- 
A1 • 
A2 - 

BCS- 

CLK- 

RE - 

WE- 

SCI 28 - 



CONTROL 
LOGIC 



INTERNAL 
REGISTERS 



DECODE 
LOGIC 



-HD/FD 

- HSC 

- HBC 

- LLB 

-LUB 

-HDCS 

-SBEF 

-CINC 

-WAUP 

-DRQ 

-CMR 

-INTRO 



WD1014 BLOCK DIAGRAM 



THE ECC POLYNOMIAL GENERATOR 



The 4 byte check/ syndrome generator consists of 
two 16 bit shift registers each of which has 8 feed- 
back terms Implemented with XOR gates, and con- 
trol gates for the feedback and data paths. 

The leading two bytes of the data field are not 
recognized by the WD1014. Therefore, in order to 
maintain compatibility with the devices that do, the 
polynomial is preset to what would have been 
calculated if the AIF8 had been read.(B517894A) 

ECC computations are made whenever the external 
sector buffer is being accessed. The data present on 
the system data bus is accepted by the input data 
buffer and processed along with the gated data from 
the last stages of the shift register strings. The direc- 
tion of shift within the ECC polynomial is from the 
LS.B. to the M.S.B. After the last byte of data has been 
accessed from the sector buffer, the internal counter 
overflow register is set. This in turn sets a feedback 
inhibit register after the last byte has been processed 
by the ECC polynomial. At this point, the feedback 
terms are forced to zero and only the data path to 
the LS.B. is enabled. This feature is convenient to 
store the 4 check / syndrome bytes internally so that 
RLONG and WLONG commands can be supported 



without the use of an external buffer. 

During a write operation, the Input data stream is 
divided by the polynomial and the 32 bit remainder 
obtained after buffer overflow is used as the 4 check 
bytes. The 4 c heck bytes are gated out of th eWD1 014 
even though RCS = 1 since the internal RBCS is 
still active. In a READ operation, the check bytes are 
recomputed and compared to the recorded check 
bytes to generate the 4 syndrome bytes. The syn- 
drome bytes are stored internally in the shift registers 
until the CP is ready to use them. OthenA/ise, the non- 
zero syndrome is used by the software algorithm to 
compute the displacement and the error vector within 
the bad sector. 

To support RLONG and WLONG (L = 1) features of 
the WD1002-05, shift register strings are used as 
storage elements. After the last byte of data, the Host 
can write or read the 4 additional bytes which serve 
as check bytes for the data transmitted to the buf- 
fer. In this mode the feedback terms and the outputs 
from M.S.B. of the shift registers are disabled so that 
only data is accepted and stored. This enables the 
user to alter the check bits / or data to verify the 
operation of the Error detection logic. 



Winchester Disk Support Devices 



4-19 



SDH REGISTER 

This register can be written into by eitlier the Host 
or WD1015. The bits are decoded as follows. 



-L BIT 



7 


6 5 


4 3 


2 1 


CRC 

+ 
ECC 


SECTOR 
SIZE 


DRIVE 
SELECT 


HEAD/DRIVE 
SELECT 



FUNCTION 



Bit 7 should be set to a 1 whenever a Winchester 
disk is selected "and" ECC is to be utilized. 
It must be set to for floppy disks. 

Bit 6-5 as shown below specify the sector size. 



SDH6 



SDH5 SECTOR SIZE IN BYTES 



1 


1 











1 


1 






128 
256 
512 
1024 



The decoded bits are used in conjunction with a 3 
bit counter which has SC128 as Its clock. The falling 
edge of this input is used to set a counter overflow 
latch for sector sizes 256, 512 and 1024. The rising 
edge of this input sets counter overflow latch when 
the sector size is 128. The counter overflow is 
available on the output as SBEF and is used inter- 
nally to set the buffer overflow latch and various other 
control logic as required by system operation. Thi s 
counter and associated logic is cleared upon MR, 
any new command, or can be directly cleared by 
CLROVF. 

Bits 4-0 are used for drive and head selection and 
are decoded in the following manner. 

Winchester 

HD/FD = 1 = SDH4 -f SDH3 + SDH4SDH3 
DSB1 = 1 = SDH3 decoded off chip for one of three 
DSB2 = 1=SDH4 drives. 

SDH2-0 = SDH2-0 decoded off chip for one of eight 
heads. 

Floppy 

HD/FD =:0 = SDH4SDH3 

DSB1 = 1 =SDH1 decoded off chip for one of four 

DSB2 = 1=SDH2 drives. 

SDH2-0 = Not used. 

Side select is controlled by the WD1015 via 

the WD2797. 

COMMAND/ERROR REGISTER 

This 8 bit register intercepts and holds the command 
issued by the Host. When a command is issued: 

(a) the sector counter and associated overflow lat- 
ches are cleared. 



(b) the external counters are cleared via CMR 

(c) the read command latch is cleared 

(d) INTRQ is reset 

(e) bit 1 (the long bit) is used by the ECC polynomial 
to implement the READLONG and WRITELONG 
command. The CP can also read this latch so that 
it can execute the command. 

(f) WAKEUP is set immediately if the command is 
a RESTORE, SEEK, or READ. For a WRITE or a 
FORMAT command, WAUP is set after counter 
overflow (COVF) occurs or an additional four RAM 
accesses have occured (SYN4), depending upon 
the long bit L = or L = 1. 

At the completion of a command, this register is re- 
used to hold error information that can be read by the 
Host. This is necessary since error information from 
two sources has to be manipulated by the CP and 
reported to the Host in real time when requested to 
do so. 

ERROR DETECTION LOGIC 

The error detection logic consists of an input data buf- 
fer and deserializer, two 16-bit shift registers to 
generate the ECC bytes, and associated control logic 
consisting of two 3-bit counters and integrated logic. 

INPUT DATA BUFFER AND DESERIALIZER 

This section is designed to accept a byte of data on 
the rising edge of RE or WE under the following 
conditions: 

1. The ECC polynomial is selected as implied by 
SDH7 = 1. 



2. A valid RBCS is generated regardless of 
the counter overflow 

3. If the syndrome is to be read by the CP. after an 
overflow condition has occurred (i.e., the syndrome 
is not saved after it has been read by the C.P.). 

Valid data presented to the WD1014 device is 
accepted by the data buffer and the ECC shift 
registers on the rising edge of RE or WE input 
strobes. These strobes are synchronized internally by 
the falling edge of the input clock so that shifting can 
begin on the rising edge of the clock. Data is serialized 
and shifted in a 2-bit parallel mode until the internal 
bit counter reaches the count of 3. This process is 
repeated for every byte of data until the counter 
overflow occurs plus an additional 4 bytes have been 
processed. Under the worst case conditions, a byte 
of data will be processed within 4 clock cycles after 
the RE or WE strobes are terminated. 



4-20 



Winchester Disk Support Devices 



MULTIPLEXER 

The multiplexer is used to channel data to the I/O 
pins D7-D0 when one of the following conditions 
occur. 

1. The command register is read 

2. The error register is read 

3. The check bytes are read 

4. The syndrome bytes are read 

The RE strobe gating with the above control sig- 
nals is designed to keep the hold time on the output 
data bus to less than 100 n.s. and the data access 
time to be no more than 200 n.s. 

WAKEUP 

This signal alerts the external CP that a command 
has been received and is internally referred to as the 
busy signal. 

WAUP will go high when MR is asserted or a 
command other than WRITE or FORMAT has been 
received. In the case of a WRITE or FORMAT com- 
mand WAUP will go high when SBEF = 1 and L = 
0, or when an additional four bytes have been 
accepted by the WD1014 when L = 1. 

For proper operation, the READ command latch must 
be set by the CP whenever that command has been 
received. Also the Multiple Mode latch is set by the 
CP in order to execute the same command a multi- 
ple number of times. This latch must be reset if 
executing a READ or a WRITE command only once, 
or if the last sector of a multiple sector transfer is 
being processed. 

WAKEUP can only be reset by asserting SLEEP. 

DATA REQUEST 

The true condition of the DRQ latch can oly be 
sampled by external circuitry if WAUP = 0. 

This latch can be set by either the CP, or whenever 
a WRITE or FORMAT command is written into the 
WD1014. It is reset by COVF = 1 (SBEF) when L = 

0, or until an additional 4 bytes have been accepted 
by the WD1014 when L = 1. 

INTERRUPT REQUEST 

Two latches are provided to handle interrupts. The 
programmed I/O interrupt (PINT) latch is set whenever 
an interrupt is desired at the start of data transmis- 
sion to the Host. The DMA interrupt (DINT) latch is 
set whenever an interrupt is desired at the end of data 
transmission to the Host. 

Both latches are reset when: 

1. A MR occurs 



2. Any command is received ^ 

D 

3. The output signal HCS is activated. ^ 

As in the case of DRQ, the true condition of INTRO j^ 
can only be sampled by external circuitry if WAUP 
= 0. 

MISCELLANEOUS CONTROL SIGNALS 

The rest of the output signals are purely combinatorial 
in nature and are best described by Boolean expres- 
sions. 



1. HSC = BUSY.CSO.A2.A1.A0.RE 

2. HBC = BUSY.CSO.HSC 

3. lOb = CST.A2.A1.A0. WE 

4. LLB = CST.A2.A1.A0. WE 

5. RCS = COVF(CSO.A2.aT.A0 + BCS) 

6. HDCS = (BUSY.A2.A1.A0. + BUSY..A2.AT.RE 
+ CSO) 

HDCS is active only if the Host is not accessing the 
error, status or the command registers of the WD1010 
device, and CSO is asserted. 

7. CINC = COVF.RSC(WE + RE) 

8. CMR = MR_+ CST where CST = BUSY.CSO 
.A2.A1.A0.WE(Any cmd written) 

9. SBEF = COVF 
ELECTRICAL CHARACTERISTICS 

MAXIMUM RATINGS 

Ambient Temperatures 

under bias 0°C (32°F) to 70°C (158°F) 

Voltage on any pin 

with respect to Vss -0.2V to + 7.0V 

Power dissipation 1.5 Watt 

STORAGE TEMPERATURE 

Plastic -55°C(-67°F) to + 125°C(257°F) 

Ceramic -55°C(-67°F) to + 150°C(302°F) 

NOTE: 

Maximum ratings indicate operation where perma- 
nent device damage may occur. Continuous opera- 
tions at these limits is not intended and should be 
limited to those conditions specified in the DC elec- 
trical characteristics. 



Winchester Disk Support Devices 



4-21 



o 



TABLE 1. DC Electrical Characteristics T^ = 0°C (32°F) to 70°C (158°F), Vqc = +5V ±.25V, Vgs = OV 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


VIL 


Input Low Voltage 


-0.2 




0.8 


V 




VIH 


Input High Voltage 


2.0 






V 




VOL 


Output Low Voltage 






.04 


V 


Iql = 1.6 m A 


VOH 


Output High Voltage 


2.4 






V 


Iqh = -100 mA 


VCC 


Supply Voltage 


4.75 


5.0 


5.25 


V 




ICC 


Supply Current 




200 


250 


mA 


All outputs open 



TIMING PARAMETERS 



A2-A0 



_ -*I»ASK- -^tAHh" 



'CS-^ p- ■* ] r~<CH 

Rl L__J 

C 



-«SP- 



»RW 



'JT 



McsK- 



D7-D0- 



> 



WAUP"1_ 



-*|«IV|*- 



-^ <IS I*' 



INTRO 



-*-|»DV[*- 



DRG 



H'Dpf- 



FIGURE 1. DATA READ CYCLE 



TABLE 2. DATA READ CYCLE TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


fcp 


Input Clock Freq. 




6.0 


5.0 


MHZ 




tAS 


Address Setup to CS 


100 


70 




nS 




tAH 


Address Hold from CS 


50 


20 




nS 




^cs 


Chip Selects Setup to 
RE 


100 


70 




nS 




tcH 


Chip Selects Hold from 
RE 


50 


20 




nS 




tRE 


RE pulsewidth 


150 


120 




nS 




tsP 


RE Strobes period 
(rising edge) 


4 






CP 




^DA 


Data Access after RE 
active 




100 


150 


nS 




^DH 


Data Hold after RE 
inactive 




50 


100 


nS 


reading 


^DS 


Data Setup to RE 
inactive 


50 


10 




nS 




t|V 


Interrupt Request valid 




50 
200 


100 
250 


nS 
nS 


Prog. I/O INT 
DMA INT 


t|S 


INTRO Reset 




100 


200 


nS 




^DV 


Data Request Valid 




50 


100 


nS 




toR 


DRQ Reset 




100 


200 


nS 





4-22 



Winchester Disk Support Devices 



AC ELECTRICAL CHARACTERISTICS 



A2-A0 



_ -*|tAS|*- 
CS 1 



-^UhI^*- 



We 1 I 



-tsp- 



D7-D0- 



-czz 



> 



WAUP"~| 



-Ht,vh- 



tww 



INTRQ 



DRG 






Hh 



-H^DH^- 



< 



-*i tis t*-l 



H^DR^— 



O 

o 



FIGURE 2. DATA WRITE CYCLE 
TABLE 3. DATA WRITE CYCLE TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


fcp 


Input Clock Freq. 




6.0 


5.0 


MHZ 




tAS 


Address Setup to CS 


100 


70 




nS 




tAH 


Address Hold from CS 


50 


20 




nS 




tcs 


Chip Selects Setup to 
WE 


100 


70 




nS 




tcH 

tsp 


Chip Selects Hold from 
WE 

WE pulsewidth 
WE Strobes period 
(rising edge) 


50 

150 
4 


20 
120 




nS 

nS 
CP 




toHW 

tos 


Data Hold after WE 

inactive 

Data Setup to WE 

inactive 



50 


30 
10 




nS 
nS 


writing 


t|V 


Interrupt Request valid 


50 


50 
200 


100 
250 


nS 
nS 


Prog. I/O INT 
DMA INT 


t|S 


INTRQ Reset 




100 


200 


nS 




tpv 


Data Request Valid 




50 


100 


nS 




^DR 


DRQ Reset 




100 


200 


nS 





Winchester Disk Support Devices 



4-23 



a 
o 

4:^ 




FIGURE 3. OUTPUT SIGNALS W.R.T. RE 



TABLE 4. OUTPUT SIGNAL (W.R.T.) RE TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


tci 


RE to Count Increm. 




50 


100 


nS 


rising edges 


^HS 


RE to Status Strobe 




130 


200 


nS 




he 


RE to HSC inactive 




130 


200 


nS 




^HB 


CSO to Host bus str 




70 


200 


nS 


active if HSC off 


^BC 


CSO to HBC inact. 




80 


200 


nS 


active if HSC off 


^BR 


RE to cir SBEF 




250 


300 


nS 


using CLROVF strobe 


tcM 


RE to counter reset 




200 


300 


nS 


using CLROVF strobe 


^WR 


RE to WAUP reset 




100 


200 


nS 


using SLEEP strobe 



4-24 



Winchester Disk Support Devices 



X. 



SDH2-0 



tLF- 



V 



SBEF- 



CMR- 






X 



-tSEH 



JC 



VALID 



t 



tLR 



t 



»CI 



y 



/^ 



C 



*cc 



X 



'sw 

-tww 



o 

o 

4^ 



WAUP- 



FIGURE 4. OUTPUT SIGNALS W.R.T. WE 



TABLE 5. OUTPUT SIGNAL (W.R.T.) WE TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


^SD 


WE Inactive to SDHX 
output 




150 


200 


nS 




tsE 


WE Inactive to DSX 
output 




175 


200 


nS 




tLF 


WE to LLB/LUB 




70 


150 


nS 


falling edges 


tLR 


WE to LLB/LUB 




80 


150 


nS 


rising edges 


tci 


WE to Count Increm. 




50 


100 


nS 


rising edges 


tec 


WE to Counter Reset 




150 


200 


nS 




tsw 


SBEF to WAUP set 




50 


200 


nS 




tww 


WE to WAUP set 




175 


200 


nS 


Command vi/ritten 



Winchester Disk Support Devices 



4-25 



o 

o 
-a 



MR, BCR 



CMR 
SBEF 



SC128 ■ 
SBEF- 



A2-A0, CSO 



— > 



— •■ 


-. — 'MR— 

' 


- 


1*<MC 
j*-«MB 


i-^tws 


J 


>l 


tSR|*- -*»SFh- 




]/ ,' 


\ 




K / 





-^'HDh- H'HR 

HDCS }— >j^ 



-^tRCh- H*RR 

RCS s^ 



'BC-*i h- -H 

Bcs vi y 



y^ 



--•bh 



FIGURE 5. MISCELLANEOUS TIMINGS 



TABLE 6. MISCELLANEOUS TIMING 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


^MR 


Master reset/Buffer 
counter reset width 


100 


50 




nS 




^MC 


MR/BCR to counter reset 




60 


100 


nS 




^MB 


MR/BCR to SBEF rst 




130 


200 


nS 




tws 


MR to WAUP reset 




100 


200 


nS 


BCR has no effect 


^SR 


Rising Edge of SC128 to 
SBEF 




100 


200 


nS 


128 byte sector 


tsF 


Falling Edge of SC128 to 




150 


200 


nS 


all other sectors 


^HD 


SBEF 

CSO to HDCS 




70 


150 


nS 


(or address lines) 


^HR 


CSO to HDCS rising to 




80 


150 


nS 




tfiC 


CMR 

CSO to RCS active 




90 


150 


nS 


(or address lines) 


tpR 


CSO to RCS high 




100 


150 


nS 




tec 


BCS to RCS active 




50 


100 


nS 




^BH 


BCS to RCS high 




60 


100 


nS 





4-26 



Winchester Disk Support Devices 



WESTERN DIGITAL 

CORPORATION 

WD1015 Buffer Manager Control Processor 



o 

.A 

en 



FEATURES 

SINGLE +5V POWER SUPPLY 

COMPLETE BUFFER MANAGER 

PROGRAMMABLE SECTOR SIZES - 128, 256, 

512, or 1024 BYTES 

ECC BURST ERROR CORRECTION UP TO 5 

BITS ON HARD DISK DATA 

8-BIT MULTIPLEXED ADDRESS/DATA I/O BUS 

FLOPPY DISK COMMAND TRANSLATION 

SUPPORTS MOTOR ON OR HEAD LOAD 

DRIVES 

SUPPORTS 250 OR 500 KBS FLOPPIES 

BUFFERED SEEKS WITH FLOPPIES AND 

WINCHESTERS 

16 POPULAR STEPPING RATES AVAILABLE 

AUTOMATIC RETRIES ON ALL ERRORS WITH 

SIMULATED COMPLETION 

POWER-ON DIAGNOSTICS INCLUDED 

10 MHZ CLOCK RATE 

40 PIN DIP PACKAGE 

44 PIN QSM PACKAGE 

DESCRIPTION 



The WD1015 is a complete Control Processor (CP) 
that is used to handle ail aspects of buffer manage- 
ment, in conjunction with the EDS (WD1014) device, 
for the Winchester/Floppy Controller board 
(WD1002-05). It executes all of the commands used 
by the WD1002-05 and does all of the control required 
except for real time processing, which is done by the 
WD1014. Throughout this specification this device will 
be referred to as the WD1015, or BMAC (buffer 
manager and controller), or simply as the CP (con- 
trol processor). The WD1015 is programmed to con- 
trol the transfer of information within the WFC and 
it maintains the necessary copies of the task files 
(TSF) found on both drives. Host access to the WFC 
causes the CP to access task file information in the 
TSF after a command is issued. Depending on the 
command, the CP will make the buffer accessible to 
the host or the WD1010 or 2797 controllers. The CP 
also controls the operation of the Error Correcting 
logic. During the transfer of data from the Host to the 
WD1010, the EDS monitors the data bus, if so 
enabled, to compute a 4 byte ECC which is appended 
to the data transferred to the WD1010 and recorded 
on the disk. During data transfers from the WD1010 
to the host the CP uses the ECC to validate the data. 
If data Is corrupted the CP envokes recovery techni- 
ques such as retries and correction. A maximum of 
8 retries are attempted if two consecutive syndroms 
do not match. Correction is attempted only if two con- 
secutive syndromes match. If the error is uncorrec- 
table, the operation is tenninated. The CP is also used 
to handle data transfers from or to the SF for the 



WAUP 
XTAL1 
XTAL2 
MR 
TST5 
INTFD 

VSS2 
T^ 

T ST9 
WE 
LAD 
DO 
D1 
D2 
D3 
D4 
D5 
D6 
D7 

Vssi 





, ^ 40 




2 


39 




3 


38 




4 


37 




5 


36 




6 


35 




7 


34 




8 


33 




9 


32 




10 


31 




11 


30 




12 


29 




13 


28 




14 


27 




15 


26 




16 


25 




17 


24 




18 


23 




19 


22 




20 


21 



VCC1 

DRQFD 

ERR 

CORRD 

BRDY 

FMO 

DIR 

STEP 

MOM 

TST31 

SBEF 

TRO_0_ 

HD/FD 

INTHD 

VCC2 
TST25 
TST24 
TST23 
TST22 
TST21 



PIN DESIGNATION 



T H I, 

S S T D N V 

T B R / T C 

U P 0° C B i 

nnnnnnnnnnn 



F D T M 
M I E O 
O R P M 





39 


38 37 36 35 


34 


33 


32 


31 


30 


29 




BRDYd 


40 














28 


Z1TST25 


CORRD tZ 


41 














27 


Z1TST24 


ERRC 


42 














26 


Zl TST23 


DRQFD C 


43 














25 


:DTST22 


vccic 


44 














24 


Z] TST21 


NCC 


1 














23 


ZINC 


waupC 


2 














22 


Zlvssi 


XTALlC 


3 














21 


ZID7 


XTAL2CI 


4 














20 


ZID6 


mrCI 


5 














19 


Z]D5 


TST5IZ 


6 














18 


Z1D4 




S. 7 


8 9 10 11 


12 


13 


14 


15 


16 


17 





uuuuuuuuuuu 



V R 
S E 

s 

2 



T W N 
SEC 

9 



D D D 
1 2 



GSM DESIGNATION 



Winchester Disk Support Devices 



4-27 



o 

.J, 

o 
en 



floppy disk controller, which only uses CRC check 
bytes for its data fields. Two commands, RESTORE 
and SEEK, are directly executed by the CP rather than 
the WD2797 floppy disk controller. During status 
reads by the Host, the CP consolidates the normal 
completion status from the WD1010, the 

PIN DESCRIPTION 



WD2797 and the current EDS status into a form con- 
sistant with established WD1010 error reporting. This 
consolidated status is then presented to the Host. The 
WD1015 Is fabricated using HMOS technology and 
is available in a 40 pin DIP package and 44 pin QSM 
package. 



PIN 
NUMBER 


SIGNAL NAME 


MNEMONIC 


FUNCTION 


1 


WAKEUP 


WAUP 


This input is used by the BMAC to poll a command from the Host. 
The BUSY status bit is set immeditately execpt in case of a 
WRITE/FORMAT command. In that case, WAUP and BUSY, are 
set only after the sector buffer has been filled by the Host. WAUP 
is reset when the command has been executed. 


2 


CRYSTAL 1 


XTAL1 


One side of crystal input for internal oscillator. Also input for 
external source. 


3 

4 


CRYSTAL 2 


XTAL2 
MR 


Other side of crystal/external source input. Frequency should 
be 10 MHz. 

This input is used to initialize the internal logic of the processor. 


MASTER RESET 


5 
6 


TESTS 


TST5 


This input is to be left open by the user. Internal pull-up 300K ohm. 
Initiates an interrupt if interrupt is enabled; disabled on reset. 


FLOPPY DISK 


INTFD 


INTERRUPT 


7 


Vss2 


Vss2 


This input is to be left open by the user. Internal pull-up 10M 
ohm 


8 

9 
10 


READ ENABALE 


RE 

TST9 
WE 


Output strobe activated during a BUS read. Can be used to enable 
data onto the BUS from an external device. 

This output is left open by the user. 

Output strobe during a BUS write. Used as write strobe to an 
external device. Signifies that valid data has been put on the BUS. 


TEST 9 


WRITE 


11 


ADDRESS LATCH 


LAD 


This output signal occurs once during each instruction cycle. The 
negative edge of LAD strobes address into an external latch, used 
to communicate to the WD1010, WD2797, and the WD1014 chips. 


12-19 


DATA BUS 


D7-D0 


True I/O bi-directional BUS which can be written to or read syn- 
chronously using RE, WE, strobes. Also contains the address 
and data during an external access to or from port devices, under 
control of LAD, RE, and WE. 


20 


GROUND 


Vssi 


Ground. 


21-25 


TEST 21-25 


TST21-25 


Unused pins to be left open by the user. 


26 


Vcc2 


Vcc2 


-f-5V during operation. 


27 
28 


HARD DISK 
INTERRUPT 


INTHD 
HD/FD 


This input is polled to sense an interrupt from the WD1010, 
indicating completion of command issued to it by the BMAC. 

This input is used to sense hard disk operation when high, and 
floppy disk operation when low. 


HARD DISK/FLOPPY 
DISK 


29 


TRACK 00 


TROO 


This input indicates that the R/W heads of the selected floppy 
drive are positioned over the outermost cylinder. 


30 


SECTOR BUFFER 
EMPTY/FULL 


SBEF 


This input to the BMAC is set high whenever a sector of data 
has been written to or read from the Sector Buffer. 


31 


TEST 31 


TST31 


Normally left open by the user. 



4-28 



Winchester Disk Support Devices 



PIN DESCRIPTION (cont.) 



PIN 
NUMBER 



SIGNAL NAME 



MNEMONIC 



FUNCTION 



O 
O 
cn 



32 



MOTOR MODE 



MOM 



33 



34 



35 



STEP 



DIRECTION 



STEP 



DIR 



FLOPPY MOTOR-ON 



FMO 



36 
37 

38 

39 
40 



BUFFER READY 
CORRECTED DATA 

ERROR 

DATA REQUEST 
Vcci 



BRDY 
CORRD 

ERR 

DRQFD 
Vcci 



Input used to select motor-on or head load timings for floppies. 
This line should be left open for motor-on type drives such as 
the m ini floppies. A delay of 1 second will be obsen/ed before 
FMO is activated. 

For head load type drives like the standard floppies, this input 
shou ld be grounded. A delay of 40 mS, will be observed before 
FMO is activated, thereby improving the overall performance 
when accessing the floppies. 

The STEP output is pulsed once for each cylinder to be stepped 
on the floppies. The step pulse period is normally determined 
by the stepping rate selected. On a RESTORE for the floppies, 
however, a stepping rate of 8 mS, is used if the specified stepp- 
ing rate is faster than 8 mS. 

This output is used by the floppy drive to determine the direc- 
tion of a seek operation. A low defines direction as out and a 
high specifies direction as in. 

This output is used to turn the motor on, on all floppy drives sup- 
ported by the WD1002 WFC board. The drives must be configured 
such that the heads are loaded when this signal is activated. 

When the floppies are being accessed for the first time, a del ay 
as determined by MOM, is observed before activating FMO. 
Motor on is turned off after - 3 seconds, if no further floppy 
accesses are made. 

This output signal indicates the sector buffer is ready to be 
accessed by an external device such as the WD1010. 

This output status indicates to the Host that the BMAC has suc- 
cessfully corrected a data error in the data buffer, at least once. 
To determine if more than one correction has taken place dur- 
ing a multisector read, each sector specified must be reread by 
the Host on an individual basis. 

Output status bit indicates that the BMAC encountered an error 
during the execution of a command.The error reg, on the WFC 
board must be read by the Host to determine the type of error 
that occurred. 

This input indicates to the BMAC that the WD2797 has a byte 
of data available to be read from the disk, or requires a byte of 
data to be written to the floppy disk. 

Main power supply. +5V ±5% 



Winchester Disk Support Devices 



4-29 



4-30 Winchester Disk Support Devices 



WESTERN DIGITAL 

CORPORATION 

WD1100-21 Buffer Manager Support Device 

FEATURES 

6-BIT AUTO-INCREMENTING ADDRESS BUS 

128, 256, 512, OR 1024 BYTES PER SECTOR 

DETECTOR 

SELECTS UP TO 4 DISK DRIVES 

SELECTS UP TO 8 HEADS PER DRIVE 

PROVIDES A RAM CHIP ENABLE AND READY 

SIGNAL 

TTL, MOS COMPATIBLE 

40 PIN DIP PACKAGE 

NMOS TECHNOLOGY 

SINGLE + 5 VDC SUPPLY 

DESCRIPTION 

The WD1 100-21 Buffer Manager Support Device is 
designed to interface up to four disk drives and eight 
heads per drive, to a WD1010-05 and Sector Buffer. 
The WD1 100-21 accepts the SDH Register informa- 
tion (Sector Size, Drive, Head) and selects the 
appropriate drive and head. It receives the data from 
the disk and develops RD and DRUN (Read Data and 
Data Run) suitable for the WD101(M)5. The WD1 100-21 
also selects the Sector Buffer and provides six of the 
address lines. The other four address lines must be 
implemented extemally. The WD1100-21 signals BRDY 
(Buffer Ready) when the buffer counter reaches the 
value stored in the SDH Register. 



DRD1 1 


, ^ .0 


ZDVcc 


UHUa 1 


2 


39 


ZJ A10 


DRD3 1 


3 


38 


— 1 All 


UH04 1 


4 


37 


ZJ A12 


URH 1 


5 


36 


— 1 A13 


DRL ( 


6 


35 


1 A14 


HD2 1 


7 


34 


:zi A15 


HD1 1 


8 


33 


Z3 ROE 


HDOI 


9 


32 


Z3 BCLR 


MR 1 


10 


31 


Z3 D6 


BCS ( 


11 


30 


=3 05 


BCR 1 12 


29 


1 D4 


RD 1 


13 


28 


ZD D3 


RRnv 1 


14 


27 


:^ D2 


DRUN 1 


15 


26 


ZDD1 


rsf 


16 


25 


ZD DO 


WE 1 


17 


24 


1 AO 


RE. 1 Ifl 


23 


ZDA1 


DRTIM ( 


19 


22 


ZIIA2 


vsscz: 


20 


21 


— 1 RDTIM 



o 

o 

o 
I 



PIN DESIGNATION 



Winchester Disk Support Devices 



4-31 



PIN DESCRIPTION 



PIN 
NUMBER 


MNEMONIC 


PIN NAME 


I/O 


FUNCTION 


1 


DRD1 


READ DATA 1 




This signal is data read from disk drive 1. It 
is shaped and placed on output pin 13. 


2 


DRD2 


READ DATA 2 




This signal is data read from disk drive 2. It 
is shaped and placed on output pin 13. 


3 


DRD3 


READ DATA 3 




This signal is data read from disk drive 3. It 
is shaped and placed on output pin 13. 


4 


DRD4 


READ DATA 4 




This signal is data read from disk drive 4. It 
is shaped and placed on output pin 13. 


5 


DRH 


DRIVE SELECT 
HIGH 




Most significant bit of the drive select 
number. Must be encoded externally. 


6 


DRL 


DRIVE SELECT 
LOW 




Least significant bit of drive select number. 
Must be encoded externally. 


7 


HD2 


HEAD SELECT 2 




Bit 2 of the head select number. Must be 
encoded externally. 


8 


HD1 


HEAD SELECT 1 




Bit 1 of the head select number. Must be 
encoded externally. 


9 
10 
11 


HDO 

MR 

BOS 


HEAD SELECT 




Bit of the head select number. Must be 
encoded externally. 

Asserted, it initializes all internal logic 
including the SDH Register. 

Asserted, this signal asserts RCE. 


MASTER RESET 


BUFFER CHIP 
SELECT 


12 


BCR 


BUFFER COUNTER 
RESET 




This signal resets the buffer address counter 
to zero making A10 thru A15 = 0. 


13 


RD 


READ DATA 





This is the MFM data read from the disk, 
shaped and made compatible v/ith the 
WD1010-05. 


14 


BRDY 


BUFFER READY 





This signal is asserted when the buffer 
counter (A10 thru A15) has reached the sec- 
tor size specified in the SDH Register, 128, 
256, 512, or 1024. 


15 
16 

17 

18 


DRUM 
CS 

WE 

RE 


DATA RUN 




1 
1 

1 


This signal is asserted when a field of ones 
or zeroes has been detected. 

Must be asserted to write into the SDH 
Register, increment the Buffer Address 
Counter, and assert RCE. 

Must be asserted to write into the SDH 
Register. WE or RE must be asserted to in- 
crement the Buffer Address Counter. 

RE or WE must be asserted to increment 
the Buffer Address Counter. 


CHIP SELECT 


READ ENABLE 


READ ENABLE 


19 


DRUM 


DRUN TIMING 


1 


An external load used to adjust DRUN to 
nominal pulse width of 250 nsec. 


20 


Vss 


GROUND 


1 


Ground. 


21 


RDTIM 


RD TIMING 


1 


An external load for adjusting the pulse width 
of RD. 1 K ohms creates approx. 90 nsec. 


22 

thru 

24 


A2 

thru 

AO 


ADDRESS 2 
thru 
ADDRESS 


1 


A2 thru AO are used to address the SDH 
Register (A2-A0 = 6) and increment the Buf- 
fer Address Counter (A2-A0 = 0). 



4-32 



Winchester Disk Support Devices 



PIN DESCRIPTION (Continued) 



PIN 
NUMBER 


MNEMONIC 


PIN NAME 


I/O 


FUNCTION 


25 

thru 

31 


DO 
thru 
D6 


DATAO 
thru 
DATA 6 


1 


7-Bit data bus used to write into the SDH 
Register. 


32 
33 


BCLR 
ROE 


BUFFER CLEAR 






Asserted, this signal indicates that the Buf- 
fer Address Counter has been cleared. 

Asserted by BCS, or CS and AO thru A2 equal 
to zero. Used to enable access to the data 
buffer. 


RAM CHIP ENABLE 


34 

thru 

39 


A10 
thru 
A15 


BUFFER ADDRESS 
10 thru 15 





Buffer Address Counter. Used to address the 
Data Buffer. 


40 


Vcc 


POWER SOURCE 




+ 5V Power Supply 






o 

o 

■ 

to 



ARCHITECTURE 

The WD1 100-21 is composed of a 7-Bit SDH Register 
(the extension bit, bit 7 Is not included), 11-Bit Sec- 
tor Buffer Counter, and miscellaneous control signals. 
The content of the SDH Register is used to select the 
drive and head, and limit the Sector Buffer Counter 
to the size decoded by bits 5 and 6. 



Figure 1 is a block diagram Illustrating the relation- 
ship of the timing and control signals with the SDH 
Register and Sector Buffer Counter. 




-► ROE 



(^ 



COUNTER 
CONTROL 




Ci=- 



N^ I 6 5 I 4 3|2 1 



:> 



BUFFER 
COUNTER 



COUNTER := 



BCR 



COUNTER = SECTOR 



SIZE 



BRDY 



A10-A15 



y/ SDH REGISTER 






DR1-DR4 



:> 



ii 







DECODE 
DRIVE 

# 



90 
NSEC 
0.8. 



250 
NSEC 
OS. 



-►RD 



D 

F/F 



-► UN 



.DRTIM 



FIGURE 1. WD1100-21 BLOCK DIAGRAM 



Winchester Disk Support Devices 



4-33 



o 
o 

I 



OPERATIONAL DESCRIPTION 

The Hos t, to write to the SDH Register asserts CS 
and WE, and places an address of zero on AO thru 
A2. 



6 5 


4 3 


2 1 


SIZE 


DRIVE 


HEAD 



SDH bits 2-1-0 make up signals HD2 HD1 and HDO 
and are encoded externally to select one of eight 
heads. SDH bits 4 and 3 make up signals DRH and 
DRL, and they are encoded externally to select one 
of four drives. Bits 4 and 3 are also used internally 
to enable the appropriate input signal DRD1 thru 
DRD4 from the drive reading data. Bits 6 and 5 are 
encoded as follows and asserts BRDY (Buffer Ready) 
when the Sector Buffer Counter reaches the 
designated amount. 



SDH6 


SDH5 


SIZE 








256 





1 


512 


1 





1024 


1 


1 


128 



Sector Buffer Counter is an 11-bit binary counter used 
to address the Sector Buffer and generate the BCLR 
and BRDY signals. Only address bits A10 thru A15 
are supplied by the counter, the o ther five bits must 
be implemented externally. BCR asserted by the 
WD1010-05 resets the counter to zero. The counter 
in turn, asserts BCLR which is used to reset the five 
remaining address bits. The Sector Buffer may be 
written into and Read from by the Host and Disk. 

The Host, to access the Sector Buffer, must place an 
address of zero on AO thru A2, assert CS to select 
the WD1100-21, WE to write, or RE to read. This is 
done for each byte written to, or read fro m the Sec- 
tor Buffer. In turn the WD1 100-21 asserts RCE en- 
abling the Sector Buffer, and increments the Sector 
Buffer Counter by one. when the count specified by 
SDH6 and SDH5 is reached, BRDY is asserted 
indicating the end of the Sector Buffer. 



Reading or writing to the Sector Buffer from the disk 
is done in much the same manner. The difference is, 
that the WD1010-05 supplies the WE and RE in- 
stead of the H ost. The WD1010-05 also replaces the 
CS with BCS. 

The drive selected by DRL and DRH, inputs its Read 
Data on one of the DRD1 thru DRD4 lines. SDH4 and 
SDH3 enables the appropriate signal and passes it 
on to an O.S. to be shaped and widened for use by 
a WD1010-05. The DRUN signal is produced by gating 
the selected DRD signal to an O.S. followed by a D 
flip flop. 

ADJUSTMENTS 

RD pulse width is established by the load placed on 
RDTIM. See Table 2 and Note 1. 

DRUN is controlled by the resistance placed on 
DRTIM. Select DRD1 with the SDH Register. Then 
place a 5 MHz signal on DRD1 while monitoring 
DRUN on pin 15. It should be high. Then a 2.5 MHz 
signal is placed on the DRD1 input. DRUN should be 
low. The resistance chosen should be midway bet- 
ween DRUN just going high at 5 MHz. See Table 2 
and Note 2. 

ELECTRICAL CHARACTERISTICS 

MAXIMUM RATINGS 

Ambient Temperature under bias 0°C {32°F) to 

50°C (122°F). 

Voltage on any pin with respect to Vss -0.2V to 7.0V 

Power dissipation 1.5 Watts 

STORAGE TEMPERATURE 

Plastic -55°C(-67°F) to 125°C (257°F) 

Ceramic -55°C(-67°F) to 150°C (302°F) 

NOTE: 

Maximum limits indicate where permanent device 
damage occurs. Continuous operation at these limits 
is not intended and should be limited to those con- 
ditions specified in the DC Electrical Characteristics. 



TABLE 1. DC OPERATING CHARACTERISTICS 

Ta = 0°C (32°F) to 70°C (158°F), Vqc = 4- 5V ± .25V, Vgs = OV 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


UNIT 


CONDITIONS 


l|L 


Input Leakage 






-10 


A 


Pins 1-4, 25-31 


loL 


Output Leakage 






10 


A 


Pins 1-4, 25-31 


l|P 


Input Pullup 


0.1 




1.6 


mA 


Pins 10-12, 16-18, 22-24 


V,H 


Voltage Input High 


2.0 






V 




V,L 


Voltage Input Low 


-0.2 




0.8 


V 




Vqh 


Voltage Output High 


2.4 






V 


loH = -100/xA 


Vol 


Voltage Output Low 






0.4 


V 


Iql = 1.6mA 


Vcc 


Supply Voltage 


4.75 


5.0 


5.25 


V 




'go 


Supply Current 




200 


250 


mA 


Outputs Open 



4-34 



Winchester Disk Support Devices 



AC TIMING CHARACTERISTICS 



1 


AO.AI 
A2,CS1 


I 


'SET— »J-^ 'MINL — 

1 




X 

H 1^ 

1 








\ 




RE, WE 
BCS 




H 'RCE h< 

1 


)f 


V 






RCE 




v_ 


!/ 










— J^ 'acc I-*- 

I 1 


A10-A15 






! X 


1 










\M-~iDS- 
1 






D0-D6 




X 




X 

— »^ 

1 








I-* — 'dout- 


DR0-DR4 








X 






BRDY 






[< 'bou 


r M 

1 

r 










[^ 'MR— 

1 

—*A tBCLR h* 

1 


— -1 




BCR.MR 

BCLR 
DRD1-DRD4 

RD 
DRUN 




/ 


\ 


-*J 


1 

1 


/ 

'C ^1 

J \ 

►! '3 1-* '4 

1 1 




■♦4* '5-r-* 

A i. 


V 

4-« 14_ 

1 


— »n '6 h* — 
1 , 


^ 1 

^ — 


V 

-'7 


—*\ k 


r^ 








\ 



"Trigger DRUN 
"Retrigger DRUN 



FIGURE 2. AC TIMING 



Winchester Disk Support Devices 



4-35 



TABLE 2. TIMING CHARACTERISTICS 



All units in nsec. 






o 
o 

■ 

lO 



SYMBOL 


CHARACTERISTIC 


MIN 


TYP 


MAX 


CONDITIONS 


♦set 


AO thru A2 and CS setup 











♦minl 


RE, WE, and BCS low 


200 








'MINH 


RE, WE, and BCS high 


100 








♦rce 


RCE delay from BCS or CS 






100 


C = 50 pf 


♦acc 


A10 thru A15 delay from RE or WE 






200 


C = 50 pf 


♦ds 


DO thru 06 setup time 


50 








*DH 


DO thru 06 hold time 


100 








♦dout 


DR1 thru 0R4 delay 






170 


C = 50 pf 


♦bout 


BROY delay 






250 


C = 50 pf 


♦MR 


MR and BCR pulse width 


150 








♦bclr 


BCLR delay from MR or BCR 






200 


C = 50 pf 


♦l 


DRD1 thru DRO 4 width 


25 








♦2 


DR01 thru 0R04 cycle time 




200 






♦3 


RD delay from 0R01 thru 0R04 






200 


C = 50 pf 


♦4 


RO high 


90 


100 


110 


Note 1 


♦5 


RO low 








t2-t4 


♦6 


ORUN delay from 0R01 thru 0R04 






200 


Note 2 


♦7 


ORUN 


225 


250 


275 





NOTE 1. 



vcco-\aaAa_(i3> 

R 



H {- 



VSS 



TYP - R = 10 Kohms, C = 150 pf 

Adjust R to meet characteristics for t4. Typical values 

for t4 and t^ are for 5MHz data rate. 



NOTE 2. 



vcc o-W\A/VJ®K 



^ h 



-o vss 



R 



R = 10 Kohms, C = 150 pf 
Adjust R to meet characteristics for \j. 



4-36 



Winchester Disk Support Devices 



WESTERN DIGITAL 

CORPORATION 

WD11C00-13 ECC Support Device 



o 

o 



FEATURES 

32-BIT COMPUTER SELECTED POLYNOMIAL 

PARALLEL INPUT AND OUTPUT 

DATA TRANSFER RATES UP TO 5 MBITS/SEC 

RECORD LENGTH UP TO 1038 BYTES 
INCLUDING CHECK BYTES 

TTL, MOS COMPATIBLE 

20 PIN DIP PACKAGE 

CMOS TECHNOLOGY 

SINGLE + 5 VDC SUPPLY 



ERR 1 


, ^ 


20 


=3 


vcc 


PREVAL r 


2 


19 


Z3 


LONG 


PRESET 1 


3 


18 


ZD 


D7 


CS 1 


4 


17 


ID 


D5 


RE in 


5 


16 


ZJ 


D3 


WF 1 


6 


15 ID 


D1 


Frn/DATA 1 


7 


14 


ID 


DO 


BUSY 1 


8 


13 


=] 


D2 


Dfi ( 


9 


12 


ZD 


D4 


vss 1= 


10 


11 


=1 


CLK 



PIN DESIGNATION 



DESCRIPTION 

The WD11C00-13 ECC Support Device is designed to 
provide ECC capabilities for Winchester Disk Con- 
trollers and accommodates data transfer rates up to 
5 Mbits/sec. Data is transferred into and out of the 
WD11C00-13 via an 8-bit, bi- directional parallel data 
port. 

The WD11C00-13 performs several operations 
including ECC byte generation, error detection, and 
error syndrome generation. Additionally, the 
WD11C00-13 supports user diagnostics by allowing 
transparent ECC byte transfers between the Host and 
disk medium. 



Winchester Disk Support Devices 



4-37 



PIN DESCRIPTION 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


1 


ERR 


ERROR 





This signal is valid only when the Byte Counter 
reaches the end of the syndrome bytes. Asserted in- 
dicates a non-zero syndrome, or the syndrome has 
not yet been generated. In the Long mode, ERR will 
be de-asserted at the completion of each ECC byte, 
but is of no meaning. 


2 

3 

4 
5 

6 

7 

8 


PREVAL 


PRESET VALUE 


1 

1 

1 
1 

1 

1 




PREVAL asserted presets the ECC accumulator to 
FFFFFFFF, and when de-asserted, presets the 
accumulator to B517894A. It is an asynchronous 
signal and enabled when PRESET Is asserted and 
LONG de-asserted. 


PRESET 

CS 
RE 

WE 

ECC/D 


PRESET 


PRESET asserted and LONG de-asserted enables 
PREVAL . 

CS asserted enables WE or RE . 

When asserted, data is written to or ECC and Syn- 
drome bytes read from the accumulator. 

When asserted, data and ECC bytes are written to 
the accumulator. 


CHIP SELECT 


READ ENABLE 


WRITE ENABLE 


ECC/DATA 


When DATA is asserted, data is written to the 
accumulator and ECC bytes are generated. When 
ECC is asserted, polynomial control logic is inhibited. 
ECC and syndrome bytes are transferred to or from 
the accumulator. 


BUSY 


BUSY 


WD11C00-1 3 asserts BUSY while performing any 
function other than PRESET. 


9 


D6 


DATA BIT 6 


I/O 


This signal is bit 6 of an 8-bit, bi-directional, data bus. 


10 


Vss 


GROUND 




Ground. 


11 


CLK 


CLOCK 


1 


5 MHZ clock used for internal timing (see text for 
additional explanation). 


12 


D4 


DATA BIT 4 


I/O 


This signal is bit 4 of an 8-bit, bi-directional data bus. 


13 


D2 


DATA BIT 2 


I/O 


This signal is bit 2 of an 8-bit, bi-directional data bus. 


14 


DO 


DATA BIT 


I/O 


This signal is bit (LSB) of an 8-bit, bi-directional data 
bus. 


15 


D1 


DATA BIT 1 


I/O 


This signal is bit 1 of an 8-bit, bi-directional data bus. 


16 


D3 


DATA BIT 3 


I/O 


This signal is bit 3 of an 8-bit, bi-directional data bus. 


17 


D5 


DATA BIT 5 


I/O 


This signal is bit 5 of an 8-bit, bi-directional data bus. 


18 
19 


D7 


DATA BIT 7 


I/O 

1 


This signal is bit 7 (MSB) of an 8-bit, bi-directional 
data bus. 


LONG 


LONG 


LONG is asserted when Long Mode is selected. This 
signal inhibits PRESET, as well as ECC and 
Syndrome byte generation. 


20 


Vcc 


POWER SUPPLY 




+ 5V Power Supply 



4-38 



Winchester Disk Support Devices 



ARCHITECTURE 

The WD11C00-13 is composed of an accumulator and 
necessary timing and control logic, to generate four 
ECC or Syndrome bytes. The generation process can 
be inhibited, allowing the WD11C00-13 to appear 
transparent to the four additional bytes that follow 
the end of data written to or read from the disk dur- 
ing READLONG or WRITELONG operations. The 
major blocks of the WD11C00-13 are shown in 
Figure 1. 

Accumulator 

The accumulator consists of a 32-bit serial, ring shift 
register. Access to this register is byte serial via the 
most significant byte. Due to the configuration of the 
register, an 8-bit byte requires only four clocks to shift 
to the next byte position. 

The WD11C00-13 operates as a destructive read out. 
As each ECO or Syndrome byte is read out, it is 
replaced with zeros. Hence, as the last ECC or Syn- 
drome byte is read, the accumulator is reset. 

The content of the WD11C00-13 is altered by any of 
the following events: 

1 . Presettin g to FFFFFFFF or B517894A with the 
PRESET and PREVAL input signals. 

2. Passing data through the device to produce 
four ECC bytes (i.e. writing data to the disk). 

3. Passing data and ECC bytes through the 
device to produce and hold a syndrome (i.e. 
reading data from the disk). 



4 . Writing only the ECC bytes into the device with 
no data (i.e. WRITELONG to, or READLONG 
from the disk, create a transparent effect on 
the ECC character). 

Polynomial Control 

The polynomial X^^ + Y?^ + X^e + X^^ + X^^ -t- X^° 
+ X^ -f X^ + 1 is the same as that used in other 
Western Digital devices. ECC and Syndrome genera- 
tion is initi ated du ring data transfer by asserting 
DATA (ECC/DATA). Polynomial logic is inhibited as 
the ECC a nd Syn drome bytes are read by asserting 
ECC (ECC/DATA). 

Preset Generator 



PRESET and PREVAL are asynchronous inputs which 
do not require CS or Clock asserted. They provide a 
means of presetting the ECC register to FFFFFFFF 
or B517894A. When WE is a sserted before the 
address mark (A 1F8) is read. PRESET and PRE- 
VAL are asserted prior to the device being selected. 
This presets the ECC register to FFFFFFFF. As the 
first data byte is reached, the polynomial control logic 
will have generated ECC bytes B517894A. 

When an application calls for not passing the addre ss 
mark (A 1F8) through the WD11C00-13, PRESET is 
asserted and PREVAL de-asserted before the device 
is selected. This presets the ECC register to 
B517894A, the same configuration that is reached 
when the address mark is read. In this manner, com- 
patibility between drives is maintained. 



O 

o 

o 

o 
A 

CO 




COUNT/CLEAR 
RESET 



FIGURE 1. WD11C00-13 FUNCTIONAL BLOCK DIAGRAM 



Winchester Disk Support Devices 



4-39 



o 
o 

o 
cp 

CO 



Byte Counter 

As the ECC or Syndrome bytes are w ritten in to or read 
out of the accumulator, ECC (ECC/DATA) is assert- 
ed. This initiates the Byte Counter. The counter is 
incremented once for each byte and used internally 
to indicate when all 4 bytes (Sync 4) have been writ- 
ten or read. It is also used to control ERR timing and 
WE. The counter is reset synchronously during da ta 
transfer or asynchronously by asserting PRESET. 

Error Logic 

ERR is de-asserted only when the Byte Counter has 
reached the count of four (SYNC 4) and the Syndrome 
is equal to zero, or the device is in the long mode. 

Internal Timing 

With the exception of PRESET and PREVAL func- 
tions all operations are performed under control of 
the external 5 MHz clock. The internal timing is 
initiated by the following signals: 

CS BUSY RE WE ECC/DATA LONG SYNC 4 

When the device is selected for either a Read or Write 
function in the normal mode, the clocks function 
throughout the entire data transfer. When the 
WD11C00-13 is selected during WRITELONG mode, 
the clocks do not start until the ECC bytes from th e 
Host or disk is reached (indicated by ECC/DATA). 
The clocks stop when the fourth byte has been 
counted. 

When the WD11C00-13 is selected during READLONG 
mode, the clocks do not start until the ECC bytes 
previously loaded are sent to the Host or disk. The 
clocks continue as long as Read functions are 
requested, even if more than four ECC bytes have 
been called for. 

LONG MODE COMMANDS 

When in the Long Mode, PRESET can not be 
asserted, thus protecting the contents of the 
Accumulator from being altered by anything other 
than ECC bytes. 



For diagnostic purposes, it is not desirable to 
generate ECC or Syndrome bytes on the data being 
passed between the Host and disk. Instead, the 
WD11C00-13 allows the ECC bytes to pass through 
unaltered. To accomplish this, READLONG and 
WRITELONG commands are provided. The three 
significant inputs u sed to acc omplish this are 
LONG, WE and ECC/DATA, with LONG being 
the primary control. 

TABLE 1. DC OPERATING CHARACTERISTICS 

Ta = 0°C (32°F) to 70°C (158°F); Vgs = OV, Vqc = +5V ± .25V 



While in the Long Mode with data on the bus, no 
internal clocks can be generated. Therefore, no data 
can be written into the Accumulator or ECC bytes pro- 
duced. The content on the Accumulator remains 
unchanged from its Preset Value. 

When the first o f the E CC bytes is placed on the d ata 
bus, ECC (ECC/DATA) is asserted. With LONG in- 
hibiting the polynomial control logic from function- 
ing, the clocks are initiated and this byte, along with 
the next three, are written into the Accumulator un- 
changed. As stated in the clock description, after the 
fourth byte is written into the WD11 COO-1 3 the clocks 
stop, preventing the destruction of the ECC bytes by 
additional Write functions. 

Reading the ECC bytes from the WD11C00-13 is much 
the same as in WRITELONG, with the following 
exception, as each byte is read out, its location is 
reseUo zero and the clock continues to run as long 
as RE is asserted. 

SUMMARY 

When writing to the WD11C00-13 during Long Mode, 
the polynomial and preset functions are inhibited and 
the clocks cannot run after the fourth byte. This pro- 
tects the ECC bytes, making the device appear 
transparent. 

When reading from the WD11C00-13 during Long 
Mode, ECC generation and preset functions are 
inhibited. The clocks can continue to run after the 
fourth byte, making it possible to supply the Host or 
disk with as many zeros as needed to fill the allot- 
ted space. This decision is controlled by the Host. 

ELECTRICAL CHARACTERISTICS 

MAXIMUM RATING 

Vcc with respect to Vss (ground) + 7V 

Voltage on any pin with respect 

to Vss -0-3 to Vcc + 0-3 volts 

Operating temperature . . 0°C (32°F) to 70°C (185°F) 

Storage 

Temperature. . . .-65°C (-85°F) to 150°C (302°F) 

NOTE: 

Maximum limits indicate where permanent device 
damage occurs. Continuous operation at these limits 
is not intended and should be limited to those con- 
ditions specified in the DC Operating Characteristics. 



SYMBOL 


PARAMETER 


MIN 


TYP 


MAX 


UNIT 


CONDITION 


V|L 


Input Low Voltage 


-0.2 




0.8 


V 




V,H 


Input High Voltage 


2.0 






V 




Vol 


Output Low Voltage 






0.4 


V 


Iql = 1-6 mA 


Vqh 


Output High Voltage 


2.4 






V 


Iqh = -lOOuA 


Vcc 


Supply Voltage 


4.75 


5.0 


5.25 


V 




'cc 


Supply Current 






10 
100 


mA 


In active state 
In rest state 



4-40 



Winchester Disk Support Devices 









^ 1 - 


\- 








REAVE 


^ / 


f N 




'ess 

■^ ► 




'CSH 
/ 




-//////; 


7///////////// 




IMS^I 


i 


















--//////, 


'cs^ 




\ 


■J / / 






'CH 

■^ ► 


1 




ECC/DATA /////// 


V ■ 


V///////////// 




1 


'DS 


'dh 












-' '////// ///h 


(— X///////////// 




'STATC 

■^ ► 






- ////////////////, 


f 










f 




\ t 


BUSY 


•DEPENDENT UPON tcYC 








tBUSY 









o 

o 
o 
I, 

CO 



FIGURE 2. DATA INPUT TIMING 



TABLE 2. DATA INPUT TIMING 



All Units in nsec. 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


TYP 


♦PWL 


REA/VE Pulse Width Low 


124 






'PWH 


RE/WE Pulse Width High 


4T + 235* 






'CSS 


CS Setup to Leading Edge of RE/WE 


10 






♦CSH 


CS Hold After Trailing Edge of RE/WE 









'MS 


Mode Input Setup to Leading Edge of RE/WE 


14 






'MH 


Mode Input Hold After Trailing Edge of RE/WE 


4T +115* 






'CS 


Control Input Setup to Leading Edge of RE/WE 


33 






'CH 


Control Input Hold After Trailing Edge of RE/WE 


37 






♦ds 


Data Input Setup to Trailing Edge of RE/WE 


40 






'DH 


Data Input Hold After Trailing Edge of RE/WE 


20 






'STATC 
'BUSY 
'BUSY 
'CYC 


Accumulator + Q\o High Level After Trailing Edge 
of RE/WE 

BUSY Output to High Level After Trailing Edge 
of RE/WE 

BUSY to Low Level After Trailing Edge 
of REA/VE 
Clock Cycle Period 


180 


40 

4T+165* 

85 





*T = 'CYC 



Winchester Disk Support Devices 



4-41 



■ 




€ 


1. . 






o 














•JL 

o 

o 
o 


WE 


'CSS 

•* — »■ 


V 

'CSH 
/ 


s 


CO 


^/////A : 


'/////////////// 








'MS 




















-V////X ; '■ )(///// 








'OS 

"* — >- 




'CH 

■* »■ 










ECC/DAIA / / / / / J 


/ 


. ' Y/////////////// 






' 


'DS 'DH 














D0-D7 ////////// 


(—)/////////////// 






1 
1 - 










r 








ERR 1 


^ 


I//// 












i^ ,.....Y////////, 

■^ — ► 

•DEPENDENT UPON IcYC 


/ 





FIGURE 3. ECC BYTE INPUT TIMING 



TABLE 3. ECC INPUT TIMING 



All Units in nsec. 



SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


TYP 


'PWL 


RE/WE Pulse Width Low 


124 






•PWH 


RE/WE Pulse Width High 


4T + 235* 






'CSS 


CS Setup to Leading Edge of RE/WE 


10 






'CSH 


CS Hold After Trailing Edge of RE/WE 









*MS 


IVIode Input Setup to Leading Edge of RE/WE 


14 






■ 'MH 


IVIode Input Hold After Trailing Edge of RE/WE 


4T+115* 






'CS 


Control Input Setup to Leading Edge of RE/WE 


33 






'CH 


Control Input Hold After Trailing Edge of RE/WE 


37 






'DS 


Data Input Setup to Trailing Edge of RE/WE 


40 






'DH 


Data Input Hold After Trailing Edge of RE/WE 


20 






'STAT 


Accumulator ?*= to Low Level After Trailing Edge 
of RE/WE 

BUSY Output to High Level After Trailing Edge 
of RE/WE 

BUSY to Low Level After Trailing Edge 
of RE/WE 




4T+165' 

4T+165* 

50 




'BUSY 
'BUSY 


'CYC 


Clock Cycle Period 


180 






*"■" = 'CYC 



4-42 



Winchester Disk Support Devices 



->PWL ► 



^ /////; 



'CSS 



■ "'PWH ■ 



'CSH 

-* »■ 



///////// ///// 



/////////////////////////// 



'cs 



ECC/DATA / / / / / 



'CH 

-* »■ 



•DEPENDENT UPON tcYC 



'DOUT 



OUTPUTS STABLE 



"^2ZZZZZZZZZZZ 

'02 



-■'STAT- 



'ZUL 



•busy 



-■'busy- 



o 

o 

O 
I, 

CO 



FIGURE 4. DEVICE OUTPUT TIMING 





TABLE 4. DEVICE OUTPUT TIMING 


All Units 


in nsec. 


SYMBOL 


CHARACTERISTICS 


MIN 


MAX 


TYP 


'PWL 


RE/WE Pulse Width Low 


124 








'PWH 


RE/WE Pulse Width High 


4T + 235* 








'CSS 


CS Setup to Leading Edge of RE/WE 


10 








'CSH 


CS Hold After Trailing Edge of RE/WE 











'CS 


Control Input Setup to Leading Edge of RE/WE 


33 








'CH 


Control Input Hold After Trailing Edge of RE/WE 


37 








'DOUT 


Data Output Valid After Leading Edge of RE 




50 






'DZ 


Data Bus Float After Trailing Edge of RE 




60 






'STAT 


Accumulator # to Low Level After Trailing Edge 

of RE/WE 

BUSY Output to High Level After Trailing Edge 

of RE/WE 

BUSY to Low Level After Trailing Edge of RE/WE 




4T-f-165* 

4T+165* 
50 






'BUSY 
'BUSY 


'CYC 


Clock Cycle Period 


180 









'CYC 



Winchester Disk Support Devices 



4-43 



o 
o 

o 
o 

CO 



CLOCK INPUT 



y 



\ 



/ 



\ 



-'CYC- 



■* 'PPW- 



/ 



•MPS 

r« ► 



^3 zzzzzzzzzzzzzx 



*MPH 



I 'MPH 

h » 



•ps 

-« »• 



'PH 

«« ^ 



7////////////////y 







^ 


' 


tpD 




•^ ► 


/ 






•STATR 


' 1 











•DEPENDENT UPON 'CYC 



-zzzzzzz 



XZZZZI 

^1 



FIGURE 5. MISCELLANEOUS TIMING 





TABLE 5. MISCELLANEOUS TIMING 


All U 


nits in nsec. 


SYMBOL 


CHARACTERISTICS 


MIN 


MAX 


TYP 


'1 

'2 

'CYC 

'PPW 

'MPS 

'MPH 

'PS 

'PH 

'DP 

'PD 
'STATR 


Clock High Period 

Clock Low Period 

Clock Cycle Period 

PRESET Input Pulse Width Low 


90 
90 
180 
109 
23 


103 

9 

4T + 375' 


91 






Mode Setup to Leading Edge of PRESET 
Mode Hold After Trailing Edge of PRESET 


SSC Input Setup to Trailing Edge of PRESET 

SSC Input Hold After Trailing Edge of PRESET 

Delay from Trailing Edge of RE/WE to Trailing 
Edge of PRESET 


Delay from Trailing Edge of PRESET to Leading 

Edge of RE/WE 

Accumulator # to High Level After Leading Edge 
of PRESET 



•T _ t 



= 'CYC 



4-44 



Winchester Disk Support Devices 



WESTERN DIGITAL 

CORPORATION 

WD11C00-17 
PC/XT Host Interface Ijogic Device 



o 
o 

o 
o 



FEATURES 

8-BIT HOST INTERFACE 

3 MICRON CMOS TECHNOLOGY 

COMBINES RANDOM LOGIC AND SPECIALIZED 
CIRCUITS 

FAST SWITCHING SPEEDS 

LOW POWER DISSIPATION 

STATIC PROTECTION ON ALL l/Os 

PROPAGATION DELAYS OF 1.4 NANOSECONDS 

68 PIN SURFACE MOUNTABLE PACKAGE 

SINGLE +5 VOLT POWER SUPPLY 

HIGH CURRENT BUS DRIVERS 

INTERFACE LOGIC CONTROL FOR PC BUS 



<<<< < 




<<<<<a|^|o,m||<^^a||5|g|Q 

nnnnnnnnnnnnnnnnn 

Q o 7 a ^ A 1 n 1 AH r,7 Kfi Kc; fid KT CO ^i 



o 



68 67 66 65 64 63 62 



;7 28 m 30 31 32 33 34 35 36 37 38 39 40 41 « 43 

uuuuuuuuuuuuuuuuu 

- ''^SOcDCpl^SwOOOO 

Q-ICQ H^^ 



60Z1GND1 

59Z]D7 

58 Z2 AD7 

57Z1D6 

56Z3AD6 

55ZID5 

5" Z3 ADS 

53Z1D4 

52 Z] AD4 

5iZlD3 

50Z1AD3 

49Z1D2 

48 Z\ AD2 

47Z1D1 
46l]AD1 

45Z]D0 

44 1] ADO 



PIN DESIGNATION 



DESCRIPTION 

The WD11C00-17 PC/XT Host Interface Logic Device 
combines the necessary random logic and specialized 
circuitry to interface the Western Digital chip set to 
the IBM PC/XT interface for Winchester Disk control. 
The chip contains integrated: Status Ports, Read/Write 
Ports, Sector Buffer Control, ECC Generation and 
Detection Logic, Reset Timing Logic, and Host Inter- 
face Logic. These features greatly simplify hardware 
requirements for the design engineer when using the 
WD chip set consisting of the: WD1015, WD1010A-05, 
and WD10C20-A. With appropriate decode logic, the 
WD11C0O-17 appears to the Host as four contiguous 
I/O locations XX0-XX3. The 32-bit ECC Generation and 
Detection circuitry allows for realtime ECC check byte 
generation and error checking; ECC correction is via 
the WD1015. The WD11C00-17 also contains all the 
handshaking logic required for polled I/O and DMA 
transfers with the Host. 



HOST INTERFACE 

The WD11C00-17 PC/XT Host Interface Logic Device 
interfaces directly to the Host Data Bus via bi- 
directional high current bus drivers on the D0-D7 pins 
and high current din/ers on the DRQ3 and DRQ5 pins. 

SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature 0°C (32°F) to 

55°C(13rF) 

Voltage on any pin with respect to 
Ground (Vss) -0.5 to 7.0V 

Power Dissipation 1W 

Storage Temperature 

Plastic -55°C (-67°F) to 

+ 125°C(257°F) 

NOTE: Maximum limits indicate where permanent 
device damage occurs. Continuous operation at these 
limits is not intended and should be limited to those 
conditions specified in the AC/DC Electrical 
Characteristics. 



Winchester Disk Support Devices 



4-45 



AC/DC ELECTRICAL CHARACTERISTICS 

Ta = 0°C to 70°C; Vcc = 5.0V ± 10%; Vgs = OV 



SYMBOL 


PARAMETER 


MIN 


TYP 


MAX 


UNIT 


CONDITON 


V,L 


TTL Low Level Input 
Voltage 






0.8 


V 


Pins:1,2,3,4,16,17,18,19,25,32,39,40 
,41,42,43,44,46,48,50,52,54,56,58,61 
,63,64,66,67 


V,H 


TTL High Level Input 
Voltage 


2.4 






V 


Pins: Same as V|l 


Vtl 


Schmitt Threshold Voltage 
Low 


0.9 






V 


Pins:23,24,26,28,29,30,37,38,45,47, 
49,51,53,55,57,59 


Vth 
Vhy 


Schmitt Treshold (High) 
Hysteresis 


0.35 




2.4 


V 
V 


Pins:Same as Vjl 
Pins: Same as Vjl 


loL 


Low Level Output 
Current Single Buffer 

Tri-State, Single Buffer 
Tri-State, Double Buffer 
Open Drain N-Channel 


5.0 

5.0 

10.0 

5.0 






mA 

mA 
mA 
mA 


Vol = 0.4V 

Pins:5,6,7,8,9,1 0,1 1 ,1 2,1 3,14,1 5,20, 

22,31,35,62,65,68 

Pins:44,46,48,50,52,54,56,58 

Pins:1 ,3,33,34,45,47,49,51 ,53,55 

Pins:36,37 


'oh 


High Level Output 
Current Single Buffer 
Tri-State, Single Buffer 
Tri-State, Double Buffer 


-5.0 

-5.0 

-10.0 






mA 
mA 
mA 


VoH = 2.4V 
Pins: Same as Iql 
Pins: Same as Iql 
Pins: Same as Iql 


'dd 


Supply Current 






15 


mA 


Pins: Same as Iql 


ll 


Input Leakage 


-10.0 




10 


uA 


Vin = or 5.5V 


h 


Tri-State Leakage 


-10.0 




10 


uA 


Vo = or 5.5V 



PIN DESCRIPTIONS 

Pin descriptions are listed in Table 1. 



TABLE 1. PIN DESCRIPTIONS 



PIN 
NUMBER 


NAME 


SYMBOL 


FUNCTION 


1 
2 
3 
4 

5-15 

16 

17 
18 
19 

20 


Read Enable 


RE 
BCS 
WE 
TEST 

RA10 
RAO 
CLCT 


Input when BCS is low. Read strobe is bi-directional for Sector 
Buffer Address. Output when BCS is high, follows RD Pin 61. 

Controls direction of bi-directional RE, WE lines. Enables 
RAMCS for WD1010 access. 

Input when BCS is low. Write strobe is bi-directional for Sector 
Buffer Address. Output when BCS is high, follows WR Pin 64. 

Input active high, used for test only, controls state of internal 

RA10 (end of data) during ECC test. 

TEST = LOW DATA 

TEST=HIGH END OF DATA 

Outputs active high, address Sector Buffer RAM and WD1010. 

Input active high clears lower RAM address counter outputs RA 

-RA7. 

Input active low enables the ECC function. 

Input 5 MHz clock for the ECC function. 

Input when high selects normal mode of the ECC function (i.e., 

check bytes are generated after end of data). 

When low selects long mcxie and inhibits preset function of ECC 

logic (i.e., check bytes are not generated after end of data and 

logic passes check bytes transparently from Host to disk). 

Output active high indicates to WD1015 that an error has been 

detected while comparing check bytes at end of data stream 

with check bytes generated internally. 


Buffer Chip Select 


Write Enable 
Test 


RAM Address 
Clear Count 


Chip Select ECC 
Write Clock 
Mode 

ECC Not Zero 


CSECC 

WCLK 

MODE 

ECC 
NOTO 



4-46 



Winchester Disk Support Devices 



TABLE 1. PIN DESCRIPTIONS (Continued) 



PIN 
NUMBER 


NAME 


SYMBOL 


FUNCTION 


21 


+ 5 VDC 


VCC 


Input supply voltage. 


22 


Read Port 322 


RD322 


Output active low when Host reads status Port 322. 


23 


DMA Acknowledge 
3 


DACK3 


Input active low acknowledges DMA request 3 (DRQ3). 


24 


I/O Read 


lOR 


Input active low enables data onto D0-D7 outputs when Host 


25 






wants to read data or status. 

Input active low when address 320 thru 323 is present on the 


Device Address 


DADD 




Code 




Host Address Bus. 


26 


Address Enable 


AEN 


Input active high indicates that DMA Controller (Host) has con- 
trol over the address, control, and data buses. 
Used to enable Host to disk I/O functions. 


27 


Ground 


GND 


Ground. 


28 


Address Bit 1 


A1 


Input active when Host asserts A1 to high state. Used to enable 
Host to disk I/O functions. 


29 


Address Bit 


AO 


Input active high when Host asserts AO to high state. Used to 


30 




low 


enable Host to disk I/O functions. 

Input active low strobes data from the Data Bus into internal 


I/O Write 








devices or into the Sector Buffer RAM when Host performs a 


31 






write function. 

Output active low when either Host, WD1010 or WD1015 wants 


RAM Write 


RAMWR 


32 




C/D 


to write to Sector Buffer RAM. 

Input when low indicates that Controller expects either a com- 


Control/ Data 








mand or status block transfer. When high, indicates that Con- 








troller expects a data block transfer. Used to enable a data block 








transfer. Used to enable disk I/O control section. 


33 


DMA Request 3 


DRQ3 


Output active high requests DMA service from the Host. 
Remains high until DACK 3- goes low. Asserted when the Con- 
troller is ready to accept data or data is ready to be read. 


34 


Interrupt Request 


IRQ5 


Output active high signals to Host that service is required. 




5 




Remains high until Host interrupt service routine resets it. 


35 


Busy 




Activated when the Controller has completed disk operation. 
Output active low indicates Host has selected controller and 


BUSY 


36 




MR 


is about to perform an I/O operation. 

Bi-directional input active low when external Power UP Reset 


Master Reset 








detects dropping VCO level. Clears all internal registers. Out- 








put active low when Host either performs a soft reset, or hand- 








shake reset from the bus is detected via the RESET Pin 38. 


37 


Reset Time 


RSTIME 


Input threshold adjust for the duration of the MR Pin 36 ac- 
tive low time during soft Reset. 


38 


Reset 


RESET 


input active high when Host performs a bus reset. Clears all 
internal registers and active MR Pin 36 to active low. 


39-42 


Option 0,1,2,3 


OPO 


Inputs normally high via internal pull up resistors. Can be 






1,2,3 


activated low by applying GND to the input. Disk configuration 
readable on Data Bus by Host via status read to Port 322. 


43 




I/O 


OPO - DO, 0P1 - D1, 0P2 - D2, 0P3 - D3. 

Input controls direction on Internal Data Bus Buffer form Host's 


Input/Output 








point of view. High = input to Host. The ADX Bus is driven onto 








the DX Bus. Low = output from Host. DX Bus is received and 








driven to the ADX Bus. 



Winchester Disk Support Devices 



4-47 



TABLE 1. PIN DESCRIPTIONS (Continued) 



O 

_^ 
—A 

o 

o 
o 



PIN 
NUMBER 


NAME 


SYMBOL 


FUNCTION 


44,46 
48,50 
52,54 
56,58 

45 

47 

49 

51 

53 

55 

57 

59 

60 

61 

62 

63 

64 
65 

66 
67 

68 


Address/Data Bus 


AD0-AD7 

DO 

Dl 

D2 

D3 

D4 

D5 

D6 

D7 

GND 

RD 

CS1010 

ALE 

WR 
REQ 

IREQ 
LS 


Bi-directional Bus carries address information to Internal RAM 

Address Counter and control de-multiplexer. Carries data to and 

from the internal ECC function and the external Sector Buffer 

RAM. 

Bi-directional Bus interfaces Controller to Host Data Bus.(DO 

through D7). 

Ground. 

Input active low when WD1015 performs a read operation. 
Output active low when WD1015 performs a read or write opera- 
tion to the WD1010. 

Input active high when WD1015 asserts ALE. Used internally 
to select and latch the control demultiplexer. 
Input active low when WD1015 performs a write operation. 
Output active high indicates to the Host that Controller is ready 
to accept data from or transfer data to the Host. Handshake 
signal for transfers between Host and Controller. The state of 
this output is read on DO by the Host via a status read to 
Port 321. 

Input when asserted enables REQ. When low, it indicates to the 
Host that the operation is complete. 
Input signal is high during a Host Controller transfer. The Con- 
troller is in the long mode (Data Transfer) when high. When this 
signal is low during Host Controller transfer, the Controller is 
in the short mode (Command Transfer). 
Output active low enables the external Sector Buffer RAM for 
read/write operations bv the Host. WD1015 or WD1010. 


Data Bus 
Data Bus 1 
Data Bus 2 
Data Bus 3 
Data Bus 4 
Data Bus 5 
Data Bus 6 
Data Bus 7 
Ground 
Read 
Chip Select 1010 

Address Latch 
Enable 
Write 
Request 

Interrupt Request 
Long/Short 


RAM Chip Select 


RAMCS 



FUNCTIONAL DESCRIPTION 

The WD11C00-17 PC/XT Host Interface Logic Device 
combines random logic and specialized circuits into 
one device. The internal architecture of the 
WD11C00-17 is shown in block diagram format and 
illustrated in Figure 1. 



4-48 



Winchester Disk Support Devices 



INT/DMA 
CONTROL 



n 



BUFFER 



I 



DRQ/IRQ 



O 

o 

o 

2 



D0-D7 



T 



BUS CONTROL 



DECODE 

AND 
CONTROL 



BUFFER 



T 



STATUS 
PORT 



n 



CONTR. 
STATUS/ 

DISK 
CONFIG. 



AD0-AD7 



RAM 

ADDR. 

COUNTER 



T 



CONTROL 



RAM ACCESS 




ECCOO 



FIGURE 1. WD11C00-17 PC/XT HOST INTERFACE LOGIC DEVICE BLOCK DIAGRAM 



Winchester Disk Support Devices 



4-49 



o 
o 

o 
o 



STATUS PORTS 

All port address decoding is done internally in the 
WD11C 00-17. This is done via the AO and A1, and 
DADD inputs. The board's hardware status register 
and INT/DRQ latches are contained within the 
WD11C00-17. The board's hardware status is available 
to the Host via a read to Port 321, This is a read only 
function. The bits are defined as follows: 

Bit 7 - Unused 

Bit 6 - Unused 

Bit 5 - Interrupt Request (IRQ) 

Bit 4 - Data Request (DRQ) 

Bit 3 - Busy (BUSY) 

Bit 2 - Command/Data (C/D) 

Bit 1 - Input/Output (I/O) 

Bit - Request (REQ) 

The four lower order bits (0P0-0P3) of the drive con- 
figuration information are readable on the Data Bus 
by the Host via read operation to Port 322. This is a 



read function only. 0P0-0P3 are input signals to the 
WD11C00-17, and are normally high due to internal 
pull-up resistors. OP0-OP3 are written directly to the 
Data Bus via D0-D3 outputs from the WD11C00-17. 

RD322 output is generated by the WD11C00-17 so that 
external 74LS244 can be used to read the four high 
order bits (OP4-OP7) of the drive configuration infor- 
mation. These bits are pulled up by external 4.7K pull- 
up resistors. 

Port 323 contains two bits which enable or disable 
the interrupt and DMA request lines to the Host. This 
is a write function only. The bits are defined as 
follows: 

Bits 7-2 - Unused 

Bit 1 - Interrupt Request Enable 

Bit - DMA Request Enable 

READ/WRITE PORTS 

All port address decoding is done internally in the 
WD11C 00-17. This is done via the AO and A1, and 
DADD inputs. A complete port summary is defined 
in Table 2. 



TABLE 2. READ/WRITE PORTS 



ADDRESS 


READ FUNCTION 


WRITE FUNCTION 


320/324 
321/325 
322/326 
323/327 


Read Data, Board to Host 
Read Board Hardware Status 
Read Drive Configuration Information 
Not Used 


Write Data, Host to Board 
Board Software Reset 
Board Select 
Set/Reset DMA, IRQ Masks 



All reads and writes to Port 320 result in data being 
transferred from the Sector Buffer and the Sector Buf- 
fer Counter being incremented. 

Write to Port 321 results in a software reset. This has 
the same effect as a hardware reset. 



Write to Port 322 results in a board selection, 
must be done prior to each command. 

SECTOR BUFFER CONTROL 



This 



The WD11C00-17 contains all the necessary Sector 
Buffer address counters and generates Sector Buf- 
fer chip select and Sector Buffer read/write signals. 

The RAO through RA9 outputs are used to control the 
Sector Buffer. A 2K by 8 RAM is used but only IK 
of it is necessary so only the lower IK is used. This 
IK is divided into four 256 byte pages. 

The RA8-RA10 outputs are rsetable by the WD1015. 
This allows the WD1010 to access the WD1010 tasks 
files. 

The RA10 putput is used to de-assert DRQ3, inform- 



ing the Host that the Sector Buffer is either empty 
or full, and signals the end of the data field or the 
start of the ECC field to the ECC logic in the 
WD11C00-17. 

The lower two pages of the Sector Buffer are used 
to store the 512 bytes of sector data. The lower page 
is also used to store command information prior to 
passing it along to the WD1015 and, to store ECC 
bytes. 



The RAMCS and RAMWR outputs are used to select 
the Sector Buffer and ReadA/Vrite to the RAM. 



The WD1015 outputs the CLCT signal to the 
WD11C0O-17. This results in the Address Counter out- 
puts RA0-RA7 to be cleared. 

DISK, HOST, AND WD1015 I/O CONTROL 

The WD11C00-17 is used in conjunction with the 
WD1015 and the Sector Buffer in controlling the 
WD1010 and performing Host transfers. 

Commands are transferred by the Host into the first 
256 byte page within the Sector Buffer. The WD1015 



4-50 



Winchester Disk Support Devices 



then reads these commands and loads the WDIOIO's 
task file registers with the approplate Information. 

The WD1010's task file registers are selected via the 
RA8-RA10 outputs together with the CS1010-output. 

The WD11C00-17 Inputs BCS, RE, and WE, are as- 
serted by the WD1010 when it wants to read the Sec- 
tor Buffer. A read or write by the WD1015 to the 
Wpi010's task file registers results In the RE or 
WE outputs to be asserted. The RE an d WE line 
are bi-directional and are inputs when BCS is low. 

The WD11C00-17 Inputs RD and WR are used by 
the WD1015 when It wants to read or write either the 
Sector Buffer or the WD1010. 

The Host Data Bus (D0-D7) interfaces directly to the 
WD11C00-17and is driven via bi-directional high cur- 
rent bus drivers to the chip. 

The bus signals DRQ3 and IRQ5 are driven by inter- 
nal high current drivers. 



The AO, A1, DACK3, lOR, lOW and RESET inputs 
to the WD11C00-17 all feature Schmitt trigger inputs 
to ensure noise immunity. 



The WD1015 outputs the CLCT signal to the 
WD11C0O-17. This results In the Address Counter out- 
puts RA0-RA7 to be cleared. 



The DADD Input to the WD11C00-17 Is generated 
by the external address decode logic. The 
WD11C00-17 will decode which of the four ports is 
being selected, but the external circuitry must decode 
the proper port address range of 320 through 323. 

The AEN input to the WD11C00-17 is asserted when 
the DMA controller has control over the bus. AEN's 
assertion de-gates the Host Processor and other 
devices from the I/O channel. 



The BUSY, CD, and I/O inputs to the WD11C00-17 
are all generated by the WD1015 and passed to the 
WD11C00-17 so that they may be read In the board's 
hardware status register. 

ECC GENERATION AND DETECTION 

The WD11C00-17 generates and appends the four byte 
ECC to the data stream. Proper placement of the ECC 
requires determination of the end of the data stream. 
Assertion of RA10 by the WD11C00-17 Address 
Counter indicates RAM overflow and the end of the 
data stream. After writing the four ECC bytes to the 
disk, the WD11C00-17 ECC circuitry supplies all zero 
bytes to the ADO through AD7 Bus as long as the ECC 
function is selected. 

During a read operation, the ECC circuitry recomputes 
the ECC. Comparison of the previously written ECC 
and computed ECC occurs at the end of the data 



stream. The ECC circuitry records the results of the 
comparison. Any additional writes to the Sector Buf- 
fer are ignored. If the results of the comparison is non- 
zero, then the WD11C00-17 asserts a ECC NOT 
signal. Assertion of ECC NOT enables the disk con- 
troller to attempt error correction. 

During Writelong and Readlong commands, the ECC 
generations and checking Is disabled. A Writelong 
command caused the WD11C00-17 to accept any four 
bytes from the Host, and stores them internally. These 
bytes are written to the disk unaltered. 

A Readlong command causes the WD11C00-17 to 
accept the four bytes written on the disk. These bytes 
are passed to the Host unaltered. This allows the Host 
to induce errors anywhere in the data stream and 
check for predictable results. 

The ECC circuitry requires a 5 MHz Input clock. 

The polynomial Y?'^ + Y?^ + X^ + )0^ + X^^ + )C^ 
+ X^ -f X^ + 1 is the same as that used in other 
Western Digital devices. 

RESET TIMING 

When asserted, RST places the board In its intitial 
power-up condition, setting the Internal parameters 
and initializing on- board circuitry properly. The 
WD11C00-17 has an internal one-shot that handles 
the reset pulse width. The input RSTIME controls the 
duration of the active low reset pulse that originates 
from the MR- output. 

The RESET input Is hard wired to the bus Interface 
reset input. A reset on this pin clears all Internal 
registers and forces the MR output low. 

The MR pin is bi-directional and acts as an input 
when the exterani VCC detect circuit forces the board 
into a reset conditon. When this occurs, the internal 
registers are reset. 

Figure 2 illustrates the WD11C00-17 PC/XT Host Inter- 
face Logic Device incorporated into the WD1002S- 
WX2 Winchester Disk Controller Board's architecture. 



O 

.A 

o 

o 
o 



Winchester Disk Support Devices 



4-51 






Figure 2 illustrates the WD11C0O-17 PC/XT Host Inter- 
face Logic Device incorporated into the WD1002S- 
WX2 Winchester Disk Controller Board's architecture. 



O 

o 
o 







KaJ 











DEVICE 
DECODER 



n 



^ 



-^ 



CONFIGURATION 



V^ 



:> 



v^ 



© 



lb 







t — ►© 



3 



c^ 



■AD7 N 



IS 







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kAJ 



FIGURE 2. WD1002S-WX2 WINCHESTER DISK CONTROLLER ARCHITECTURE 



4-52 



Winchester Disk Support Devices 



WESTERN DIGITAL 

CORPORATION 

WD33C93 
SCSI-Bus Interface Controller 



o 

CO 
Cd 

O 

(O 
CO 



FEATURES 

• IMPLEMENTS FULL SCSI BUS FEATURES: 
ARBITRATION, DISCONNECT, RECONNECT, 
PARITY, AND SYNCHRONOUS DATA 
TRANSFERS 

• COMPATIBLE WITH MOST MICROPROCESSORS 
THROUGH AN 8-BIT DATA BUS; SUPPORTS 
BOTH MULTIPLEXED AND NON-MULTIPLEXED 
ADDRESS/DATA BUS SYSTEMS 

• CAN BE USED AS HOST ADAPTER OR 
PERIPHERAL ADAPTER 

• PROGRAMMED I/O OR DMA TRANSFERS 

• INCLUDES 48-MA DRIVERS FOR DIRECT 
CONNECTION TO THE SCSI BUS 

• INTERNAL 24-BIT TRANSFER COUNTER 

• PROGRAMMABLE TIMEOUTS FOR SELECTION 
AND RESELECTION 

• "COMBINATION" COMMANDS GREATLY 
REDUCE INTERRUPT-HANDLING RESPON- 
SIBILITIES 

• SPECIAL "TRANSLATE ADDRESS" COMMAND 
PERFORMS THE LOGICAL-TO-PHYSICAL 
ADDRESS TRANSLATION 

• SINGLE +5V SUPPLY 

• AVAILABLE IN 44-PIN CHIP CARRIER OR 40-PIN 
DIP 

• LOW POWER CMOS DESIGN 



DESCRIPTION 

The WD33C93 is a MOSA/LSI device which is 
implemented in the WD CMOS-3, 3-micron gate pro- 
cess. It operates from a single 5 volt supply and is 
available in either a 44-pin chip carrier or a 40-pin dual- 
in-line package. All Inputs and outputs are TTL- 
compatible. 

The WD33C93 is intended for use in Host or peripheral 
systems which interface to the SCSI (Small Computer 
Standard Interface) Bus. When used in the Host 
system, the WD33C93 interfaces both to the Host bus 
(8086/8088 type) and to the SCSI Bus. It waits for the 
Host to give it a command to select the desired unit. 
The WD33C93 then arbitrates for the SCSI Bus and 
selects the peripheral unit. If It fails to get the bus 
because of a higher priority Host, It continues trying, 
notifying the Host when It has succeeded by 
generating an interrupt. When the peripheral requests 
a command byte from the Host, the WD33C93 
receives the request and generates an interrupt to the 
Host. The Host responds to the interrupt by giving 
a "Transfer Info" command and a peripheral com- 
mand byte to the WD33C93. The WD33C93 sends the 
command byte to the peripheral, and the process con- 
tinues until all command, data, and status bytes have 
been transferred. 

When the WD33C93 is used in a peripheral system, 
it can communicate to the local processor and the 
SCSI Bus just as it does when used as a Host 
adapter. The WD33C93 has the additional capability 
of interfacing with the WD Bus. This means that in 
the data transfer phase, rather than interfacing to an 
external DMA controller, it can issue read and write 
enables in order to access the Sector Buffer. 

The WD33C93 implements the full SCSI physical path 
definition for use with the single-ended interfacing 
option. Arbitration, parity, and synchronous transfers 
will be implemented along with the standard SCSI 
physical path signaling. 



SCSI-Bus Interface Controller 



5-1 



o 

o> 
O 

(O 
CO 



SCSI 
BUS 



INTERNAL 
DATA BUS 











SCSI 

ARBITRATIGN 

PLA 














SCSI 

PARITY 

GEN/CHECKER 














SCSI REQ/ACK 

HANDSHAKE 

LOGIC 














DATA BUFFER 





















REGISTER 

FILE 

AND STACK 



ADDR 
CNTR 



PROCESSOR 
INTERFACE & 
DATA BUFFERS 



32 X 8 
ALU 



BYTE COUNTER 



ROM 



PROGRAM CNTR 



■ AO/ALE 



CS- 

RE_ 
WE 
D7 
I 
DO 



■*- PRO 
-^ DACK 



WD33C93 BLOCK DIAGRAM 



V R A A G D D 
CECTMNBB 
CQKNRD76 



D D 
B 8 
5 4 



(SI)IZ ' 

l/OC 2 

MSGlZ 3 
GNDC ■• 
C/DIZ 5 
BSYtZ 6 
SELC ' 
CLKC 8 
JBRQEZ s 
DACKLZ '° 
(SO)[I 11 



nnnnnnnnnnn 



44 43 42 41 40 39 38 37 36 35 34 



Z] DB3 
Z2 DB2 
Zl GND 
Z] DB1 
Z2 DBO 
Zl DBP 
Zl ALE 
Z]RE 
ZlWE 

Zics 

Z]GND 



uuuuuuuuuuu 

I DDDDDDDDA( 
N01 2345670S 
T C 

R L 

Q K 



44 PIN CHIP CARRIER 



Note: Pins in parentheses are for test purposes only, 
and should be left unconnected for normal cfiip 
operation. 



i/o[Z 1 

MSGlZ 2 

gndIZ 3 
c/dIZ * 
bsyCZ 5 

SELiZ 5 
CLK[Z ' 

drq C 8 

DACK[Z 9 
INTRQ[Z ™ 
DO[Z 11 
D1 IZ 12 
D2[Zi3 
DSC 14 

D5[Z 16 

Dec " 

D7[Z 18 

A0[Zi9 

GNDIZ2" 



V/" 



40 PIN DIP 



40 ^ VCC 
39Z1REQ 
38 Z]ACK 
37 Z] ATN 
36 Z]MR 
35 Z] GND 
34 ZJDB7 
33 UDB6 
32 Z] DBS 
31 Zl DB4 
30 Z1DB3 
29 Z1DB2 
28 ZlGND 
27 Zl DB1 
26 Z] DBO 
25Z]i3BP 
24 ZJALE 
23 ZJRE 

22 Z]WE 

21 Zlcs 



5-2 



SCSI-Bus Interface Controller 



WESTERN DIGITAL 

CORPORATION 

WD1002-05 Winchester/Floppy Controller 



FEATURES 

CONTROL FOR UP TO 3 WINCHESTER AND 
4 FLOPPY DRIVES. 

ON BOARD DATA SEPARATOR AND WRITE 
PRECOMPENSATION 

128, 256, 512, AND 1024 BYTE SECTOR SIZES. 

PROGRAMMABLE SECTOR SIZES TO IK. 

AUTOMATIC TRACK FORMATTING ON HARD 
AND FLOPPY DISKS. 

MULTIPLE SECTOR OPERATIONS. 

5-BIT SINGLE BURST ERROR CORRECTION ON 
WINCHESTER. 

5-MBIT DATA TRANSFER RATE. 

ECC DIAGNOSTIC COMMANDS (READ LONG & 
WRITE LONG). 

SINGLE + 5V POWER SUPPLY. 

DESCRIPTION 

The WD1002-05 Winchester-Floppy Controller (WFC) 
is a stand-alone general purpose board designed to 
interface up to three 5 1/4" Winchester hard disks and 
up to four 5 1/4" floppy disk drives. The WFC 
implements all the logic required for a variable length 
sector (to 1 K bytes), ECC correction, data separation 
and Host interface circuitry. The Winchester interface 
is based on the Seagate ST506 and the floppy inter- 
face on the Shugart SA450. All necessary buffers and 
drivers/receivers are on board. 

Communication to and from the Host is made via a 
separate computer access port. This port consists 
mainly of an 8-bit bi-directional bus and appropriate 
control signals. All data to be written to or read from 
the disk, status information, and macrocommands are 
transferred via this 8-bit bus. An on-board Sector Buf- 
fer allows data transfers to the Host computer at a 
rate independent of the drive transfer rate. 

The WD1 002-05 Controller board is based on the 
WD1014 EDS device and WD1015 Buffer Controller 
device, as well as the WD2797 Floppy Disk Controller 
and WD1010 Winchester Disk Controller chips. It is 
form factor compatible with most 5 1/4" Winchesters 
and may be directly mounted on the drive. 



ARCHITECTURE 

The Block Diagram of the WD1002-05 is shown in 
Figure 1. The heart of the system is the WD1015 Buf- 
fer/Controller, which generates and processes all data 
and control lines, along with the WD1014 EDS that 
generates all control signals that cannot be handled 
in real time by the WD1015. 

Commands, parameters, and data are entered via the 
Host Interface Logic. The WD1015 accepts both 
floppy and Winchester commands in identical forniat, 
converting these parameters to the WD1797/WD1010 
protocol. Data is read from the selected drive and 
transferred to the Sector Buffer. If an error in the data 
field has been encountered, the WD1015 instructs the 
controllers to perform retries automatically. On a Win- 
chester drive, the WD1014 ECC device is enabled and 
error correction procedures invoked. Error Correction 
may be disabled via software from the Host to allow 
"CRC-oniy" formatted Winchester drives to be used 
in the system. Data Separation and Write Precompen- 
sation Logic is onboard for Winchester transfers, 
while the WD2797 Floppy Controller provides an 
integrated Data Separator and adjustable write 
precomp. After the Sector Buffer is full, the WD1015 
informs the Host Interface Logic that data may be 
read by the Host. The use of an on-board Sector Buf- 
fer provides both transparent error correction and data 
transfers to the Host that are independent of drive 
transfer rates. 



o 

o 
ro 

o 

en 



Winchester Board Products 



6-1 



o 
o 

I 

O 

cn 



C 



HOST 

INTERFACE 

LOGIC 



2^ 



WD1015-10 

BUFFEn 

COtO'nOLLEP 



ADDR 
LOGIC 



%^ 



u 



WD10U 
ECC 



^Z 



3^ 



SECTOR 
BUFFER 



1^ 



W02797 

FLOPPY 

CONTROLLER 



z-^ 



M -N 
-1/ 



WDIOIOOS 
WINCHESTER 
CONTAOLLER 



J 



o 



DATA 
SEP 
LOGIC 



If 



CONTROL BUS 



Figure 1. WD1 002-05 BLOCK DIAGRAM 



HOST INTERFACE 

The WD1002-05 has been designed to interface with 
a Host processor via a parallel port or CPU bus con- 
figurations. The specific signals are compatible with 
the Western Digital WD1000/WD1001 series of 
Winchester-only controller boards. With the inclusion 
of the WD1015, the previous WAIT signal is no longer 
necessary but has been provided for compatiability; 



status information is always availabale to the Host 
for monitoring command progress. When the Busy 
bit is set, no other status bits are valid. 

The Host Interface connector (J5) consists of an 8-bit 
bi-directional bus, three address lines, and read and 
write signals. All functions within the WD1002-05 are 
initiated by the Host Interface. 



6-2 



Winchester Board Products 



SIG 
PIN 


SIG 
GND 


MNEMONIC 


SIGNAL NAME 


I/O 


DESCRIPTION 


1 

3 

5 

7 

9 

11 

13 

15 


2 
4 
6 
8 
10 
12 
14 
16 


DALO 

thru 

DAL 7 


DATAO 

thru 
DATA 7 


I/O 


8-bit bi-directional Data Access Lines. These lines 
remain in a high-impedance state whenever the CS 
line is de-asserted. 


17 
19 
21 


18 
20 
22 


AO 
A1 
A2 


ADDRESS 
ADDRESS 1 
ADDRESS 2 


1 


These three Address Lines are used to select one 
of nine registers in the Task File or the Sector Buf- 
fer. They must remain stable during all read and 
write operations. 


23 


24 


CS 


CARD 
SELECT 


1 


When Card Select is active along with RE or WE, 
data is read or written via the DAL bus. CS must 
make a transition for each byte read from or written 
to the Task File. 


25 


26 


WE 


WRITE 
ENABLE 


1 


When Write Enable is active along with CS, the 
Host may write data to a selected register of the 
WD1 002-05. 


27 


28 


RE 


READ 
ENABLE 


1 


When Read Enable is active along with CS, the 
Host may read data from a selected register of the 
WD1 002-05. 


29 


30 


Pull-up 
(PUP) 






Used only when replacing WD1000 or WD1001 with 
WD1002-05. Tied to a pull-up resistor. 


31 


32 


Not 
Connected 








33 


34 


Not 
Connected 








35 


36 


INTRQ 


INTERRUPT 
REQUEST 





The Intererupt Request Line is asserted whenever a 
command has been completed. It is de-asserted when 
the Status Register is read, or a new command is 
loaded via the DAL lines. 


37 


38 


DRQ 


DATA 
REQUEST 





The Data Request line is asserted whenever the Sec- 
tor Buffer contains data to be read by the Host, or 
is awaiting data to be loaded by the Host. This line 
is de-asserted whenever the buffer has been 
exhausted or filed by the Host. 


39 


40 


MR 


MASTER 
RESET 


1 


The Master Reset line initializes all internal logic 
on the WD1002-05. Sector Number, Cylinder number 
and SDH are cleared, stepping rate for Winchester 
devices are set to 7.5mS, stepping rate for floppies 
is set to 40 mS, Write Precomp is set to cylinder 128 
and Sector Count is set to 1. The DRDQ and INTRQ 
signals are de-asserted. 



Note: All even numbered pins (2 through 40) are to be used as signal grounds. Power ground is available on J6, pin 1. 



Winchester Board Products 



6-3 



o 

o 
o 
ro 

o 

en 



DRIVE CONNECTORS 

Six connectors are provided for connection of up to 
three Winchester and four Floppy drives. All 
applicable drivers and receivers have been included 
on the board to allow direct connections to the drives. 
All signals to the Floppies are daisy-chained and 
require the last (or only) drive to contain termination 
resistors. 

The Winchester control cable is daisy-chained and 
requires resistors on the last drive termination. Most 
Floppy/Winchester drives can be configured to pro- 
vide this. The data cables on the Winchester are 
radially connected to each drive. Three data cable 
connectors are included on the board. 

FLOPPY DRIVE CONTROL/DATA CONNECTOR J8 



34-PIN WINCHESTER DRIVE CONTROL 
CONNECTOR J7 



SIGNAL 


SIGNAL 




SIGNAL 


GROUND 


PIN 


I/O 


NAME 


1 


2 




NC 


3 


4 




NC 


5 


6 





Drive Select 1 


7 


8 


1 


Index/Sector 


9 


10 





Drive Select 2 


11 


12 





Drive Select 3 


13 


14 





Drive Select 4 


15 


16 





Motor On 


17 


18 





Direction In 


19 


20 





Step 


21 


22 





Write Date 


23 


24 





Write Gate 


25 


26 


1 


Track 00 


27 


28 


1 


Write Protect 


29 


30 


1 


Read Data 


31 


32 





Side Select 


33 


34 




NC 



SIGNAL 


SIGNAL 




SIGNAL 


GROUND 


PIN 


I/O 


NAME 


1 


2 





RWC 


3 


4 





Head Select 2 


5 


6 





Write Gate 


7 


8 


1 


Seek Complete 


9 


10 


1 


TRACK 000 


11 


12 


1 


Write Fault 


13 


14 





Head Select 


15 


16 




NC 


17 


18 





Head Select 


19 


20 


1 


Index 


21 


22 


1 


Ready 


23 


24 





Step 


25 


26 





Drive Select 1 


27 


28 





Drive Select 2 


29 


30 





Drive Select 3 


31 


32 




NC 


33 


34 





Direction In 



WINCHESTER DRIVE DATA CONNECTOR J1-J3 


SIGNAL 


SIGNAL 




SIGNAL 


GROUND 


PIN 


I/O 


NAME 


2 


1 




NC 


4 


3 




NC 


6 


5 




NC 


8 


7 




NC 


10 


9 




NC 


11 






GND 


12 






GND 




13 





-f MFM Write Data 




14 





-MFM Write Data 


15 






GND 


16 






GND 


\ 


17 


1 


+ MFM Read Data 




18 


1 


-MFM Read Data 


19 






GND 


20 






GND 



POWER CONNECTOR J6 



PIN 



SIGNAL NAME 



NC 

GROUND 

GROUND 

+ 5VREGULALTED 



6-4 



Winchester Board Products 



COMMANDS 

The WD1002-05 executes five macrocommands. Most 
commands feature automatic 'implied' seek, which 
means the Host system need not tell the WD1002-05 
where the R/W heads of each drive are or when to 
move them. The controller automatically performs all 
needed retries on all errors encountered including 
data ECC errors. If the R/W head mispositions, the 
WD1 002-05 automatically performs a restore and a 
re-seek. If the error is uncoverable, the WD1 002-05 
simulates a normal completion to simplify the Host 
system's software. 

Commands are executed by loading the command 
byte into the Command Resister while the controller 
is not busy. (Controller is not busy if it has completed 
the previous command). The Task File must be loaded 
prior to issuing a command. On Write/Format opera- 
tions, the Sector buffer must be filled with the 
required data before the command can be executed 
by the WD1 002-0 5. On Wincheste r dr ives no command 
executes if the Seek Complete or Ready Signal are 
de-asserted or if the Write Fault signal is asserted. 
Normally it is not necessary to poll these signals 
before issuing a command. If the WD1002-05 receives 
a command that is not defined in the following table, 
undefined results occur. 

For ease of discussion, commands are divided into 
three types: 



TYPE 


COMMAND 


7 6 5 4 3 2 10 




Test 


10 10 




Restore 


1 r3 r2 r1 rO 




Seek 


1 1 1 r3 r2 r1 rO 


II 


Read Sector 


1 1 M L 


II 


Write Sector 


1 1 M L 


III 


Format Track 


10 10 



'3-'0 


Winchester Disk Drives 


Floppy Disk Drives 


0000 


~35fiS 


~15 /iS 


0001 


0.5 ms 


1.0 ms 


0010 


1.0 ms 


2.0 ms 


0011 


1.5 ms 


3.0 ms 


0100 


2.0 ms 


4.0 ms 


0101 


2.5 ms 


5.0 ms 


0110 


3.0 ms 


6.0 ms 


0111 


3.5 ms 


8.0 ms 


1000 


4.0 ms 


10 ms 


1001 


4.5 ms 


12 ms 


1010 


5.0 ms 


14 ms 


1011 


5.5 ms 


16 ms 


1100 


6.0 ms 


18 ms 


1101 


6.5 ms 


20 ms 


1110 


7.0 ms 


25 ms 


1111 


7.5 ms 


40 ms 



I = DMA Read Mode 

I = 0, Programmed I/O Mode 

1 = 1, DMA Mode 

L = Read/Write Long 

L = 0, Normal R/W Transfer 

L = 1, R/W ECC Bytes from Host 

M = Multiple Sector 

M = 0, Single Sector R/W 

M = 1, Multiple Sector R/W 



o 
o 
ro 

o 
en 



^3 - ^0 = STEPPING RATES 



Winchester Board Products 



6-5 



o 
o 

lO 
I 

o 



I, L, M FLAGS 

The T Flag allows the Interrupt line (INTRQ) to be 
activated when the data is available. The Data 
Request signal is always activated when the 
WD1002-05 either needs data (in the case of the Write 
commands) or has data available for the Host. If the 
'I' Flag is not set, then the INTRQ is activated before 
the start of data transfer. If set, then INTRQ is set 
after the last byte of the last sector has been transfer- 
red to the Host. 

The 'L' Flag allows the Host to Read the ECC bytes 
as data. The ECC generator is inhibited. This func- 
tion may be used for diagnostic and performance pur- 
poses by allowing the Host to compute and check 
ECC operation. Since the floppy disk format does not 
allow ECC, the 'L' Flag Is a "don't care" bit in this 
case. 

The 'M' Flag allows multiple sectors to be transfer- 
red via one command. The Sector Count Register In 
the Task File is used to specify the number of sec- 
tors to be transferred from a track. Retries and ECC 
correction (if applicable) are performed on each 
sector. 

TYPE I COMMANDS 

These commands simply position the R/W heads of 
the selected drive or run Diagnostics, Restore 
and Seek Commands have explicit stepping rate 
fields. The lower four bits of these commands 
form the stepping rate. 



Test 

The Test Command is used to run internal diagnostics 
for checking WD1002-05 board function. It is mainly 
employed to Isolate faults In the board logic. This 
command is always executed when MR is asserted. 
Any faults are reported as error codes. 

Restore 

The Restore Command is used to move the R/W 
heads to the Track position. It is usually performed 
after a power-up operation. When restoring a Win- 
chester drive, the specified stepping rate is not used; 
the actual Restore rate is handshaked with the Seek 
Complete. When Restoring a floppy drive, the R3-R0 
rate is used when the rate is equal to or slower than 
8 msec. On rates faster than 8 msec., the restore step- 
ping rate defaults to 8 msec. On both floppy and Win- 
chester, the rate is stored for subsequent implied 
Seeks for Read/Write Commands. 

Seek 

The Seek Command is used to position the 
Read/Write to a specified location. Since the Read 
and Write Commands feature implied Seek, this com- 
mand is normally used to perform simultaneous 
(overlap Seek) operations on multiple drives. The 
specified stepping rate Is used for Track to Track 
access time. 

The desired location is loaded into the cylinder 
registers prior to issuing the command. On Win- 
chester drive, the Write Fault, Seek Complete, and 
Ready lines must be true for the command to execute. 
The Seek Complete line is not checked after all step- 
ping pulses have been issued. A Seek operation on 
a floppy drive will be performed regardless of the state 
of Write Protect on the Drive Interface. 



6-6 



Winchester Board Products 



TYPE II COMMANDS 

This type of command is cliaracterized by a transfer 
of a biock of data from the WD1 002-05 buffer to the 
Host. This command has an implicit stepping rate as 
set by the last Restore or Seek command. 

Read Sector 

The Read Sector Command is used to transfer a 
specified sector from any drive to the Host buffer. The 
stepping rate, specified in an earlier Restore or Seek 
command, is used to automatically perform a Seek 
prior to execution of the Read. After the Task File has 
been loaded with the desired parameter, the on-board 
Sector Buffer is filled with the data from the disk. The 
Host may then read this data by accessing the Sec- 
tor Buffer repeatedly. 

The option flags I, L, M are also available and work 
exactly as described in the I, L, M FLAG description. 

Write Sector 

The Write Sector Command is used to transfer a block 
of data from the on-board buffer to a specified sec- 
tor. After the command is issued, the WD1002-05 
generates a DRQ and the Host proceeds to fill the 
buffer. Once filled, the desired sector is searched for. 
This may include an implied Seek. After the ID field 
is found the Write Gate signal Is activated and the 
data is MFM encoded and written serially to the 
selected drive. The Write Precompensation Register 
in the Task File specifies the starting cylinder on a 
Winchester drive where precomp is to be enabled. The 



WFC is configured with no precompensation when 
writing to the floppies. The user may cut the etch on 
WD2797 pin 1 so that precomp is always enabled or 
jumper it to pin 29 so that precomp is enabled for 
tracks greater than 43. 

The option Flags 'L' and 'M' are also available and 
work exactly as described in the I, L, M FLAG 
description. 

TYPE 111 COMMAND 

Format Track 

This command is used to format a drive prior to 
reading or writing it causes ID fields, gaps and all 
information to be written to a selected Track for 
initialization. The on-board Sector Buffer serves a dif- 
ferent purpose for this command; it contains the Bad 
Block Flag and the physical numbers of the sectors 
to be recorded. Since the actual sector numbers are 
now taken from the buffer, unlimited Interleaving is 
allowed. The Sector Count Register in the Task File, 
normally used during a multiple sector R/W, now 
specifies the number of sectors to be formatted. The 
Format Track Command also features the implied 
Seek option, so that the entire drive can be format- 
ted by incrementing the cylinder number after each 
execution. 



g 

o 
o 

lO 

o 

U1 



Winchester Board Products 



6-7 



o 
o 
ro 

o 



SETTING UP TASK FILES 

Before any of the five commands may be executed, 
a set of parameter registers called the Task File must 
be set up. For most commands, this informs the 
WD1002-05 of the exact location on the disk that the 
transfer should take place. For a normal read or write 
sector operation, the Sector Number, the 
Size/Drive/Head, Cylinder Number, and Command 
registers (usually in that order) are written. 

Note that most of these registers can be read as well 
as written. These registers nomnally are not read from, 
but this feature is provided so that error reporting 
routines can determine physically where an error 
occurred without recalculating the sector, head and 
cylinder parameters. 

Since the WD1002-05 can recall all the Task File 
parameters sent to it, it is recommended that Task 
File parameters be stored in the WD1 002-05 as they 
are calculated. This saves the programmer a few 
instructions by not maintaining two copies of the 
same information. 

REGISTER SELECTION ARRAY 



cs 


A2 


A1 


AO 


RE 


WE 


1 


X 


X 


X 


Deselected 


Deselected 














Sector Buffer 


Sector Buffer 











1 


Error Register 


Write Precomp* 








1 





Sector Count 


Sector Count 








1 


1 


Sector Number 


Sector Number 





1 








Cylinder Low 


Cylinder Low 





1 





1 


Cylinder High** 


Cylinder High** 





1 


1 


1 


Size/Drive/Head 


Size/Drive/Head 





1 


1 


1 


Status Register 


Command 
Register 



'Not used on Floppy 

'When LSB = 1, permits 48 t.p.i. Floppy disk to be 
used on 96 t.p.i. Floppy disk system, for all com- 
mands used. 



SDH REGISTER 


BIT 


7 


6 5 


4 3 


2 1 


Function 


Sec 


Sec 


Drive 


Head/ 




Ext 


Size 


Select 


Drive 
Select 




SECTOR EXTENSION 


BIT 7 


(WINCHESTER ONLY) 





Selects CRC for data field 


1 


Selects ECC for data field 


BIT 6 


BITS 


SECTOR SIZE 





1 
1 




1 


1 


256 Bytes 
515 Bytes 
1024 Bytes 
128 Bytes 


BIT 4 


BIT 3 


DRIVE SELECTION 








Winchester Drive Sel 1 





1 


Winchester Drive Sel 2 


1 





Winchester Drive Sel 3 


1 


1 


Floppy Drive Sel 










WIN- 












CHESTER 


FLOPPY DRIVE 


BIT 2 


BIT1 


BITO 


HEAD NR 


& HEAD NRS. 














DR1 HDO 








1 


1 


DR1 HD1 





1 







2 


DR2 HDO 





1 




1 


3 


DR2 HD1 


1 








4 


DR3 HDO 


1 





1 


5 


DR3 HD1 


1 


1 







6 


DR4 HDO 


1 


1 




1 


7 


DR4 HD1 



Since most hard disk drives contain more than one 
head per position, it is more efficient to step the R/W 
head assemblies of most disk drives by, cylinders, 
not tracks. In other words, the disk driver software 
should be designed to read or write all data that is 
directly accessible by all the heads on a positioner 
before stepping to a new cylinder. 



STATUS & ERROR REGISTERS 

The Status Register is used to monitor command flow 
and to supply the Host with specific information 
about the drive. A bit called "Busy" (Bit 7) indicates 
that the WD1002-05 is executing a current command 
and register access is prohibited. This bit can be read 
at any time by the Host but all other bits are invalid 
when this status bit is set. 

The Error Register is used to report different types 
of errors caused by execution of the last command. 
To ease programming, the LSB of the Status Register 
is set if any of the bits in the Error Register are also 
set. 



6-8 



Winchester Board Products 



STATUS REGISTER BITS 



ERROR REGISTER BITS 



BIT 



STATUS REGISTER 



Busy 
Ready 
Write Fault 
Seek Complete 
Data Request 
Corrected Date 

Error 





Normal Operation 


Diagnostic Operation 


Bit 


Status Reg. Bit = 1 


Status Reg. Bit = 


7 


Bad Block Detect 




6 


Uncorrectable Error 




5 


CRC Error ID Field 


WD1015 Error 


4 


ID Not Found 


WD1014 Error 


3 


- 


Sector Buffer Error 


2 


Aborted Command 


WD1010 Error 


1 


TKOOO Error 


WD2797 Error 





DAM not found 


Pass WD1002 is 
Functional 



o 
o 
ro 

o 



SPECIFICATIONS: 

Encoding methiod: 
Cylinders per Head: 
Sectors per Track: 
Heads: 
Drive Selects: 
Step Rate: 



Data Transfer Rate: 

Write Precomp Time: 

Sectoring: 

Host Interface: 

Drive Cable Length: 

Host Cable Length: 

Power Requirements: 

Ambient Operating Temperature 

Relative Humidity: 

Air Flow 

MTBF: 

MTTR: 

Length: 

Width: 

Height: 

Mounting Centers: 



HARD DISK 

MFM 

Up to 1024 

Up to 64 

8 

3 (ST506) 

35 usee, to 7.5 msec. 

(0.5 msec, increments) 

5.0 Mbits/sec 

12 nsec 



FLOPPY DISK 

MFM 

Up to 245 

Up to 64 

2 

4 (SA450) 

0-40 msec. 

(1 of 16 rates in this range) 

250 Kbits/sec 

100-300 nsec adj. 
Soft 

8-Bit bi-directional bus 
10 ft (3M) max. 
3 ft (1M) max. 
+ 5V ±5%,3.0A Max. 
0°C to 50° C (32° F to 122° F) 
20% to 80% 

100 linear ft. per minute at .5" from component surface 
10,000 POH 
30 minutes 
8.00 in 
5.75 in 
0.75 in 
7.50 X 5.250 in 



Winchester Board Products 



6-9 



6-10 Winchester Board Products 



WESTERN DIGITAL 

CORPORATION 

WD1002-HDO Winchester Controller 



D 

_^ 
o 
o 

N) 

± 
O 
O 



FEATURES 

CONTROL FOR UP TO 3 WINCHESTER 

DRIVES 

ON BOARD DATA SEPARATOR AND 

WRITE PRECOMPENSATION 

128, 256, 512, AND 1024 BYTE SECTOR SIZES 

PROGRAMMABLE SECTOR SIZES TO IK 

AUTOMATIC TRACK FORMATTING ON HARD 

DISKS 

MULTIPLE SECTOR OPERATIONS 

5-BIT SINGLE BURST ERROR CORRECTION 

ON WINCHESTER 

CRC GENERATION/VERIFICATION ON ID 

FIELDS 

5-MBIT DATA TRANSFER RATE 

ECC DIAGNOSTIC COMMANDS (READ LONG 

& WRITE LONG) 

SINGLE +5V POWER SUPPLY 



DESCRIPTION 

The WD1002-HDO Winchester Controller is a stand- 
alone general purpose board designed to interface 
up to three 51/4" Winchester hard disks. The Win- 
chester Controller implements all the logic required 
for a variable length sector (to 1 K bytes). ECC cor- 
rection, data separation and Host interface circuitry. 
The Winchester interface is based on the Seagate 
ST506. All necessary buffers and drivers / receivers 
are on board. 

Communication to and from the Host is made via a 
separate computer access port. This port consists 
mainly of an 8-blt bi-directional bus and appropriate 
control signals. All data to be written to or read from 
the disk, status information, and macro commands 
are transferred via this 8-bit bus. An on-board Sector 
Buffer allows data transfers to the Host computer at 
a rate independent of the drive transfer rate. 

The WD1002-HDO Controller board is based on the 
WD1014 EDS device and WD1015 Buffer Controller 
device, as well as the WD1010 Winchester Disk Con- 
troller chips. It is form factor compatible with most 
51/4" Winchesters and may be directly mounted on 
the drive. 



Winchester Board Products 



6-11 



ARCHITECTURE 



D 

-A 
o 
o 
ro 

X 
O 
O 



The Block Diagram of the WD1002-HDO Is shown In 
Figure 1. The heart of the system is the WD1015 Buf- 
fer/Controller, which generates and processes all 
data and control lines, along with the WD1014 EDS 
that generates all control signals that cannot be 
handled in real time by the WD1015. 

Commands, parameters, and data are entered via the 
Host Interface Logic. Data Is read from the selected 
drive and transferred to the Sector Buffer. If an error 
In the data field has been encountered, the WD1015 
Instructs the controller to perform retries 
automatically. 



On a Winchester drive, the WD1014 ECC device Is 
enabled and error correction procedures invoked. 
Error Correction may be disabled via software from 
the Host to allow CRC-only formatted Winchester 
drives to be used In the system. The WD1002-HDO 
provides Data Separation and Write Precompensation 
Logic for data transfers. After the Sector Buffer is full, 
the WD1015 Informs the Host Interface Logic that 
data may be read by the Host. The use of an on-board 
Sector Buffer provides both transparent error correc- 
tion and data transfers to the Host that are Indepen- 
dent of drive transfer rates. 



O 



MOST 

INTEBfACE 

LOGIC 




SZ. 



:^ 



\7 



L7^ 



7\ 



CONTROL BUS 



7^ 



1— -N^ WD1010 /1-\. DATA y^-^v 
) WINCHESTER C ) SEC C ) 

' Y CONTROLLER VV '■°°'^ NV^ 



FIGURE 1. WD1002HDO BLOCK DIAGRAM 



HOST INTERFACE 

The WD 1002-HDO Is designed to interface to a Host 
processor via a parallel port or CPU bus configura- 
tions. The specific signals are compatible with the 
Western Digital WD1000/WD1001 series of 
Winchester-only controller boards. With the inclusion 
of the WD1015, the previous WAIT signal is no longer 
necessary but has been provided for compatibility; 
status information is always available to the Host for 



monitoring command progress. When the Busy bit is 
set, no other status bits are valid. 

The Host interface connector (J5) consists of an 8-bit 
bi-directional bus, three address lines, and read and 
write signals. All functions within the WD1002-HDO 
are initiated by the Host interface. 



6-12 



Winchester Board Products 



HOST INTERFACE CONNECTOR J5 



SIG. 


SIG. 


MNEMONIC 


SIGNAL 


I/O 


FUNCTION 


PIN 


GND. 




NAME 






1 


2 


DALO 


DATA ACCESS 


I/O 


8-bit bi-directional Data Access Lines. 


3 


4 


thru 


LINE thru 




These lines remain in a high-impedance 


5 


6 


DAL 7 


DATA ACCESS 




state whenever the CS line is de-asserted 


7 


8 




LINE 7 






9 


10 










11 


12 










13 


14 










15 


16 










17 


18 


AO 


ADDRESS 


1 


These three Address Lines are used to sel- 


19 


20 


A1 


ADDRESS 1 




ect one of nine registers in the Task File or 


21 


22 


A2 


ADDRESS 2 




the Sector Buffer. They must remain stable 


23 


24 


CS 




1 


during all read and write operations. 
When Card Select is active along with RE 


CARD SELECT 












or WE, data is read or written via the DAL 












bus. CS must make a transition for each 


25 


26 


WE 




1 


byte read or written to the Task File. 
When Write Enable is active along with 


WRITE ENABLE 












CS, the Host may read data to a selected 


27 


28 


RE 




1 


register of the WD1002-HDO. 


READ ENABLE 


When Read Enable is active along with 












CS, the Host may read data from a 












selected register of the WD1002-HDO. 


29 


30 


Pull-up (PUP) 






Used only when replacing WD1000 or 
WD1001 with WD1002-HDO. Tied to a pull- 
up register. 


31 


32 


NOT 
CONNECTED 








33 


34 


NOT 
CONNECTED 








35 


36 


INTRO 


INTERRUPT 
REOUEST 





The Interrupt Request Line is asserted 
whenever a command has been completed. 
It is de-asserted when the Status Register is 
read, or a new command is loaded via the 
DAL lines. 


37 


38 


DRQ 


DATA REQUEST 





The Data Request line is asserted whenever 
the Sector Buffer contains data to be read 
by the Host, or is awaiting data to be loaded 
by the Host. This line is de-asserted 
whenever the buffer has been exhausted or 


39 


40 


MR 




1 


filled by the Host. 

The Master Reset line initializes all internal 


MASTER RESET 












logic on the WD1002-HDO Sector Number, 












Cylinder Number and SDH are cleared, step- 












ping rate for Winchester devices are set to 












7.5 msec. Write Precomp is set to cylinder 












128 and Sector Count is set to 1. The DRO 












INTRO signals are de-asserted. 


Note: 










All even numbered pins (2 through 40) are to 


Grounds 










be used as signal grounds. Power ground is 
available on J6, pin 1. 



Winchester Board Products 



6-13 



o 

o 
o 
ro 

X 
D 
O 



DRIVE CONNECTORS 

Five connectors are provided for connection of up to 
tinree Winchester drives. All applicable drivers and 
receivers have been included on the board to allow 
direct connections to the drives. 

The Winchester control cable is daisy-chained and 
requires termination resistors on the last drive. Most 
Winchester drives can be configured to provide this. 
The data cables are radially connected to each drive. 
Three data cable connectors are included on the 
board. 

34-PIN WINCHESTER DRIVE CONTROL 
CONNECTOR J7 



SIGNAL 


SIGNAL 




SIGNAL 


GROUND 


PIN 


I/O 


NAME 


1 


2 





RWC 


3 


4 





Head Select 2 


5 


6 





Write Gate 


7 


8 


1 


Seek Complete 


9 


10 


1 


TRACK 000 


11 


12 


1 


Write Fault 


13 


14 





Head Select 


15 


16 




NC 


17 


18 





Head Select 1 


19 


20 


1 


Index 


21 


22 


1 


Ready 


23 


24 





Step 


25 


26 





Drive Select 1 


27 


28 





Drive Select 2 


29 


30 





Drive Select 3 


31 


32 




NC 


33 


34 





Direction In. 



WINCHESTER DRIVE DATA CONNECTIONS 
AND DESCRIPTIONS J1-J3 



SIGNAL 


SIGNAL 




SIGNAL 


GROUND 


PIN 


I/O 


NAME 


2 


1 




NC 


4 


3 




NC 


6 


5 




NC 


8 


7 




NC 


10 


9 




NC 


11 






GND 


12 






GND 




13 





+ MFM Write Data 




14 





-MFM Write Data 


15 






GND 


16 






GND 




17 


1 


+ IV1FM Read Data 




18 


1 


-MFM Read Data 


19 






GND 


20 






GND 



POWER CONNECTOR 

A four pin AMP connector is used for power input to 
the WD1002-HDO. The pin-outs are as shown: 

POWER CONNECTOR J6 



PIN 


SIGNAL NAME 


1 
2 
3 
4 


NC 

GROUND 

GROUND 

-t-5V REGULATED 



COMMANDS 

The WD1002-HDO executes five macro commands. 
Most commands feature automatic 'implied' seek, 
which means the Host system need not tell the 
WD1002-HDO where to RA/V heads of each drive are 
or when to move them. The controller automatically 
performs all needed retries on all errors encountered 
including data ECO errors. If the R/W head misposi- 
tions, the WD1002-HDO automatically performs a 
restore and re-seek. If the error is unrecoverable, the 
WD1002-HDO simulates a normal completion to 
simplify the Host system's software. 

Commands are executed by loading the command 
byte into the Command Register while the controller 
is not busy. (Controller is not busy if it has completed 
the previous command). The Task File must be loaded 
prior to issuing a command. On Write/Format opera- 
tions, the Sector Buffer must be filled with the 
required data before the command can be executed 
by the WD1002-HDO. On Winchester d riv es no c om- 
mand executes if the Seek Com plete or Rea dy 
signals are de-asserted or if the Write Fault signal 
is asserted. Normally, it is not necessary to poll these 
signals before issuing a command. If the 
WD1002-HDO receives a command that is not defined 
in the following table, undefined results occur. 



The Restore Command is used to move the RAA/ 
heads to the Track position. It is usually performed 
after a power-up operation. The Restore Command 
does not use the specified stepping rate, instead the 
rate is determined by two handshakes with the Seek 
Complete signal. The specified rate is stored for use 
by the Read and Write Commands. 



6-14 



Winchester Board Products 



For ease of discussion, commands are divided into 
three types: 



TYPE 


COMMAND 


7 6 5 4 3 2 10 




Test 


10 10 




Restore 


1 ^3 ^2 ^1 ^0 




Seek 


1 1 1 ^3 ^2 M ^0 


II 


Read Sector 


1 1 M L 


III 


Write Sector 


1 1 M L 


III 


Format Track 


10 10 



^3-^0 = STEPPING RATES 



'3.^0 


Winchester Disk Drives 


0000 


-35 /isec 


0001 


0.5 msec 


0010 


1.0 msec 


0011 


1.5 msec 


0100 


2.0 msec 


0101 


2.5 msec 


0110 


3.0 msec 


0111 


3.5 msec 


1000 


4.0 msec 


1001 


4.5 msec 


1010 


5.0 msec 


1011 


5.5 msec 


1100 


6.0 msec 


1101 


6.5 msec 


1110 


7.0 msec 


1111 


7.5 msec 



I = DMA Read Mode 

I = 0, Programmed I / O Mode 
I = 1, DMA Mode 

L = Read / Write Long 

L = 0, Normal R / W Transfer 

L = 1, R/W ECC Bytes from Host 

M = Multiple Sector 

M = 0, Single Sector R/W 
M = 1, Multiple Sector R/W 



TYPE I COMMANDS 

These commands simply position the R/W heads 
of the selected drive or run Diagnostics. Restore and 
Seek Commands have explicit stepping rate fields. 
The lower four bits of these commands form the step- 
ping rate. 



Test 

Bit code: 10 10 

The Test Command is used to run internal diagnostics 
for checking WD1002-HDO board function. It is mainly 
employed to isolate faults in the board logic. This 
command is always executed when MR Is assert- 
ed. Any faults are reported as error codes. 

Restore 

The Restore Command is used to move the R/W 
heads to the Track position. It is usually performed 
after a power-up operation. The Restore Command 
does not use the specified stepping rate, instead the 
rate is determined by two handshakes with the Seek 
Complete signal. The specified rate is stored for use 
by the Read and Write Commands. 

Seek 

The Seek Command is used to position the 
Read/Write to a specified location. Since the Read 
and Write Commands feature implied Seek, this com- 
mand is normally used to perform simultaneous 
(overlap Seek) operations on multiple drives. The 
specified stepping rate is used for Track to Track 
access time. 

The desired location is loaded into the cylinder 
registers prior to issuing the command. On Win- 
chester drive, the Write Fault, Seek Complete, and 
Ready lines must be true for the command to execute. 
The Seek Complete line is not checked after all step- 
ping pulses have been issued. 

TYPE II COMMAND 

This type of command is characterized by a transfer 
of a block of data from the WD1002-HDO buffer to 
the Host. This command has an implicit stepping rate 
as set by the last Restore or Seek command. 

Read Sector 

The Read Sector Command Is used to transfer a 
specified sector from any drive to the Host buffer. The 
stepping rate, specified in an earlier Restore or Seek 
command, is used to automatically perform a Seek 
prior to execution of the Read. After the Task File has 
been loaded with the desired parameter, the on-board 
Sector Buffer is filled with the data from the disk. The 
Host may then read this data by accessing the Sec- 
tor Buffer repeatedly. 

Sector Buffer 

The T Flag allows the Interrupt line (INTRO) to be 
activated when the data is available. The Data 
Request signal is always activated when the 
WD1002-HDO either needs data (in the case of the 
Write commands) or has data available for the Host. 
If the 'I' Flag is not set, then the INTRO is activated 
before the start of data transfer. If set, then INTRO 
is set after the last byte of the last sector has been 
transferred to the Host. 



O 

o 
o 

± 
o 
O 



Winchester Board Products 



6-15 



o 

o 
o 

lO 

X 
O 
O 



The 'U Flag allows the Host to Read the ECC bytes 
as data. The ECC generator is inhibited. This func- 
tion may be used for diagnostic and performance pur- 
poses by allowing the Host to compute and check 
ECC operation. 

The 'M' Flag allows multiple sectors to be transfer- 
red via one command. The Sector Count Register in 
the Task File is used to specify the number of sec- 
tors to be transferred from a track. Retries and ECC 
correction (if applicable) are performed on each 
sector. 

TYPE III COMMANDS 

Write Sector 

The Write Sector Command is used to transfer a block 
of data from the on-board buffer to a specified sec- 
tor. After the command is issued, the WD1002-HDO 
generates a DRQ and the Host proceeds to fill the 
buffer. Once filled, the desired sector is searched for. 
This may include an implied Seek. After the ID field 
is found, the Write Gate signal is activated and the 
data is MFM encoded and written serially to the 
selected drive. The Write Precompensation Register 
in the Task File specifies the starting cylinder on a 
Winchester drive where precomp is to be enabled. 

The option Flags 'L' and 'M' are also available and 
work exactly as described in the Read Sector 
command. 

Format Track 

This command is used to format a drive prior to 
reading or writing. It causes ID fields, gaps, and all 
information to be written to a selected Track for 
initialization. The on-board Sector Buffer serves a dif- 
ferent purpose for this command; it contains the Bad 
Track Flag and the physical numbers of the sectors 
to be recorded. Since the actual sector numbers are 
now taken from the buffer, unlimited Interleaving is 
allowed. The Sector Count Register in the Task File, 
normally used during a multiple sector RA/V, now 
specifies the number of sectors to be formatted. The 
Format Track Command also features the implied 
Seek option, so that the entire drive can be format- 
ted by Incrementing the cylinder number after each 
execution. 

SETTING UP TASK FILES 

Before any of the five commands may be executed, 
a set of parameter registers called the Task File must 
be set up. For most commands, this informs the 
WD1002-HDO of the exact location on the disk that 
the transfer should take place. For a normal read or 
write sector operation, the Sector Number, the 
Size/Drive/Head, Cylinder Number, and Command 
registers (usually in that order) are written. 



Note that most of these registers can be read as well 
as written. These registers normally are not read from, 
but this feature is provided so that error reporting 
routines can determine physically where an error 
occurred without recalculating the sector, head and 
cylinder parameters. 

Since the WD1002-HDO can recall all the Task File 
parameters sent to it, it is recommended that Task 
File parameters be stored in the WD1002-HDO as they 
are calculated. This saves the programmer a few 
instructions by not maintaining two copies of the 
same information. 

REGISTER SELECTION ARRAY 



cs 


A2 


A1 


AO 


RE 


WE 


1 


X 


X 


X 


De-selected 


De-selected 














Sector Buffer 


Sector Buffer 












1 


1 



Error Register 
Sector Count 


Write Precomp 
Sector Count 








1 


1 


Sector Number 


Sector Number 







1 

1 
1 





1 




1 




Cylinder Low 
Cylinder High 
Size/Drive/Head 


Cylinder Low 
Cylinder High 
Size/Drive/Head 





1 


1 


1 


Status Register 


Command 
Register 



SDH REGISTER 


BIT 


7 . 


6 5 


4 3 


2 1 


Function 


Sec 


Sec 


Drive 


Head 




Ext 


Size 


Select 


Select 


BIT 7 


SECTOR EXTENSION 





Selects CRC for data field 


1 


Selects ECC for data field 


BIT 6 


BITS 


SECTOR SIZE 








256 Bytes 





1 


512 Bytes 


1 





1024 Bytes 


1 


1 


128 Bytes 


BIT 4 


BITS 


DRIVE SELECTED 








Winchester Drive Sel 1 





1 


Winchester Drive Sel 2 


1 





Winchester Drive Sel 3 


1 


1 




BIT 2 


BIT1 


BITO 


HEAD 




















1 


1 





1 





2 





1 


1 


3 


1 








4 


1 





1 


5 


1 


1 





6 


1 


1 


1 


7 



6-16 



Winchester Board Products 



Since most hard disk drives contain more than one 
head per positioner, it is more efficient to step the 
R/W head assembiies of most disk drives by cyiinders, 
not tracks. In other words, the disk driver software 
shouid be designed to read or write ali data that is 
directly accessible by all the heads on a positioner 
before stepping to a new cylinder. 

STATUS & ERROR REGISTERS 

The Status Register is used to monitor command flow 
and to supply the Host with specific information 
about the drive. "Busy" (Bit 7) indicates that the 
WD1002-HDO is executing a current command and 
register access is prohibited. This bit can be read at 
any time by the Host but all other bits are invalid when 
this status bit is set. 

The Error Register is used to report different types 
of errors caused by execution of the last command. 
To ease programming, the LSB of the STATUS 
Register is set if any of the bits in the Error Register 
are also set. 



STATUS REGISTER BITS 



BIT 


STATUS REGISTER 




7 
6 
5 


Busy 
Ready 
Write Fault 


o 
o 

lO 

i 


4 
3 
2 
1 



Seek Complete 
Data Request 
Corrected Data 


o 
o 


Error 




ERROR REGISTER BITS 




Bit 


Nomrial Operation 
Status Reg.Bit = 1 


Diagnostic Operation 
Status Reg.Bit = 




7 


Bad Block Detect 






6 


Uncorrectable Error 






5 


CRC Error ID Field 


WD1015 Error 




4 


ID Not Found 


WD1014 Error 




3 


- 


Sector Buffer Error 




2 


Aborted Command 


WD1010 Error 




1 


TKOOO Error 









DAM not found 


Pass WD1002 is 
Functional 





SPECIFICATIONS: 

Encoding method: 
Cylinders per Head: 
Sectors per Track: 
Heads: 
Drive Selects: 
Step Rate: 

Data Transfer Rate: 

Write Precomp Time: 

Sectoring: 

Host Interface: 

Drive Cable Length: 

Host Cable Length: 

Power Requirements: 

Ambient Operating 

Temperature: 

Relative Humidity: 

Air Flow: 

MTBF: 

MTTR: 

Length: 

Width: 

Height: 

Mounting Centers: 



HARD DISK 

MFM 

Up to 1024 

Up to 64 

8 

3 (ST506) 

35 iisec to 7.5 msec. 

(0.5 msec, increments) 

5.0 Mbits / sec 

12 nsec 

Soft 

8-bit bi-directional bus 

10 ft (3M) max. 

3 ft (1M) max. 

+ 5V 5%, 3.0A Max. 

0°C to 50°C (32°F to 122°F) 

20% to 80% 

100 linear ft per minute at .5" from component surface. 

10,000 POH 

30 minutes 

8.00 in 

5.75 In 

0.75 in 

7.50 X 5.250 in 



Winchester Board Products 



6-17 



6-18 Winchester Board Products 



WESTERN DIGITAL 

CORPORATION 

WD1002-SHD Winchester Disk Controller 



FEATURES 

• SINGLE + 5V SUPPLY 

• SASI™ HOST INTERFACE 

• CONTROL FOR UP TO 2 WINCHESTER DRIVES, 
UP TO 8 R/W HEADS EACH 

• 32- BIT ECC FOR WINCHESTER DATA COR- 
RECTION 

• DIAGNOSTIC READS AND WRITES FOR 
CHECKING ERROR CORRECTION 

• BAD TRACK MAPPING CAPABILITY 



AUTOMATIC FORMATTING 

256 OR 512 BYTES PER SECOND 

SELECTABLE INTERLEAVE 

MULTIPLE SECTOR READS AND WRITES 

BUILT-IN DATA SEPARATOR 

BUILT-IN WRITE PRECOMPENSATION 

IMPLIED SEEKS 

OVERLAPPED SEEKS 



O 

o 
o 
to 

di 

Z 
O 



DESCRIPTION 

The WD1002-SHD is a stand alone, general purpose 
Winchester Controller Board designed to interface up 
to two Winchester Disk Drives to a Host Processor. 
The Winchester Drive signals are based upon the 
Floppy look-alil<e interface available on the Seagate 
Technology ST506 and other connpatible drives. All 
necessary receivers and drivers are included on the 
board to allow direct connection to the drive. 

Communications to and from the Host Computer are 
made via a separate computer access port. This port 

SASI ^'^ is a trademark of Shugart Assoc. 



conforms to the popular Shugart Associates System 
Interface (SASI). It consists of control signals and an 
8-bit, bi-directional bus. All data to be written to or 
read from the disk, status information, and command 
parameters are transferred via this bus. An on-board 
Sector Buffer allows bus transfers to be executed 
independently of the actual data transfer of the drive. 

The WD1002-SHD is based upon the WD1015-02, 
WD1010, and WD1100-13, specifically designed for 
Winchester disk drive control. 



Winchester Board Products 



6-19 



D 

o 
o 
ro 

in 

z 
o 



ARCHITECTURE 

The WD1002-SHD has five on-board interface connec- 
tors. Other connectors are for test only and should 
not be used. 

The five connectors consist of a Power Connector, Host 
Interface Connector, Winchester Drive Control Connec- 
tor and two Winchester Data Cable Connectors. 

SPECIFICATIONS: 

DRIVE INTERFACES 

Encoding Method 
Cylinders per Drive 
Bytes per Sector 
Sectors per Track 

Head Selects 

Drive Selects 

Stepping Rates/Algorithms 

Data Transfer Rate 

Write Precomp Time 

Sectoring 

Max Cable Length 

Control (Total Daisy Chain) 

Data (Radial - each) 

HOST INTERFACE 

Type 

Max Cable Length (Total Daisy Chain) 

Termination 

Addressing 

POWER 

Voltage 
Current 
Ripple 

MECHANICAL 

Length 

Width 

Height (Max inci leads, board, & components 

ENVIRONMENTAL - OPERATING 

Ambient Temperature 
Relaltive Humidity 
Altitude 

CONNECTORS 

MECHANICAL INFORMATION 

Table 1 defines the connectors and a source for the 
mating connectors on the associated cables. 



The Winchester Drive Control Cable is daisy-chained 
to the drive. The Drive Data Connectors carry differen- 
tial signals and are radially connected. 

The Host Interface Connector provides a path to the 
Host thru a SASI Bus. Other SASI-compatible con- 
trollers may also be connected to the same bus. 



MFM 

Programmable 
Selectable, 256 or 512 
32 (256 bytes/sector) 
17 (512 bytes/sector) 

8 

2 

Programmable 

5 Mbits/sec 

12 nsec 

Soft 

6M (20ft.) 
6M (20ft.) 



SASI 

4.5M (15 ft.) 

Socketed 220/330 pack 

Jumperable, to 7 (factory default = 0) 



5V -t- 5% 

2.0A Max, 1.5ATYP 

0.1 volts max, 0.1 to 25 MHz 



8.0 inches 
5.75 inches 
0.75 inches 



0°C (32°F) to 55°C (131°F) 
10% to 90% non-condensing 
to 3000M (10,000ft.) 



6-20 



Winchester Board Products 



Table 1. CONNECTORS 



REFERENCE DESIGNATION 


INTERFACE FUNCTION 


EQUIVALENT MATING 
CONNECTOR 


P1 

P2 

J1 

J2,J3 

J4 


Power 

SASi Bus 

Winchester Control (Daisy-Cfiain) 
Winchester Data (Radial) 
Test - do not use 


AMP1-480424-0 (Housing) 
AMP350078-4 (Pins) 

AMP88379-8 
AMP88373-3 
AMP88377-4 



o 

o 

o 

in 

X 

o 



ADDRESS 
COUNTER 



DATA 
BUFFER 



WD11C00-13 

ECC 

SUPPORT 

DEVICE 



WD 101 0-05 
WINCHESTER 

DISK 
CONTROLLER 



lOOL^ 



D SEPARATION /IJ\ 
& WRITE ) 

PRECOMP \^ 



DRIVERS AND 
RECEIVERS 



D WINCHESTER 
DISK DRIVES 



/" 







S£ 



SASI DATA 
TRANSCEIVER 



SENSE 
SIGNALS- 



2i 



WD1015-02 

CONTROL 

PROCESSOR 



'^ 



DRIVERS AND 
RECEIVER 







SASI 

BUS 

CONTROLLER 



t 

CONTROL 
SIGNALS 



v^ 



RESET CIRCUIT 

AND WRITE GATE 

DEGLITCHER 




Figure 1. WD1002SHD BLOCK DIAGRAM 



Winchester Board Products 



6-21 



HOST INTERFACING 



D 

o 
o 
ho 

in 

X 
Q 



The WD1002-SHD Controller has been designed to 
interface to the Shugart Associates System Interface 
(SASI) bus. All interfacing is done through the SASI 
connector (P2). Up to eight SASI compatible devices 
(including the Host) may be connected to this bus. 
The cable terminating resistor pack is socketed on 
the last controller in the daisy-chain to aid flexibility 
in daisy-chaining bus devices. 



The controller is shipped from the factory configured 

to respond to SASI device address 0. This may be 

changed by the user to any SASI address (0 through 

7). 

HOST INTERFACE CONNECTOR 

The host interface connector is a 50 pin vertical 
header. The connector pin-outs are as follows: 



SIGNAL GROUND 


SIGNAL PIN 


SIGNAL NAME 


DESCRIPTION 


1 


2 


DATA (LSB) 


Bi-directional bytewide bus bits D0-D7. 


3 


4 


DATA 1 




5 


6 


DATA 2 




7 


8 


DATA 3 




9 


10 


DATA 4 




11 


12 


DATA 5 




13 


14 


DATA 6 




15 


16 


DATA 7 (MSB) 




17 


18 


SPARE 




19 


20 


SPARE 




21 


22 


SPARE 




23 


24 


SPARE 




25 


26 


SPARE 




27 


28 


SPARE 




29 


30 


SPARE 




31 


32 


SPARE 




33 


34 


SPARE 




35 


36 


BUSY 


Controller-to-host signal whose falling edge 
acknowledges receipt of SEL and own address. 
Rising edge indicates transaction complete. 


37 


38 


ACK 


Host-to controller handshake for byte transfers (both 
edges used). 


39 
41 


40 
42 


RST 
MSG 


100 nsec low level initiate host-to controller. 


Controller-to-host MESSAGE signal to indicate type 








of bus transfer (see INFORMATION TRANSFER 








PHASE). 


43 


44 


SEL 


Host-to-controller low level signal gives control of bus 
to the addressed target. 


45 


46 


C/D 


Controller-to-host COMMAND/DATA signal used 
to indicate type of bus transfer (see INFORMATION 








TRANSFER PHASE). 


47 


48 


REQ 


Controller-to-host handshake for byte transfers (both 
edges used). 


49 


50 


I/O 


= Input to host. 

1 = Output from host. 

(see INFOMATION TRANSFER PHASE) 



WINCHESTER DRIVE CONTROL CONNECTOR 

The drive control connector is a 34-pin PC card edge 
connector that provides a low speed bus that is daisy 
chained to each of the Winchster drives in the system. 
To properly terminate the open collector outputs from 
the WD1002-SHD, the last drive in the daisy chain 



should have a 220/330 ohm line termination resistor 
pack installed. No other drives should have this ter- 
mination. The drive control signals and pinouts are 
as follows: 



6-22 



Winchester Board Products 







SIGNAL NAME 




SIGNAL GROUND 


SIGNAL PIN 


I/O 


DESCRIPTION 


1 


2 


RWC (0) 


When the Reduce Write Current (RWC) line is acti- 
vated by Write Gate (WG), a lower write current is 
used to comoensate for a areater bit packina den- 
sity on the inner cylinders. RWC is only valid 
when WG is low. 


3 


4 


HS2 (0) 


Head Select lines are used by the WD1002-SHD to 


13 


14 


HSO (0) 


select a specific R/W head on the drive. 


17 


18 


HS1 (0) 




5 


6 


WG (0) 


Write Gate (WG) enables data to be written on the 
disk. Special circuitry has been included to ensure 
that this signal will not "glitch" at power-on. This 
enables the disk drive to remain powered while the 








WD1002-SHD power is being cycled. 


7 


8 


SC(I) 


Seek Complete (SC) informs the WD1002-SHD that 


9 


10 


^ 


the head of a selected drive has stabilized. 
Track 000 (TROOO) indicates that the R/W heads 


TROOO (1) 








are positioned on the outermost cylinder. 


11 


12 


WF(I) 


Write Fault (WF) informs the WD1002-SHD that 
some fault has been detected by the selected drive. 


15 


16 




NC 


19 


20 


IND (1) 


Index (IND) indicates the index point for synchroniza- 
tion during formatting. IND is also used as a time- 
out mechanism for retries. IND should pulse once 
for each disk rotation. 


21 


22 


RDY (!) 


Ready (RDY) informs the WD1002-SHD that the de- 
sired drive is selected and its motor is up to speed. 


23 


24 


STEP (0) 


STEP is pulsed for each desired step. The direction 
of the step is determined by the DIRIN line. 


25 


26 


DSO 


The Drive Select bits (DS0-DS1) are used to select 


27 


28 


DS1 


either drive 1 or drive 2. 


29 


30 




NC 


31 
33 


32 

34 




NC 


DIRIN 


Direction in (DIRIN) determines the direction 








of movement of the R/W heads when STEP is 








pulsed: 








DIRIN = 1 = direction out 








DIRIN = = direction in 



WINCHESTER DRIVE DATA CONNECTOR 

Two data connectors are provided for data transfer 
between the controller and each drive. All lines 
associated with the transfer of data between the drive 
and the controller are differential in nature and may 



not be multiplexed. The data connectors are 20-pin 
vertical headers on tenth-inch centers. The cable 
pinouts are as follows: 



O 

o 
o 
ro 

0) 

X 
D 



Winchester Board Products 



6-23 



o 

o 
o 

in 

X 
D 



SIGNAL 


SIGNAL 


(I/O) 


SIGNAL NAME 


GROUND 


PIN 






2 


1 


1 


Drive Selected 


4 


3 


- 


NC 


6 


5 


- 


NC 


8 


7 


- 


NC 


10 


9, 


- 


NC 


12 


11 


- 


GND 




13 





+ MFM Write Data 




14 





-MFM Write Data 


16 


15 


- 


GND 




17 


1 


+ MFM READ 
DATA 




18 


1 


-MFM READ DATA 


20 


19 


- 


GND 



POWER CONNECTOR 

A four pin AMP connector is provided for power input 
to the board. The pinouts are as follows: 



PIN 


SIGNAL 


1 
2 
36 

4 


NC 

GROUND 

GROUND 

+ 5V regulated 



HOST INTERFACE DETAILED BUS OPERATION 

With regard to bus operations, time can be partitioned 
into the following mutually exclusive phases: 

1. Reset 

2. Bus Free 

3. Target Selection 

4. Information Transfer 

5. Bus Release 

Bus Phase Sequencing 

A Reset Phase may occur at any time. It is followed 
by the Bus Free Phase. In the absence of a Reset 
Phase, the bus alternates between the Bus Free 
Phase and one Transaction. 

A Transaction always consists of the following 
sequence: 



1. one Target Selection Phase 

2. one or more Information Transfer Phases 

3. one Bus Release Phase 

The five bus phases are described below. The Infor- 
mation Transfer Phase is broken down into its 
mutually exclusive categories, which are also called 
phases. 

1. RESET PHASE 



Defined as the time RESET is low. It is used by a 
Host to force the controller(s) on the bus to the same 
state as that following a power on condition. Power- 
on-Reset is 110msec. Master Reset from Host is 
lOO/iSec. 

2. BUS FREE PHASE 

Defined as the time between the Reset Phase or com- 
pletion (Bus Release Phase) of one Transaction and 
Initiation (Target Selection Phase) of the next Tran- 
saction. It can also be thought of as the time during 
which no unit has control of the bus. All eight con- 
trol lines are high. The Data Lines are in an undefined 
state. 

3. TARGET SELECTION PHASE 

This phase begins when the host places a target 
address on the bus. The Host then brings SEL 
low. The phase ends when the target corresponding 
to that address responds by b ringing BUSY low. 
Note: the Host must bring SEL high before comple- 
tion of the current Transaction (end of next Bus 
Release Phase). 

The target address consists of one of DO through 
D7 low and the other seven higJi^The controller's 
default address corresponds to DO low. It may be 
changed to any address by jumpering. Two controllers 
may not have the same address. 

4. INFORMATION TRANSFER PHASE 

This phase is used to transfer one or more bytes over 
the bus. It begiris when t he cu rrently selected con- 
troller sets I/O, C/D, and MSG to one of the five 
legal combinations in the following table. This 
indicates to the Host the type of byte transfer(s) which 
will follow. 



i/0 


C/D 


MSG 


TYPE OF TRANSFER PHASE 


NUMBER OF BYTES 


1 
1 








1 
1 





1 
1 

1 
1 



Command Block (from Host) 
Data Block (from Host) 
Data Block (to Host) 
Status Byte (to Host) 
Message Byte (to Host) 


6 
3, 8, 256, 260, 512 or 516 
1, 4, 256, 260, 512 or 516 

1 
1 



6-24 



Winchester Board Products 



For each byte transferred, the following operations 
must occur in sequence to perform the asynchronous 
handshake. 

1. The controller b rings REQ low 

2. The host brings ACK low 

3. The controller b rings REQ high 

4. The host brings ACK high 

For controller to host transfers, the eig ht bits are valid 
on the bus at least 125 nsec before REQ goes low. 
For host to controller transfers, they mu st be valid 
on the bus no later than 375 nsec after ACK goes 
low. Note: for debugging, it is useful to know that 
bytes are valid on the bus at the rising edge of REQ 
during any transfer. 

The Command Block Transfer Phase is used to send 
a block of parameters to the controller. This block 
specifies the operation to be performed (e.g. Format 
Disk). 

The Data Transfer Phase is primarily used to send 
one or more sectors of data (with or without ECC) in 
either direction. It is also used to send an extra block 
of parameters to the controller or to send byte(s) of 
controller operational information to the host. 

During the Status Transfer Phase, a byte is sent to 
the Host. They are encoded to indicate whether an 
error has been detected, and if so, which drive. 

During the Message Byte Transfer Phase, one byte 
of all zeroes is sent to the host. This is necessary to 
satisfy the protocol. 

BUS RELEASE PHASE 

This p hase is simply the low-to-high transition of 
BUSY. This event signifies to the host that the cur- 
rent Transaction has terminated and the associated 
target is no longer controlling the bus. 

SUMMARY 

Now in more detail, a transaction always consists of 
the following sequence: 

a. One Target Selection Phase 

b. One Command Block Transfer Phase 

c. Zero or more Data Block Transfer Phase(s) (type 
and number determined by the preceding Com- 
mand Block parameters) 

d. One Status Byte Transfer Phase 

e. One Message Byte Transfer Phase 

f. One Bus Release Phase 

During a transaction, all Data Block Transfer Phases 
are in the same direction and of the same size. 

COMMAND BLOCKS 

A transaction is initiated by the host to instruct the 
controller to execute a command. During the Com- 
mand Block Transfer Phase, six bytes of information 
specifying the command are transferred to the con- 
troller. There is a specific fomat for these bytes, 



shown in figure below. 



BITS 


BYTE 


7 


6 


5 


4 


3 


2 


1 








Command Class 


OP Code 


1 


Logical Unit 
Number 


Logical Sector Address 
(high) 


2 

3 
4 
5 


Logical Sector Address (Middle) 
Logical Sector Address (Low) 
Interleave or Block Count 
Control Byte 



Byte is transferred first. Byte must be specified 
for all commands. Each command has exactly one 
Byte value associated with it. 

Depending on the value of Byte 0, each parameter 
in Bytes 1 through 5 may require specification. Table 
2 specifies the supported commands and their 
parameters. It also includes information in data 
transfers required during execution. All other com- 
mands are reserved. 

LOGICAL UNIT NUMBER (LUN) 

This is contained in the upper three bits of Byte 1. 
The allowed values are 0,1. The designators in the 
Command Table are: 

Drive (LUN 0) or 1 (LUN 1) 

LOGICAL SECTOR ADDRESS (L) 

This is a 21-bit field contained in Bytes 1, 2, and 3. 
It is computed from the Cylinder address (C), Head 
address (H), and Sector address (S), as well as the 
drive parameters, heads per drive (HD) and Sectors 
per track (ST): 

L - (((C*Hd) -f H) * ST) -f S 

C,H, and S can be derived from L, HD, and ST as follows: 

S = LModulo ST 

H - ((L-S)/ST) Modulo HD 

C = (((L-S)/ST)-H)/HD 

This field specifies a sector (or a beginning sector) for 
the Read and Write Drive commands. It specifies a track 
for the Format and Seek commands (marked with a * 
In the table). When only a track specification is required, 
the sector number implied by the Logical Sector Address 
Is Ignored. 

INTERLEAVE OR BLOCK COUNT 

This field makes up Byte 4. The Interleave Ratio (I) 
is specified in the Five Format commands. The max- 
imum ratio is the sectors-per-track minus 1. 

The Block Count (B) is specified in the Read, Write, 
Read Long, and Write Long commands. It specifies 
the number of Logical Sectors to be transferred. 

Both Interleave Ratio and Block Count use all 8-bits 
to specify the parameters. 



O 

.A 
o 
o 

lO 

GO 

X 

o 



Winchester Board Products 



6-25 



Table 2. WD1002-SHD SUPPORTED COMMAND SUMMARY 



O 

o 
o 

lO 
CO 

I 
D 











INTER- 


CON- 










CLASS 




LOGICAL 


LEAVE OR 


TROL 


# OF SASI 


DATA 






+ 0P 




SECTOR 


BLOCK 


BYTE 


DATA BLOCK 


BLOCK 




COMMAND NAME 


CODE 


LUN 


ADDRESS 


COUNT 


OPTIONS 


TRANSFERS 


SIZE 


DIRECTION 


Test Drive Ready 


0,0 


W 


- 


- 


- 





- 


- 


Restore to track 


0,1 


W 


- 









- 


- 


Request Status 


0,3 


w 


- 




- 


1 


4 


To Host 


Format Drive 


0,4 


w 


L* 




R,P,S 





- 


- 


Checl< Track Format 


0,5 


w 


L* 




R,S 





- 


- 


Format Track 


0,6 


w 


L* 




R,P,S 





- 


- 


Format Bad Track 


0,7 


w 


L* 




R,P,S 





- 


- 


Read Drive 


0,8 


w 


L 


B 


R,A,S 


B 


Sector 


To Host 


Write Drive 


0,A 


w 


L 


B 


R,S 


B 


Sector 


To CTLR 


Seek 


0,B 


w 


L* 


- 


R,S 





- 


- 


Winchester 


















Parameters 


0,C 


w 


- 


- 


- 


1 


8 


To CTLR 


Return Burst Error 


















Length 


0,D 


w 


- 


- 


- 


1 


1 


To Host 


Format Alternate 


















Track 


0,E 


w 


L* 


1 


R,P,S 


1 


3 


To CTLR 


Write Sector Buffer 


0,F 


- 


- 


- 


- 


1 


Sector 


To CTLR 


Read Sector Buffer 


0,10 


- 


- 


- 


- 


1 


Sector 


To Host 


Perform RAM 


















Diagnostics 


7,0 


- 


- 


- 


- 





- 


- 


Perform Drive 


















Diagnostics 


7,3 


w 


- 


- 


R,S 





- 


- 


Perform Controller 


















Diagnostics 


7,4 




- 


- 


- 







- 


Read Drive Long 


7,5 


w 


L 


B 


R,S 


B 


Sector 

+ 4 


To Host 


Write Drive Long 


7,6 


w 


L 


B 


R,S 


B 


Sector 

+ 4 


To CTLR 



LEGEND 

W Winchester 

L* Logical sector Address used only to specify track 

I Interleave 

B Block count 

R Retry enable/disable 

A Attempt immediate error correction enable/disable 

S Stepping algorithm 

P Used with format commands for determining data field pattern 



6-26 



Winchester Board Products 



CONTROL BYTE 

This Byte is broken into the following fields: 



COMMAND STATUS BYTE 



FIELD 


BIT(s) 


FUNCTION 


S 

(STEP) 

u 
p 

(FORMAT) 

A 

(REREAD) 

R 

(RETRY) 


0-3 

4 
5 

6 
7 


Used in all commands which 
may cause a seek. Contains a 
code corresponding to a seek 
stepping algorithm. See Device 
Control Block (Fast Step 
Options). 

Reserved. Unused. 

Used in the format commands. 
If 0, fill data fields with hex 6C. 
If 1, fill with the pattern in the 
sector buffer. 

Used in the Read Drive com- 
mand with LUN indicating Win- 
chester. Normally 0. If 1, do not 
reread before attempting error 
correction. 

Used in all commands which 
will cause an ID field to be read. 
Normally 0. If 1, Disable retries. 



NOTE: 

If one or more of the above fields are required to be 
specified for a command, then all the other fields in 
that control byte must be set to zero. If none are 
required, all eight bits are interpreted as "don't cares." 

If retries are required then, a maximum of 8 are per- 
formed. If a Read problem still exists, a Reseek is 
issued and a maximum of eight more retries are 
performed. 

WD1002-SHD DEVICE CONTROL BLOCK 

FAST STEP OPTIONS 

The fast step option field contains an unsigned 3-bit 
integer. These Integers correspond to the following 
fast step algorithms: 



OPTION 







Default: 3msec/step 


1 


Half-step for Seagate drives 


2 


3 msec 


3 


Half-step for Tl drives 


4 


200 fisec/step. This is appropriate for buf- 




fered steps on drives made by Computer 




Memories Inc. and Rotating Memories 




Inc. 


5 


70 jjsec/step. 


6 


30 /isec/step. 


7 


15 fisec/step. 


8 


2 msec/step. 


9 


3 msec 


B-F 


Spare (3 msec) 



BITS 




O 








o 


1 

2 
3 


Error flag: -= no error 

1 -= error 




o 
o 


4 







5-7 


Logical unit number 





At the completion of execution of each command, 
a command status byte is sent by the WD1002-SHD 
to the host to indicate to the host whether or not the 
command was successful. 

The logical unit number returned is simply the con- 
tents of the logical unit field in the drive control block. 
For those commands that do not take a logical unit 
number as an input parameter, the logical unit 
number returned in the command status byte is not 
meaningful. 

COMMAND COMPLETION BYTE 

The command completion byte is an all zero byte sent 
by the WD1002-SHD to the host immediately follow- 
ing each command status byte. It indicates to the 
host that the Wd1002-SHD has freed the SASI bus. 

COMMANDS 

Each command is briefly described below. 
1. TEST DRIVE READY (CLASS 0, OPCODE 0) 



BYTE 




CONTENTS 





Bits 5-7 


= Command class 







Bits 0-4 


= Operation code 





1 


Bits 5-7 


= Logical unit number 






Bits 0-4 




don't care 


2 






don't care 


3 






don't care 


4 






don't care 


5 






don't care 



Possible Error Codes 

No error, no seek complete, drive not ready, write 
fault. 

Action 

Select the drive and determine whether or not it is 
ready. 

For a Winchester drive, read its status register and 
test the ready bit and busy bit. For Winchester drives 
supporting buffered seeks, this command is useful 
for determining the first drive to reach its target track. 



Winchester Board Products 



6-27 



2. RESTORE TO TRACK (CLASS 0, OPCODE 1) 



Error Byte 



O 

o 
o 

tn 

o 



BYTE 




CONTENTS 





Bits 5-7 = Command class 







Bits 0-4 = Operation code 


1 


1 


Bits 5-7 = Logical unit 






number Bits 0-4 


don't care 


2 




don't care 


2 




don't care 


4 




don't care 


5 


Control Field 
Bit 7 


don't care 




Bit 6 - Immediate ECC:0— no 







Immediate correction 






Bit 4 - Reserved for future 







use. Must be zero. 






Bit 5 - Format data 







Bits 0-3 


don't care 



Possible Error Codes 

No error, invalid command, Track not found, drive 
not ready, write fault. 

Action 

Position the heads to cylinder 0. 

3. REQUEST STATUS (CLASS 0, OPCODE 3) 



BYTE 




CONTENTS 





Bits 5-7 


= Command class 







Bits 0-4 


= Operation code 


3 


1 


Bits 5-7 


= Logical unit 








number Bits 0-4 


don't care 


2 






don't care 


3 






don't care 


4 






don't care 


5 






don't care 



Possible Error Codes 

No error, invalid command. 

Action 

Send the Host 4 bytes, the error byte and a 3-byte 
logical sector address for the specified drive. 

The following non-drive error codes are treated as 
drive errors: RAM failure (30.), ROM failure (31), ECC 
failure (32.). Hence, if command RAM diagnostic or 
command controller diagnostic detects an error, then 
status for drive should be requested. 



BITS 




7 


Logical sector address flag: 




= sector address not valid 




1 = sector address valid 


6 


Not used. Set to 


0-5 


Error codes 



Logical Sector Address 



BYTE 




1 

2 
3 


Bits 5-7 = Logical unit number 

Bits 0-4 = Logical sector address bits 

16-21 
Logical sector address bits 8-15 
Logical sector address bits 0-7 



If the most recent non-request-status command to the 
specified drive required a logical sector address, then 
the logical sector address flag is 1; else, it is 0. If the 
logical sector address flag is 0, then the logical sec- 
tor address is not meaningful. 

If there was an error on the immediately preceding 
command and the logical sector address flag is 1, 
then the logical sector address indicates the sector 
or track on which the error occured. If the command 
was a format type command, then the logical sector 
address indicates the track; else, it indicates the 
sector. 

If there was no error on the immediately preceding 
command and the command was a format type com- 
mand, then the logical sector address indicates the 
track one beyond the last track accessed. 

If there was no error and the command was not a for- 
mat type command, then the logical sector address 
indicates the last sector accessed. 

3A. ERROR CODES 

Disk Drive Error Codes 






No error 








1 

2 
3 


No index pulses 
No seek complete 
Write fault 








4 
6 


Drive not ready 
Track not found 








Controller Error Codes 








10/14 


Not used because WD1010 combines CRC 




with several other errors in 


an 


I.D. 


field as 




errors not found. 








11 


Uncorrectable data error 








12 


Address mark not found 








15 


Seek error 








18 


Error burst corrected 








19 


Bad track 









6-28 



Winchester Board Products 



1A Format error 

1C Illegal (direct) access to an alternate track 

1D Alternate track already used 

IE Alternate track not marked as alternate 

1F Alternate track equals bad track 

Command Error Codes 

20 Invalid command 

21 Invalid sector address 

Miscellaneous Error Codes 

30 RAM failure 

31 ROM failure 

32 EGG hardware failure 

SB. ERROR CODE DESCRIPTIONS 

No Seek Complete (2) 

This error code is only returned by the Test Drive 
Ready command when the target drive is a Win- 
chester that supports buffered seeks. It indicates the 
drive is busy doing a buffered seek. 

Write Fault (3) 

Indicates that there was write current to the head 
when the write gate was disabled. This is a very 
serious problem and should be fixed immediately. 

Track Not Found (6) 

This error code is only returned by the recalibrate 
command. It indicates that the track status from 
the drive did not become active after the maximum 
necessary steps towards cylinder 0. 

Uncorrectable Data Error (11) 

For a Winchester drive this error code indicates one 
or more error bursts in the data field were beyond the 
error correction code's ability to correct. The sector 
data for the sector in error is not sent to the Host. 

Address IVIark Not Found (12) 

Indicates that the header for the target sector was 
found, but its address mark was not detected. 

Error Burst Corrected (18) 

Indicates that the error correction code (EGG) was 
used to successfully correct an error. The corrected 
sector data is sent to the Host. This is the only error 
condition for which sector data is sent to the Host. 



Bad Track (19) 

This usually indicates access of a track that was for- 
matted as a bad track. However, there is a very small 
chance that it indicates that a track formatted as a 
bad track with alternate is so faulty that none of the 
multiple, duplicate pointers to the alternate track can 
be read. 

Format Error (1A) 

This error code is returned by the check track format 
command. It indicates that the track is not format- 
ted with the specified interleave factor, or at least one 
sector header is unreadable. 

This error code is returned by drive diagnostic to 
indicate that a bad-track-with-alternate does not con- 
tain a valid pointer to the alternate track. 

Altemate Track Already Used (1 D) 

This error code is only returned by the format alter- 
nate track command. It indicates that the specified 
alternate track is already an alternate or bad track. 

Altemate Track Not IVIarked as an Altemate (IE) 

This error code indicates that access of a bad-track 
with-alternate caused access to an alternate track 
which was not marked as an alternate track. 

Altemate Track Equals Bad Track (1 F) 

This error code is only returned by the format alter- 
nate track command. It indicates that the same track 
was specified as the bad track and the alternate track. 

Invalid Command (20) 

This error code indicates that the command class, 
command code, interleave factor, or fast step number 
were invalid. 

RAIVI Failure (31) 

This error code indicates one of the following condi- 
tions: (1) The program memory RAM checksum does 
not match the calculated checksum. (2) The RAM in 
the microprocessor failed. (3) The microprocessor 
GPU failed. 

ECC Hardware Failure (32) 

This error code indicates that the EGG Support Device 
failed during internal diagnostics. 



O 

o 
o 

lO 
I 

CO 

o 



Winchester Board Products 



6-29 



4. FORMAT DRIVE (CLASS 0, OPCODE 4) 



5. CHECK TRACK FORMAT (Continued) 



D 

o 
o 
ro 

(>> 

X 
D 



BYTE 




CONTENTS 





Bits 5-7 = Command class 







Bits 0-4 = Operation code 


4 


1 


Bits 5-7 = Logical unit number 
Bits 0-4 = Logical sector 

address bits 16-21 




2 


Logical sector address bits 8-15 




3 


Logical sector address bits 0-7 




4 


Interleave factor 




5 


Control field 

Bit 7 - Retry disable: 

= no disable 

1 = disable 

Bit 6 - Immediate ECC: 






= no immediate correction 







Bit 5 - Format Data: 






= Hex 6C 






1 = contents of sector buffer 






Bit 4 - Reserved for future use. 






Must be zero. 







Bits 0-3 = Fast step option 






integer 





Possible Error Codes 

No error, invalid command, invalid sector address, 
drive not ready, seek error, write fault. 

Action 

Format from the specified tracl< to the end of the disk. 
The previous contents of the formatted tracks are 
ignored. 

5. CHECK TRACK FORMAT (CLASS 0, OPCODE 5) 



BYTE 




CONTENTS 





Bits 5-7 = Command class 







Bits 0-4 = Operation code 


5 


1 


Bits 5-7 = Logical unit number 
Bits 0-4 = Logical sector 

address bits 16-21 




2 


Logical sector address bits 8-15 




3 


Logical sector address bits 0-7 




4 


Interleave factor 




5 


Control field 

Bit 7 - Retry disable: 

= no disable 

1 = disable 

Bit 6 Immediate ECC: 






= no immediate correction 






BYTE 




CONTENTS 




Bit 5 ■ Format data 







Bit 4 - Reserved for future 






use. Must be zero. 







Bits 0-3 = Fast step option 






Integer 





Possible Error Codes 

No error, invalid command, invalid sector address, 
seek error, format error, drive not ready, write fault. 

Action 

Verify that the specified track is formatted with the 
specified interleave factor. Do not read the sector data 
fields. 

6. FORMAT TRACK (CLASS 0, OPCODE 6) 



BYTE 




CONTENTS 





Bits 5-7 = Command class 







Bits 0-4 = Operation code 


6 


1 


Bits 5-7 = Logical unit number 
Bits 0-4 = Logical sector 

address bits 16-21 




2 


Logical sector address bits 8-15 




3 


Logical sector address bits 0-7 




4 


Interleave factor 




5 


Control field 

Bit 7 - Retry disable: 

= no disable 

1 = disable 

Bit 6 - Immediate ECC: 






= no immediate correction 







Bit 5 - Format data: 






= Hex 60 






1 = contents of sector buffer 






Bit 4 - Reserved for future use. 






Must be zero 







Bits 0-3 = Fast step option 






Integer 





Possible Error Codes 

No error, invalid command, invalid sector address, 
drive not ready, seek, error, write fault. 

Action 

Format the specified track. The current contents of 
the specified track are ignored. 



6-30 



Winchester Board Products 



WESTERN DIGITAL 

CORPORATION 

WD1002-SAS Winchester/Floppy Disk Controller 



FEATURES 

• XSASI 8-BIT BI-DIRECTIONAL BUS HOST 
INTERFACE 

• CONTROLS UP TO 2 WINCHESTER DRIVES (UP 
TO 8 RA/V HEADS EACH) 

• CONTROLS UP TO 2 FLOPPY DRIVES (DOUBLE- 
SIDED, DOUBLE DENSITY, SA450) 

• USER-SELECTABLE 5 1/4" WINCHESTER AND 
FLOPPY OPERATION 

• 32-BIT ECC FOR WINCHESTER DATA ERROR 
DETECTION AND CORRECTION 

• DIAGNOSTIC READS AND WRITES FOR CHECK- 
ING ERROR CORRECTION 

• BAD TRACK MAPPING CAPABILITY FOR 
WINCHESTER 

• AUTOMATIC FORMATTING 

DESCRIPTION 

The WD1002-SAS is a stand-alone, general-purpose 
Winchester and Floppy Controller Board designed to 
interface up to two Winchester disk drives and up to 
two Floppy disk drives to a Host Processor.The Win- 
chester drive signals are based on the Floppy look- 
alike interface available on the Seagate Technology 
ST506 and other compatible drives. All necessary 
receivers and drivers are included on the board, allow- 
ing direct connection to the drive. 



256 OR 512 BYTES PER SECTOR FOR 
WINCHESTER 

PROGRAMMABLE SECTOR SIZES 
(128,256,512,1024 BYTES) FOR FLOPPY 

PROGRAMMABLE INTERLEAVE CAPABILITY 
FOR WINCHESTER 

MULTIPLE SECTOR READS AND WRITES 

BUILT-IN DATA SEPARATOR 

BUILT-IN WRITE PRECOMPENSATION 

OVERU\PPED SEEK CAPABILITY ON BUFFERED 
STEP DRIVES 

SUPPORTS IMPLIED SEEKS ON ALL 
COMMANDS 

SINGLE + 5V POWER SUPPLY 



A separate computer access port enables com- 
munications between the Host Computer and Con- 
troller. This port conforms to XSASI and consists of 
an 8-bit bi-directional bus and appropriate control 
signals. All data to be written to or read from the disk, 
status information, and command parameters are 
transferred via this bus. An on-board data buffer 
allows bus transfers to be executed independently 
of the drive's data transfer. 

The WD1002-SAS is based on a proprietary chip set 
consisting of the WD1010-05, WD1770, WD11C00-13, 
and WD1015-06 designed specifically for Winchester 
and Floppy control. 



O 

o 
o 

lO 
GO 

> 



Winchester Board Products 



6-31 



o 
o 
ro 

00 

> 
C/) 



ARCHITECTURE 

The WD1002-SAS consists of six on-board interface 
connectors: 

• Power Connector (P1) 

• Host interface connector (J1) 

• Winchester drive control connector (P2) 

• Two Winchester data cable connectors (J2,J3) 

• Floppy control and data connector (J4) 

The J5 connector is used for test only. The 
WD1002-SAS architecture is illustrated in Figure 1. 



The WD1002-SAS accommodates up to two Win- 
chester and up to two Floppy drives. The Winchester 
drive control cable is daisy-chained to each of two 
drives, and the drive data connectors, which carry dif- 
ferential signals, are radially connected. The drive con- 
trol and data connector is daisy-chained to each of 
two drives. Table 1 defines the WD1002-SAS connec- 
tors and a source for the mating connectors on the 
associated cables. 



TABLE 1. WD1002-SAS INTERFACE CONNECTORS 







EQUIVALENT 


CONNECTOR 


INTERFACE FUNCTION 


MATING CONNECTOR 


P1 


Power 


AMP1-480424-0 (Housing) 
AIVIP350078-4 (Pins) 


J1 


Host Interface 
(XSASI Bus) 


AIVIP88379-8 


P2 


Winchester Control 


AMP88373-3 




(Daisy-chained) 


.^, 


J2,J3 


Winchester Data 
(Radially connected) 


AMP88377-4 


J4 


Floppy Control and Data 
(Daisy-chained) 


AMP88379-6 


J5 


Test (Do not use) 








HOST 

INTERFACE 

LOGIC 



! 



^ 






r 



CTOR ^— 
, I BUFFER ^y- 



:> 



■LZ. 



5 



WD101506 

BUFFER 

MANAGER 

CONTROL 

PROCESSOR 



WD11C0O-1 

SUPPORT 
DEVICE 



f 



w///////////////^/////////7y??^(d 



7> 



WD 1010-05 
WINCHESTER 
DRIVE 
CONTROLLER 



DATA 

SEPARATOR/ 
WRITE 
PRECOMP 



WINCHESTER 
DISK DRIVE 
BUFFER 
INTERFACE 



DSEL0.DSEL1(2), 



IS 






CLOCK 
GENERATOR 


8 MHZ 


5 MHZ 





j=^^ 



-». V^WINCHESTER DISK 
^ y^DRIVEI/O 





FLOPPY DISK 
DRIVE BUFFER 
INTERFACE 


,RD 








tHoo 


WD 1770 
FLOPPY DRIVE 

CONTROLLER 




INDEX 


^ WPST 


SS 












STEP 


3 


DiHiN 


' 




Wt5 






MO : 




wB 








BUS 


bSSLO, CSEl 


(51, 





y 



FIGURE 1. WD1002-SAS FUNCTIONAL BLOCK DIAGRAM 



6-32 



Winchester Board Products 



SPECIFICATIONS 

HOST INTERFACE 



Type 


XSASI 




o 


Cable length (Daisy-chained) 


15 ft (4.6 m) max. 




o 


Termination 


Socketed 220/330 ohm resistor pack 


to 


Addressing 


Jumper selectable (0 to 7) 




g 


DRIVE INTERFACES 


WINCHESTER 


FLOPPY 


CO 


Encoding method 


MFM 






Cylinders per drive 


Programmable up to 1024 


MFM 




Bytes per sector 


Programmable 256 or 512 


Programmable up to 245 
Programmable (128, 256, 512, 
or 1024) 




Sectors per tracl< 


17, 32 for 256, 512 bytes/sector, 


26, 16, 9, 5 for 128, 256, 512, 






respectively 


1024 bytes/sector, respectively 




Heads 


8 


2 




Drives 


2 


2 




Stepping rates/algorithm 


Programmable 


Programmable 




Data transfer rate 


5 Mbps 


250 Kbps 




Write precompensation time 


12 nsec 


125 nsec 




Sectoring 


Soft 


Soft 




CRC polynomial 


Xi6 + x^2 + X^ + 1 






ECC polynomial 


X32 + X28 + X26 + X19 + 

X17 + xio + X6 + X2 + 1 






Reciprocal ECC polynomial 


X32 + x30 + X26 + X22 + 
X^s + xi3 + x6 + X'* + 1 






Drive cable length: 








Control (Daisy-chained) 


10 ft (3 m) max. 


10 ft (3 m) max. for control and 
data combined 




Data (Radially connected) 


10 ft (3 m) max. 






DATA SEPARATOR 








Aquisition Time 


<6.4^sec. 






Capture Range 


±5% 






Bit Jitter Tolerance 


±36 nsec. 






Asymmetry Tolerance 


20 nsec. as measured over constant RCLK pattern. 




fo Stability 


<2% 






POWER 








Voltage 


+ 5V ±5% 






Current 


2.0 amps max., 1.5 amps typ. 






Ripple 


0.1V max. 






DIMENSIONS 








Length 


8 inches (20.3 cm) 






Width 


5.75 inches (14.6 cm) 






Heigt (max. including board, 








components, & leads) 


0.75 inches (1.9 cm) 






ENVIRONMENTAL 








Ambient temperature 


0°C (32°F) to 55°C (131°F) 






Relative humidity 


10% to 90% non-condensing 






Altitude 


to 10,000 ft (3048 m) 






Air Flow 


100 linear ft/min. at 0.5 inches (0.13 cm) from component 




MTBF 


surfaces 






MTTR 


10,000 POH 
30 minutes 







Winchester Board Products 



6-33 



o 

o 
o 
ro 

> 

CO 



HOST INTERFACE 

The WD1002-SAS Controller interfaces to the XSASI 
bus. Interfacing is acconnplished through the J1 con- 
nector, connecting up to eight XSASI-connpatible 
devices. The controller is shipped fronn the factory 
already configured to respond to device address 0. 
This preset address may be changed to any address 
from through 7 by jumpering via the resistor pack 
at location RN2. 



HOST INTERFACE CONNECTOR 
The Host interface connector (J1) is a 50-pin vertical 
header. Table 2 provides the connector pin descrip- 
tion and its bus signals. The cable terminating 
220/330 ohm resistor pack is socketed onto the con- 
troller to provide flexibility in daisy-chaining the bus 
devices. 



TABLE 2. HOST INTERFACE CONNECTOR (J1) PIN DESCRIPTION 



SIG. 
GND 


SIG. 
PIN 


SIGNAL 
MNEMONIC 


SIGNAL NAME 


I/O* 


FUNCTION 


1 

3 

5 

7 

9 
11 
13 
15 

17 

thru 

34 

35 

37 
39 

41 

43 

45 
47 
49 


2 

4 
6 
8 
10 
12 
14 
16 

36 

38 
40 

42 

44 

46 
48 
50 


DO 
thru 
07 

BSY 

ACK 

RST 

MSG 

SEL 

C/D 
REQ 
I/O 




I/O 


1 
1 



1 






An 8-bit bi-directional bus used to transfer 
commands, status, and data. 

Indicates to the Host that the WD1002-SAS is 
busy executing a command and is unable to 
accept another command. When BSY is ass- 
erted, it acknowledges receipt of SEL and its 
own address. De-asserting indicates transaction 
is completed. 

Indicates to the controller that the Host has 
accepted the byte for data transfer. 

When asserted, RST places the WD1002-SAS 
into its initial power-up state. When asserted for 
>100 nsec, RST initializes the controller. 

Used with I/O, C/D, and REQ to indicate type 
of transfer. For example, during the Message 
Byte Transfer Phase, one byte of zeros is sent 
to the Host to indicate the command is 
complete. 

An asserted signal gives control of the bus to 
the address (0 through 7) which is selected by 
jumpering at location RN2. 

Used with I/O, MSG, and REQ to indicate type 
of transfer. 

Indicates to the Host that the controller is ready 
for data transfer. 

Identifies the direction of tjansfers between 
the Host and WD1002-SAS. 1 asserted = input 
to Host; asserted = output to controller. 


DATAO 
thru 
DATA 7 

NOT 
CONNECTED 


BUSY 


ACKNOWLEDGE 


RESET 


MESSAGE 


SELECT 


CONTROL/DATA 


REQUEST 


INPUT/OUTPUT 



'The I/O column is in relation to the WD1002-SAS and not the Host. 



HOST INTERFACE BUS OPERATION 

The timing sequence for bus operations includes 
five phases: 



1 . Reset Phase. Occurs when RESET is asserted. 
Used by the Host to force the controller(s) 
on the bus to the same state it was in following 
a power on condition. 



6-34 



Winchester Board Products 



2. Bus Free Phase. Occurs between the completion 
of one transaction (Bus Release Phase) and 
the initiation of the next transaction (Target 
Selection Phase). Also occurs during the time 
in which no unit has control of the bus. All 
eight control lines and eight data lines are 
de-asserted. 

3. Target Selection Phase. Occurs when the Host 
plac es a target address on the bus and asserts 
SEL. and the addressed co ntrol ler asserts 
BSY. The Host then de-asserts SEL before com- 
pleting the phase. 

The target address consists of one asserted and 
seven de-asserted DO through D7 signals. The 
controller's default address of O corresponds to 
an asserted DO, which may be changed to any 
address by jumpering. Two controllers may not 
use the same address. 

4. Information Transfer Phase. Used to transfer one 
or more bytes on th_e bu^. The ty pe of transfer is 
determined by the I/O, C/D, and MSG signal 
codes on the lines (providing five valid 
combinations) as shown in Table 3, and as 
qualified by request. A valid combination in- 
dicates to the Host the types of byte transfers that 
are to follow. 

The following are used to transfer information: 

• Command Block Transfer Phase. Used to send a 
block of command bytes from the Host to the con- 
troller, specifying the operation to be performed 
(e.g. Format Disk). 

• Data Block Transfer Phase. Used primarily to send 
one or more sectors of data either from or to the 
Host. Also used to send a block of parameters to 
the controller or to the Host. 

• Status Byte Transfer Phase. During this phase, one 
byte is sent to the Host indicating the status of 
the operation. 

• Message Byte Transfer Phase. One byte of zeros is 
sent to the Host to indicate the command is 
complete. 

For each byte transferred, the following operations 
occur in sequence to perform the asynchronous 
handshake: 



• Controller asserts REG 

• Host asserts ACK 

• Controller de-asserts REQ 

• Host de-asserts ACK 

For controller-to-Host transfers, the eight bits 
are valid on the bus at least 100 nsec before REQ 
is asserted. Host-to-controller transfers are 
valid on the bus no later than 250 nsec after ACK 
is as serte d. It is recommended that before asser- 
ting ACK, make sure the data is valid. (Note : For 
debugging, bytes are valid on the bus when REQ 
is de-asserted during any transfer.) 

5. Bus Release Phase. Occurs when BSY is de- 
asserted. This phase signals the Host that the cur- 
rent transaction has terminated and the 
associated selected target is no longer controll- 
ing the bus. 

BUS PHASE SEQUENCING 

A Reset Phase may occur any time and is followed 
by the Bus Free Phase. In the absence of a Reset 
Phase, the bus alternates between the Bus Free 
Phase and one transaction. A transaction always con- 
sists of the following: 

1. One Target Selection Phase 

2. One Command Block Transfer Phase 

3. Zero or more Data Block Transfer Phase(s) - Type 
and number determined by the preceding Com- 
mand Block Transfer Phase 

4. One Status Byte Transfer Phase 

5. One Message Byte Transfer Phase 

6. One Bus Release Phase 

During a transaction, all Data Block Transfer Phases 
are the same size and are sent in the same direction. 

DRIVE INTERFACES 

WINCHESTER DRIVE CONTROL CONNECTOR 

The Winchester drive control connector, a 34 pin 
printed circuit card edge connector, is a low- speed 
bus daisy-chained to each Winchester drive in the 
system. To terminate the control signals on the 
WD1002-SAS properly, the last drive in the daisy-chain 
must have a 220/330 ohm resistor pack installed. The 
pin description and control signals are provided in 
Table 4. 



O 

o 
o 

lO 
CO 

> 



TABLE 3. INFORMATION TRANSFER PHASE 



SIGNAL MNEMONIC 


TRANSFER TYPE 


NUMBER OF BYTES 


I/O C/D MSG 


1 1 
1 1 1 
1 1 
1 



Command Block 
Data Out Block 
Data In Block 
Status Byte 
Message Byte 


6 
3, 8, 128, 256, 260, 512, 516, or 1024 
1, 4, 128, 256, 260, 512, 516, or 1024 

1 

1 



Winchester Board Products 



6-35 



TABLE 4. WINCHESTER DRIVE CONTROL CONNECTOR (P2) PIN DESCRIPTION 



SIG. 
GND 


SIG. 
PIN 


SIGNAL 
MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


1 
3 

5 

7 
9 
11 

13 


2 

4 

6 

8 
10 
12 

14 











1 
1 
1 






RWC 
HS2 

WG 
SC 


REDUCE WRITE 
CURRENT 


RWC is asserted when the cylinder specified 
by the Set Parameters Comnnand is reached. 

HS2 is one of three Head Select signals 
decoded by the drive to select one of eight RA/V 
heads. 

WG is asserted when valid data is to be written 
on disk. WD1002-SAS de-asserts this signal when 
a WF is detected. Special circuitry is included 
to ensure the output does not glitch during power 
on. 

SC informs the WD1002-SAS the head of a 
selected drive reached the desired cylinder and 
has stabilized. 

The drive asserts this signal when the RAA/ heads 
are positioned over the outermost cylinder, 
cylinder 0. 

WF is asserted by the selected drive when a 
write error occurs. The command in progress 
aborts and no other disk command can be exe- 
cuted while this signal is asserted. 

HSO is one of three Head Select signals 
decoded by the drive to select one of eight RA/V 
heads. 


HEAD SELECT 2 


WRITE GATE 


SEEK COMPLETE 


TKOOO 

WF 

HSO 


TRACK 000 


WRITE FAULT 


HEAD SELECT 


15 
17 

19 

21 
23 

25 
27 


16 
18 

20 

22 

24 

26 
28 


HS1 


NOT CONNECTED 




1 
1 







HS1 is one of three Head Select signals 
decoded by the drive to select one of eight RA/V 
heads. 

This signal indicates the start of a track. It is 
used as a synchronization point during for- 
matting and as a time-out mechanism for 
retries. This signal pulses once for each disk 
revolution. 

Informs the controller that the drive motor is up 
to speed. 


HEAD SELECT 1 


INDEX 


INDEX PULSE 


DRDY 


DRIVE READY 


STEP 


STEP PULSE 


STEP, together with DIRIN, positions the heads 


to the desired cylinder. STEP pulses once for 
each step. DIRIN determines the step direction. 


DSELO 


DRIVE SELECT 


DSELO is used to select drive 0. 


DSEL1 


DRIVE SELECT 1 


DSEL1 is used to select drive 1. 


29 

thru 

32 

33 


34 




NOT CONNECTED 







DIRIN 


DIRECTION IN 


DIRIN determines the direction the RA/V heads 
take when the step line is pulsed. De-asserted 
= out; asserted = in. 



6-36 



Winchester Board Products 



TABLE 5. 
WINCHESTER DRIVE DATA CONNECTOR 



WINCHESTER DRIVE DATA CONNECTORS 

Connectors J2 and J3 allow data transfer between 
the controller and each drive. The data lines are dif- 
ferential in nature and must be connected to each 
drive with its own cable, i.e., drive O to J2 and drive 
1 to J3. Each drive is radially connected with a max- 
imum cable length of 10 feet. Each data connector 
is a 20-pin vertical header on 0.1 inch center. Data 
connector pin descriptions and signals are given in 
Table 5. 

FLOPPY DRIVE CONTROL AND DATA CONNECTOR 

The Floppy drive control signals function in a man- 
ner similar to the Winchester except both the con- 
trol and data signals are transmitted on the same 
connector. The connector is daisy-chained to each 
drive. To properly terminate each TTL level output 
signal from the WD1002-SAS, the last drive in the 
daisy-chain must have line terminations installed as 
specified by the drive manufacturer. A flat ribbon 
cable, or twisted-pair, of less than 10 feet should be 
used. The connector is a 34-pin vertical header on 0.1 
inch center. Pin description and signals are given in 
Table 6. 



TABLE 6. FLOPPY DRIVE CONTROL AND DATA CONNECTOR {J4) PIN DESCRIPTION 



J2,J3 



SIG. 


SIG. 






GND 


PIN 


I/O 


SIGNAL NAME 




1 




NC 


2 






GND 




3 




NC 


4 






GND 




5 




NC 


6 






GND 




7 




NC 


8 






GND 




9 




NC 




10 




NC 


11 






GND 


12 






GND 




13 





+ MFM Write Data 




14 





-MFM Write Data 


15 






GND 


16 






GND 




17 


1 


+ MFM Read Data 




18 


1 


-MFM Read Data 


19 






GND 


20 






GND 



SIG. 
GND 


SIG. 
PIN 


SIGNAL 
MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


I th 
5 

7 

9 

II th 
15 

17 

19 

21 
23 


ru 4 
6 

8 

10 

ru 14 

16 

18 

20 

22 

24 




NOT CONNECTED 




1 














DSELO 


DRIVE SELECT 


DSELO is used to select drive 0. (Note: On an 
SA450, this is drive 4.) 

This signal indicates the start of a track. It is 
used as a synchronization point during for- 
matting and as a time-out mechanism for 
retries. This signal pulses once for each disk 
revolution. 


INDEX 


INDEX PULSE 


DSEL1 
MO 


DRIVE SELECT 1 
NOT CONNECTED 


DSEL1 is used to select drive 1. 

Directly controls the Floppy drive's power-on of 
the spindle motor. A 1-second delay occurs 
after the motor is on. 


MOTOR ON 


DIRIN 


DIRECTION IN 


DIRIN determines the direction the RAA/ heads 
take when the step line is pulsed. De-asserted 
= out; asserted - in. 


STEP 

WD 
WG 


STEP PULSE 


STEP, together with DIRIN, positions the heads 


to the desired cylinder. STEP pulses once for 


each step. DIRIN determines the step direction. 

Provides data to be written on the diskette and 
is enabled by WG asserted. 

WG is asserted when valid data is to be written 
on disk. It is used by the drive to enable the 
write current to the head. 


WRITE DATA 


WRITE GATE 



Winchester Board Products 



6-37 



TABLE 6. FLOPPY DRIVE CONTROL AND DATA CONNECTOR (J4) PIN DESCRIPTION (CONTINUED) 



O 

O 

o 
ro 

> 



SIG 
GND 


SIG 
PIN 


SIGNAL 
MNEMONIC 


SIGNAL NAME 


I/O 


DESCRIPTION 


25 
27 

29 
31 

33 


26 
28 

30 
32 

34 


TROO 


TRACK 00 


1 

1 

1 



The drive asserts this signal when the R/W 
heads are positioned over the outernnost cylinder. 
Indicates to the controller a write-protected 


WPRT 

RD 
SS 


WRITE PROTECT 


diskette is installed. When WPRT is asserted, 

no data is written to the diskette. 

Provides raw data (clock and data combined) 

as detected by the drive circuitry. 

SS determines the side of the diskette to be 

used. Asserted = select side 0; de-asserted = 

select side 1. 


READ DATA 


SIDE SELECT 
NOT CONNECTED 



POWER CONNECTOR 

A 4-pin amp connector P1 provides power input to the 
WD1002-SAS: 



SIG 


SIG. 




GND 


PIN 


SIGNAL NAME 




1 


NOT CONNECTED 


2 




GND 


3 




GND 




4 


-f 5V Regulated 



WD1002-SAS COMMAND BLOCK 

A transaction is initiated by the Host, instructing the 
controller to execute a command. During the Com- 
mand Block Transfer Phase, six bytes of information 
specifying the command are transferred to the con- 
troller. Figure 2 defines the contents of each byte in 
the Command Block. These parameters are sent to 
the WD1002-SAS by the Host to perform specific tran- 
sactions. 





BITS 1 


BYTE 


7 1 6 1 5 


4 1 3 1 2 1 1 1 





COMMAND 
CLASS 


OP CODE 


1 


LOGICAL 
UNIT NUMBER 


LOGICAL SECTOR 

ADDRESS 
(BITS 20 THRU 16) 


2 


LOGICAL SECTOR ADDRESS 
(BITS 15 THRU 8) 


3 


LOGICAL SECTOR ADDRESS 
(BITS 7 THRU 0) 


4 


INTERLEAVE OR BLOCK COUNT 


5 


CONTROL BYTE 



FIGURE 2. COMMAND BLOCK DESCRIPTION 



Command Class 

Designates whether the command is used in opera- 
tion (class 0) or for diagnostic (class 7). Command 
classes 1 through 6 are reserved for future use. 

OP Code 

An operation code is used in each command class 
to identify the function of the commands, e.g., read 
and write. 

Logical Unit Number 

There are 8 logical unit numbers. For example, logical 
unit numbers and 1, respectively. The Floppy logical 
unit numbers are 4 and 5. 

Logical Sector Address 

This address is a 21-bit unsigned integer specifying 
a unique physical sector. The following equation 
shows the one-to-one ratio between the set of logical 
sector addresses and the set of physical sectors: 

Logical Sector Address = (((Cylinder Number* 
Number of Heads) + Head Number)* Number of 
Sectors per Track) + Sector Number 

Each format command begins operation at the begin- 
ning of the track containing the specified sector. 

Interleave or Block Count 

The interleave factor is used by format commands. 
The 3:1 ratio is the minimum operational interleave; 
however, the disk also may be formatted at a 1:1 ratio. 
The maximum interleave is equal to the sectors-per- 
track minus one. Block count specifies the number 
of sectors to be used for each data transfer com- 
mand. The block count is an unsigned, no-zero 
integer. A block count of all zeros equals 256 sectors. 

Control Byte 

The descriptions and contents of the Control Byte for 
both the Winchester and Floppy drives are shown in 
Table 7. 



6-38 



Winchester Board Products 



TABLE 7. CONTROL BYTE DESCRIPTION 



BIT 


WINCHESTER CONTENTS 


FLOPPY CONTENTS 





Step Option. Unsigned 4-bit integers corres- 


Step Option. Unsigned 4-bit integers corres- 


thru 
3 
4 


ponding to stepping rates in Table 8. 


ponding to stepping rates in Table 8. 


Reserved for future use. Must be 0. 


MSB LSB 






Bit 5 Bit 4 Sector Size 






128 bytes/sector 






1 256 bytes/sector 






1 512 bytes/sector 






1 1 1024 bytes/sector 


5 


Format Data: 

= 6C Hex 

1 = Contents of Sector Buffer (Data is pro- 

vided by ttie Write Sector Buffer Com- 
mand) 




6 


Error Correction: 

- Correction After Tw/o Identical Syn- 

dromes 

1 = Correction After One Syndrome 


Not used. Must be 0. 


7 


Error Retry: 

= Enable Retry 

1 = Disable Retry 


Not used. Must be 0. 



TABLE 8. STEP OPTIONS 







FLOPPY 


OPTION 


WINCHESTER STEP RATE* 


STEP RATE 





3 msec per step** 


15 Msec 


1 


Half-step for Seagate ST506 (MLC2); fast step for Texas Instru- 
ments drives 


1 msec 


2 


3 msec per step 


2 msec 


3 


Half-step for Seagate ST506 (MLC2); fast-step for Texas Instru- 
ments drives 


3 msec 


4 


200 ^sec per step (appropriate for buffered-steps on drives manu- 
factured by Computer Memories Inc. and Rotating Memories Inc.) 


4 msec 


5 


70 f^sec per step 


5 msec 


6 


3 ^(sec per step 


6 msec 


7 


15 jjsec per step 


8 msec 


8 


2 msec per step for Olivetti-561 


10 msec 


9 


3 msec per step 


12 msec 


A 


3 msec per step 


14 msec 


B 


3 msec per step 


16 msec 


C 


3 msec per step 


18 msec 


D 


3 msec per step 


20 msec 


E 


3 msec per step 


25 msec 


F 


3 msec per step 


40 msec 



*For the Seek Command, buffered-seei<s(Options 4 through 7) do not wait for seek completion. All other seeks 

wait for seek completion. 

**This is the preferred 3 msec step rate. 



Winchester Board Products 



6-39 



o 
o 
ro 



COMMAND DESCRIPTIONS 

The WD1002-SAS commands are summarized in Table 9. Each command is listed with its Command Block 
contents. 

TABLE 9. SUMMARY OF COMMANDS 



COMMAND 


CLASS 


OP 
CODE 


LUN 
(W/F) 


ISA 


INT/BLK 


CONTROL BYTE | 


R 


C 


F 


MSB 
SS 


LSB 
SS 


STEP 


TEST DRIVE 
READY 





00 


V(W) 


n 


n 


n 


n 


n 


n 


n 


n 


RECALI- 
BRATE 





01 


V(W) 
V(F) 


n 
n 


n 
n 


V 
n 


V 
n 


n 
n 


n 
n 


n 
n 


V 
V 


REQUEST 
STATUS 





03 


V(W/F) 


n 


n 


n 


n 


n 


n 


n 


n 


FORMAT 
DRIVE 





04 


V(W) 


V* 


V(INT) 


V 


V 


V 


n 


n 


V 


CHECK TRACK 
FORMAT 





05 


V(W) 


V* 


V(INT) 


V 


V 


V 


n 


n 


V 


FORMAT 
TRACK 





06 


V(W) 
V(F) 


V* 
V* 


V(INT) 
V(INT) 


V 
n 


V 
n 


V 
n 


n 
V 


n 
V 


V 
V 


FORMAT BAD 
TRACK 





07 


V(W) 


V* 


V(INT) 


V 


V 


V 


n 


n 


V 


READ 
SECTOR 





08 


V(W) 
V(F) 


V 
V 


V(BLK) 
V(BLK) 


V 
n 


V 

n 


V 
n 


n 
V 


n 
V 


V 
V 


WRITE 
SECTOR 





OA 


V(W) 
V(F) 


V 
V 


V(BLK) 
V(BLK) 


V 
n 


V 

n 


V 
n 


n 
V 


n 
V 


V 
V 


SEEK 





OB 


V(W) 
V(F) 


V* 
V* 


n 
n 


V 

n 


V 
n 


V 
n 


n 
V 


n 
V 


V 
V 


SET 
PARAMETERS 





OC 


V(W/F) 


n 


n 


n 


n 


n 


n 


n 


n 


RETURN LAST 
CORRECTED 
BURST 
LENGTH 





CD 


V(W) 


n 


n 


n 


n 


n 


n 


n 


n 


FORMAT 

ALTERNATE 

TRACK 





OE 


V(W) 


V* 


V(INT) 


V 


V 


V 


n 


n 


V 


WRITE 

SECTOR 

BUFFER 





OF 


n(W) 


n 


n 


n 


n 


n 


n 


n 


n 


READ SECTOR 
BUFFER 





10 


n(W) 


n 


n 


n 


n 


n 


n 


n 


n 


RAM 
DIAGNOSTIC 


7 


00 


n(W/F) 


n 


n 


n 


n 


n 


n 


n 


n 


DRIVE 
DIAGNOSTIC 


7 


03 


V(W) 


n 


n 


V 


V 


V 


n 


n 


V 


CONTROLLER 
DIAGNOSTIC 


7 


04 


n(W/F) 


n 


n 


n 


n 


n 


n 


n 


n 


READ LONG 


7 


05 


V(W) 


V 


V(BLK) 


V 


V 


V 


n 


n 


V 


WRITE LONG 


7 


06 


V(W) 


V 


V(BLK) 


V 


V 


V 


n 


n 


V 



6-40 



Winchester Board Products 



LEGEND: 

V Must be a valid parameter 

n Not used (should be for future compati- 

bility). 

LUN(W/F) Logical Unit Number of Winchester drives 

INT Interleave factor. 

BLK Block Count. 

R Error Retry. Bit 7 of the Control Byte for Win- 

chester drives. 

C Error Correction. Bit 6 of the Control Byte 

for Winchester drives. 



F Format Dat6a. Bit 5 of the Control Byte for 

Winchester Drives. 

MSB SS Most Significant Bit Sector Size. Bit 5 of the 
Control Byte for Floppy drives. 

LSB SS Least Significant Bit Sector Size. Bit 4 of the 
Control Byte for Floppy drives. 

STEP Stepping Rate. Bits through 3 of the Con- 
trol Byte as defined in Table 8 for Win- 
chester and Floppy drives. 



O 

o 

o 
ro 

CO 

> 
C/) 



Each Wd1002-SAS command is described briefly 
in the following paragraphs. Refer to Table 9 for 
their parameter contents. 

1. TEST DRIVE READY (CLASS 0, OP CODE 00) 

This command reads the drive's status. For 
Winchester drives supporting buffered-seeks, this 
command is useful for determining the first drive 
to reach its selected track. 

This command is not used for the Floppy drives. 

Possible Error Codes 

GO No Error 

03 Write Fault 

04 Drive Not Ready 

08 Buffered-Seek in Progress 
32 Invalid Command 

2. RECALIBRATE (CLASS 0. OP CODE 01) 

This command positions the R/W heads over the 
outer most cylinder, cylinder 0. 

Possible Error Codes 

00 No Error 

03 Write Fault 

04 Drive Not Ready 
06 Track Not Found 
32 Invalid Command 

3. REQUEST STATUS (CLASS 0, OP CODE 03) 

This command sends the Host four status bytes of 
error information (as shown in Figure 3) for the 
specified drive. 





BITS 


BYTE 


7 


6 


5 1 4 1 3 1 2 1 1 1 





AVF 





ERROR CODE 


1 


LOGICAL LOGICAL SECTOR 
UNIT NUMBER ADDRESS 

(BITS 20 THRU 16) 


2 


LOGICAL SECTOR ADDRESS 
(BITS 15 THRU 8) 


3 


LOGICAL SECTOR ADDRESS 
(BITS 7 THRU 0) 



AVF 

Address valid flag. Indicates that the Logical Sector 
Address fields are valid. 

FIGURE 3. FOUR STATUS BYTES 

The information sent by the controller to the Host via 
the Request Status Command includes these 
conditions: 

% If the most recent non-Request-Status Command 
to the specified drive requires a logical sector 
address, then the address valid flag is 1. 

% If an error has occurred on the preceding com- 
mand and the address valid flag is 1, then the 
logical sector address indicates the record on 
which the error occurred. 

% If no error has occurred on the preceding com- 
mand to format the track, format the drive, or for- 
mat the alternate track, then the logical sector 
address indicates one track beyond the last track 
accessed. 

% If no error has occurred and the command is to 
check the track format, format the bad track, or 
is not a format command, then the logical sector 
address indicates the last track or sector 



Winchester Board Products 



6-41 



Possible Error Codes 



00 No Error 

32 Invalid Command 



The WD1002-SAS error code descriptions are sum- 
marized in Table 10. 



o 
o 
to 

I 

ifi 

> 
CO 



TABLE 10. ERROR CODE DESCRIPTIONS 



ERROR 
CODE 


ERROR NAME 


TYPE OF ERROR 


DESCRIPTION 


00 


No Error 


Disk Drive 


No error has occurred. 


03 


Write Fault 


Disk Drive 


Indicates write current occurred when WG is de- 
asserted, or a SC is not asserted and a drive is 
selected while WG is asserted. 


04 


Drive Not 
Ready 


Disk Drive 


The selected drive's DRDY is de-asserted. Indicates 
the motor of the selected drive is not up to speed. • 


06 


Track 
Not Found 


Disk Drive 


This code is returned bv the Recalibrate Command. 
Indicates the TKOGO or TROO from the selected 
drive was not asserted after the maximum number of 
steps (up to 1024 for the Winchester; up to 256 for 
the Floppy) toward cylinder 0. 


08 


Buffered-Seek 
in Progress 


Disk Drive 


This code is returned by the Test Drive Ready Com- 
mand, indicating the selected drive (Winchester sup- 
porting buffered-seeks) is busy performing a 
buffered-seek. 


10 


Write 
Protected 


Controller 


This code is returned by Floppy drives when write-pro- 
tect tab is detected on the diskette. 


11 


CRC Error 


Controller 


Indicates a CRC error in the data field is detected dur- 
ing a Floppy command execution after eight retries. 


12 


Address Mark 
Not found 


Controller 


This code is returned when address is not found during 
Floppy command execution after eight retries. 


17 


Uncorrectable 
Data Error 


Controller 


For a Floppy drive, this code indicates a CRC error in 
the data field. For a Winchester drive, this code indi- 
cates one or more error bursts in the data field are 
beyond the ECC's ability to correct. Data for the sec- 
tor in error is not sent to the Host. 


18 


Data 

Address Mark 
Not Found 


Controller 


This code is returned by Winchester drives. Indicates 
the selected sector's header is found, but its Address 
Mark is not detected. 


21 


Seek Error 


Controller 


Indicates the controller cannot locate the specified 
address on the disk. 


24 


Error Burst 
Corrected 


Controller 


A code returned by Winchester drives. Indicates the 
ECC successfully corrected an error. The corrected sec- 
tor data is sent to the Host (Note: This is the only error 
condition in which sector data is sent to the Host.) 


25 


Bad Track 


Controller 


Usually indicates access of a formatted bad track. Also 
indicates a formatted Bad-Track-With-Alternate is faulty 
and multiple, duplicate pointers to the Alternate Track 
cannot be read. 


26 


Format Error 


Controller 


This code is returned by the Check Track Format Com- 
mand. Indicates a track is not formatted, a track is not 
formatted with the specified interleave factor, or at least 
one sector header is unreadable. This code is also 
returned by the drive diagnostic, indicating a Bad-Track- 
With-Alternate does not contain a valid pointer to the 
Alternate Track. 


28 


Illegal (Direct) 
Access to an 
Alternate Track 


Controller 


The specified address is not a valid address for an 
Alternate Track. 



6-42 



Winchester Board Products 



TABLE 10. ERROR CODE DESCRIPTIONS (CONTINUED) 



ERROR 








CODE 


ERROR NAME 


TYPE OF ERROR 


DESCRIPTION 


29 


Alternate 


Controller 


This code is returned by the Format Alternate Track 




Track 




Command. Indicates the specified Alternate Track is 




Already Used 




already an alternate or bad track. 


30 


Alternate Track 


Controller 


Indicates access of a Bad-Track-With-Alternate caused 




Not Marked 




access to an Alternate Track not marked as an Alter- 




as Alternate 




nate Track. 


31 


Alternate 


Controller 


This code is returned by the Format Alternate Track 




Track Equals 




Command. Indicates the same track is specified as 




Bad Track 




the Bad Track and the Alternate Track. 


32 


Invalid 


Command 


Indicates an invalid command class, operation code, 




Command 




logical unit number, interleave factor, or step number. 


33 


Invalid 


Command 


Indicates the specified address has reached the file 




Sector Address 




device's given range, exceeding capacity. 


48 


RAM Failure 


Miscellaneous 


Indicates the external RAM failed. 


49 


ROM Failure 


Miscellaneous 


Indicates ROM checksum does not match the calcu- 
lated checksum. 



4. FORMAT DRIVE (CLASS 0, OP CODE 04) 

This command formats from the specified track to 
the end of the disk. The previous contents of the for- 
matted tracks are ignored. 

This command is not used for the Floppy drives. 

Possible Error Codes 

00 No Error 

03 Write Fault 

04 Drive Not Ready 
21 Seek Error 

32 Invalid Command 

33 Invalid Sector Address 

5. CHECK TRACK FORMAT (CLASS 0, OP CODE 05) 

This command verifies v^/hether the specified track 
is formatted vi/ith the specified interleave factor. It 
does not read the sector data fields. 

This command is not used for the Floppy drives. 

Possible Error Codes 

00 No Error 

03 Write Fault 

04 Drive Not Ready 
21 Seek Error 

26 Format Error 

32 Invalid Command 

33 Invalid Sector Address 

6. FORMAT TRACK (CLASS 0, OP CODE 06) 

This command formats the specified track, ignoring 
the current contents. For Floppy drives, 5E Hex is writ- 
ten in the data field. 

Possible Error Codes 

00 No Error 

03 Write Fault 

04 Drive Not Ready 



21 Seek Error 

32 Invalid Command 

33 Invalid Sector Address 

7. FORMAT BAD TRACK (CLASS 0, OP CODE 07) 

This command formats the specified track with a Bad 
Block Mark in each sector header, ignoring the 
previous contents. The contents of a bad track are 
not accessible. 

This command is not used for the Floppy drives. 
Possible Error Codes 

00 No Error 

03 Write Fault 

04 Drive Not Ready 

32 Invalid Command 

33 Invalid Sector Address 

8. READ SECTORS (CLASS 0, OP CODE 08) 

Beginning with the specified sector, this command 
reads the specified number of consecutive sectors. 

Possible Error Codes 

00 No Error 

03 Write Fault 

04 Drive Not Ready 
1 1 CRC Error 

1 2 Record Not Found 

1 7 Uncorrectable Data Error 

1 8 Address Mark Not Found 

21 Seek Error 

24 Error Burst Corrected 

25 Bad Track 

28 Illegal (Direct) Access to an Alternate Track 

30 Alternate Track Not Marked as Alternate 

32 Invalid Command 

33 Invalid Sector Address 



O 

o 

o 
ro 

00 

> 
if) 



Winchester Board Products 



6-43 



o 
o 
ro 

GO 

> 
C/) 



9. WRITE SECTORS (CLASS 0, OP CODE OA) 

Beginning with tlie specified sector, this command 
writes the specified number of consecutive sectors. 

Possible Error Codes 

00 No Error 

03 Write Fault 

04 Drive Not Ready 
1 Write-Protected 

1 2 Record Not Found 

1 8 Address Mark Not Found 

21 Seek Error 

25 Bad Track 

2 8 Illegal (Direct) Access to an Alternate Track 
30 Alternate Track Not Marked as Alternate 

32 Invalid Command 

33 Invalid Sector Address 

10. SEEK (CLASS O, OP CODE OB) 

This command moves the read/write head to the 
specified cylinder. It does not read any sector header 
to verify start or end position. 

Possible Error Codes 

00 No Error 

03 Write Fault 

04 Drive Not Ready 

32 Invalid Command 

33 Invalid Sector Address 

11. SET PARAIVIETERS (CLASS 0, OP CODE OC) 

For Winchester Drives, the following parameters are 
set to their respective default values upon power up 
or reset: 



BYTE 


DESCRIPTION 





Number of Cylinders MSByte 


1 


Number of Cylinders LSByte 


2 


Bits 4 thru 7 = Must be 




Bits thru 3 = Numbers of Heads 


3 


Start RWC Cylinder Number MSByte 


4 


Start RWC Cylinder Number LSByte 


5 


Start Write Precomp Cylinder Number 




MSByte 


6 


Start Write Precomp Cylinder Number 




LSByte , 


7 


Bits 4 thru 7 = Must be 




Bits thru 3 = Maximum Length of 




Error Burst To Be 




Corrected 



For Floppy Drives, power up or reset sets the 
parameters to the following defaults: 





DEFAULT 


PARAMETER 


VALUE 


Number of Cylinders 


40 


Number of Heads 


2 


Tracks Per Inch Flag for 96 tpi 





Diskette 





Floppy Parameter Block 

The parameters sent by the Host to the WD1002-SAS 
in the following format replace the default values 
shown above: 



PARAMETER 


DEFAULT 
VALUE 


Number of Cylinders 

Number of Heads 

Starting RWC Cylinder: The specified 
number for this parameter is rounded 
down to the nearest integer in multi- 
ples of four. For example, 0,4,8,12,. . . 
,1020. 

Starting Write Precomp Cylinder 

Maximum Length of Error Burst To 
Be Corrected: For most applications, 
the maximum length of error burst 
to be corrected should be approxi- 
mately 5 because correcting longer 
bursts increases the chance of 
miscorrecting. 


153 

4 

128 

64 
11 



Winchester Parameter Block 

The parameters sent by the Host to the WD1002-SAS 
in the following format replace the default values 
shown above: 



BYTE 


DESCRIPTION 





Number of Cylinders MSByte 




1 


Number of Cylinders LSByte 




2 


Bits 4 thru 7 = Must be 

Bits thru 3 = Number of Heads 




3 


If 48 or 96 Tracks Per Inch diskette is 






used in a drive with the same TPI = 







If 48 Tracks Per Inch diskette is used 


in 




a 96 TPI drive = 1 




4 


Zeros 




5 


Zeros 




6 


Zeros 




7 


Zeros 





Possible Error Codes 



00 
32 



No Error 

Invalid Command 



6-44 



Winchester Board Products 



12. RETURN LAST CORRECTED BURST LENGTH 
(CLASS 0, OP CODE OD) 

This command sends the Host one byte of data con- 
taining the length of the most recently corrected error 
burst. If no error burst has been corrected since the 
last power-up or reset, then Error Burst Length Block 
of zero is sent to the Host. 

This command is not used for the Floppy drives. 

Possible Error Codes 

00 No Error 

13 FORMAT ALTERNATE TRACK (CLASS O, OP 
CODE OE) 

This command formats the specified track as a Bad- 
Track-With-Alternate. Then it formats the specified 
Alternate Track with the specified interleave factor. 
The alternate Track is specified by the Host by sen- 
ding the following Alternate Sector Address Block to 
the WD1002-SAS after the device Control Byte : 



15. READ SECTOR BUFFER (CLASS O, OP CODE 10) 

This command sends current contents of the 
WD1002- SAS Sector Buffer the Host. The Host 
accepts as many bytes as there are in a sector on 
Logical Unit 0. 

This command is not used for the Floppy drives. 

Possible Error Codes 

00 No Error 

16. RAM DIAGNOSTIC (CLASS 7,0P CODE 00) 

This command writes and reads various patterns into 
the Sector Buffer to test. This command also destroys 
the previous contents of the Sector Buffer. 

Possible Error Codes 



00 
48 



no Error 
RAM Failure 





BITS 


BYTE 


7 1 6 1 5 


4 1 3 1 2 1 1 1 








LOGICAL SECTOR 

ADDRESS 
(BITS 20 THRU 16) 


1 


LOGICAL SECTOR ADDRESS 
(BITS 15 THRU 8) 


2 


LOGICAL SECTOR ADDRESS 
(BITS 7 THRU 0) 



This command is not used for the Floppy drives. 
Possible Error Codes 



17. DRIVE DIAGNOSTIC (CLASS 7,0P CODE 03) 

This command recalibrates the selected drive, then 
scans the ID on each track. This command does not 
write to the disk or send any sector data to the Host. 

The drive diagnostic is used to verify that at least one 
sector header can be read on each track. When a 
track formatted as bad Track, Bad-Track- With- 
Alternate, or Alternate Track Is encountered, an error 
is not reported. However, an error is reported when 
a Bad-Track-Wlth-Alternate is encountered with the 
Alternate Track Not Marked as an Alternate. If no 
pointer to the Alternate Track can be read from a Bad- 
Track-With-Alternate then a Bad Track error is 
reported. 

This command is not used for the Floppy drives. 



00 


No Error 


Possible 


i Error Codes 


03 


Write Fault 


00 


No Error 


04 


Drive Not Ready 


03 


Write Fault 


21 


Seek Error 


04 


Drive Not Ready 


29 


Alternate Track Already Used 


21 


Seek Error 


31 


Alternate Track Equals Bad Track 


25 


Bad Track 


32 


Invalid Command 


30 


Alternate Track Not Marked as Alternate 


33 


Invalid Sector Address 


32 


Invalid Command 



14. WRITE SECTOR BUFFER (CLASS 0,0P CODE OF) 

This command writes data from the Host to the 
WD1002-SAS Sector Buffer. The Host sends as many 
bytes as there are in a sector on Logical Unit 0. This 
data is not written to any disk. The Write Sector Buf- 
fer Command provides the data used by format com- 
mands having bit 5 of the Control Byte = 1. 

This command is not used for the Floppy drives. 

Possible Error Codes 

00 No Error 



18. CONTROLLER DIAGNOSTIC (CLASS 7,0P CODE 
04) 

This command calculates a checksum for the ROM 
program, and tests the microprocessor and Sector 
Buffer. This command does not access any disk drive 
but destroys the previous contents of the Sector 
Buffer. 

Possible Error Codes 

00 No Error 

48 RAM Failure 

49 ROM Failure 



O 

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I 

CO 

> 



Winchester Board Products 



6-45 



o 
o 

lO 

GO 

> 



19. READ LONG (CLASS 7,0P CODE 05) 

Beginning with the specified sector, this command 
reads the specified number of consecutive sectors 
and an additional four ECC data bytes per sector pro- 
vided by the controller. 

This command is not used for the Floppy drives. 

Possible Error Codes 

00 No Error 

03 Write Fault 

04 Drive Not Ready 

1 8 Address Mark Not Found 
21 Seek Error 

25 Bad Track 

2 8 Illegal (Direct) Access to an Alternate Track 
30 Alternate Track Not Marked as Alternate 

32 Invalid Command 

33 Invalid Sector Address 

20. WRITE LONG (CLASS 7,0P CODE 06) 

Beginning with the specified sector, this command 
writes the specified number of consecutive sectors. 
Following each sector, the Host sends the 
WD1002-SAS an additional four ECC data bytes 
(unaltered by the controller) which are written to the 
disk as ECC bytes for the sector. This command is 
useful for diagnostic purposes. 

This command is not used for the Floppy drives. 

Possible Error Codes 

00 No Error 

03 Write Fault 

04 Drive Not Ready 

1 8 Address Mark Not Found 
21 Seek Error 

25 Bad Track 

2 8 Illegal (Direct) Access to an Alternate Track 
30 Alternate Track Not Marked, as Alternate 

32 Invalid Command 

33 Invalid Sector Address 



COMMAND STATUS BYTE 

After each command is executed, the WD1002-SAS 
sends a Command Status Byte to the Host to deter- 
mine whether the command is completed suc- 
cessfully. The logical unit number returned represents 
the contents of the logical unit field in the drive con- 
trol block. 



BITS 


7 


6 


5 


4 


3 


2 


1 





LUN 











E 






LUN Logical Unit Number 
E Error Flag: 

= No Error 

1 = Error 

COMMAND COMPLETION BYTE 

Immediately following each Command Status Byte, 
the WD1002-SAS sends a Command Co mpletio n Byte 
containing all zeros to the Host while MS G is ass- 
erted. This byte indicates to the Host that BSY will 
be de-asserted, the bus is available for the next 
command. 



6-46 



Winchester Board Products 



HOST INTERFACE TIMING 

Timing diagrams are shown in Figures 4 through 6 
and their vaiues are given in Tabies 11 and 12. 



o 
o 

N) 

GO 
> 
C/) 



00 TERMINATES COMMAND 



#2 #3 #4 #5 #6 




DATA \\\X VALID 
CONTROLLER 



I Y VALID Y VALID Y VALID Y VALID Y 



VALID 



ADDRESS 



BYTE #1 OF COMMAND IF COMMAND HAS A DATA TRANSFER IT HAPPENS HERE 



A^l 




VALID Y VALID 



STATUS BYTE 



SEL 



~u 



r 





nnr^nnr" 



\ 



y v_^ 



FIGURE 4. TYPICAL HOST-CONTROLLER BUS TRANSFER TIMING 



Winchester Board Products 



6-47 



o 

o 
o 




H' 

' '//////m//////M — y 







r 


tCY 

AH 


i 

1 




'RAL 


*ARH *F 












— »4'sur|-*- 


1 


^ 


^ 


•rdh 


WM 





FIGURE 5: HOST-TO-CONTROLLER TIMING 



FIGURE 6: CONTROLLER-TO-HOST TIMING 



TABLE 11. 
HOST-TO-CONTROLLER TIMING PARAMETERS 



*xx 


MIN(nsec) 


MAX(nsec) 


^CY* 


1152 




tRALt 







Urh 


600 


840 


tRAHtt 







Url 


200 


488 


Udv 




375 


Trdh 








*lf conditions in f and ft are met, then tcv (typ) = 
1200 nsec and toy max = 1248 nsec. 

tif tpy^L - 89 nsec, tlien no wait states are inserted, 
ttif tpAH - 97 nsec, then no wait states are inserted. 
One wait state = 200 nsec. 



TABLE 12. 
CONTROLLER-TO-HOST TIMING PARAMETERS 



*xx 


MIN(nsec) 


MAX{nsec) 


^CY* 


1152 




tRALt 







Urh 


200 


448 


tRAHtt 







tARL 


200 


848 


tsUR 


125 




tRDH 


152 





*if conditions in t and ft are met, then tcvOyp) = 
1200 nsec and toy max = 1248 nsec. 

t'f tRAL -497 nsec, then no wait states are 
inserted, 
tt'f tRAH ^200 nsec, then no wait states are 
inserted. 



6-48 



Winchester Board Products 



WESTERN DIGITAL 

CORPORATION 

WD1002-WX1 Winchester Disk Controller 



FEATURES 

4.95" X 3.85" HALF-SLOT FORM FACTOR 

IBM XT WINCHESTER CONTROLLER EMULA- 
TION, IBM PC HOST INTERFACE 

WD10C20 SELF-ADJUSTING DATA SEPARATOR 

DATA RATES UP TO 5 MBITS/SEC 

CONTROLS UP TO 2 DRIVES USING SEAGATE 
TECHNOLOGY ST506 

SUPPORTS DRIVES OF ANY CONFIGURATION 
UP TO 1024 CYLINDERS AND 16 R/W HEADS 

32-BIT ECC POLYNOMIAL FOR ERROR DETEC- 
TION AND CORRECTION 



DIAGNOSTIC READS AND WRITES FOR CHECK- 
ING ERROR CORRECTION 

AUTOMATIC FORMATTING 

512 BYTES PER SECTOR 

SECTOR INTERLEAVE CAPABILITY 

MULTIPLE SECTOR READS AND WRITES 

INTERNAL DIAGNOSTICS 

DMA TRANSFER CAPABILITY 

AUTO-CONFIGURABLE BIOS ROM 

COMPATIBLE WITH WD1002S-WX2 



O 

o 
o 

X 



DESCRIPTION 

The WD1002-WX1 Winchester Controller is a half-slot 
sized IBM XT compatible board designed to interface 
up to two hard disk drives. The drive interface is based 
upon the Seagate Technology ST506. The drives need 
not be of the same capacity or configuration. All 
necessary receivers and drivers are included on the 
board to allow/ direct connection to the drive(s). 

The WD1002-WX1 interfaces directly with the Host I/O 
bus via several interface buses. Data transfer to or 
from the Controller can be either programmed I/O or 
DMA. 

The WD1002-WX1 is based on the WD1010A-05 Win- 
chester Controller/Formatter, the WD1015 Control Pro- 
cessor, the WD110C0-17 Logic Array, and WD10C20 
Data Separator. 

Monitoring of the disk drive status lines is a major 
function of the WD1010A-05. The WD1010A-05 also 
controls passage of read and write data between the 
WD10C20 Data Separator and the other major com- 
ponents of the WD1002-WX1. 



The WD1015 controls and coordinates the activity of 
the disk drive, WD1010A-05, and WD11C00-17. The 
WD1002-WX1 receives and sends commands or 
status information over the 8-bit multiplexed 
address/data bus, ADO through ADZ. Drive control 
signals select the proper drive and head when 
enabled by the WD1015. 

The WD11C00-17 Logic Array incorporates several 
functions in a single package. Implementation of 
these functions occurs by combining random logic 
and specialized circuits. The WD11C00-17 contains 
the following circuits 

Status ports 

Read and write ports 

Sector Buffer RAM addressing and control 

Disk I/O Control 

ECC 

Reset Timing 

The WD10C20 is a monolithic CMOS Data Separator. 
This component interfaces the WD1010A-05 to a Win- 
chester disk drive. 



Winchester Board Products 



6-49 



o 

o 
o 

lO 

X 




RESET 



WD1002-WX1 BLOCK DIAGRAM 



6-50 



Winchester Board Products 



WESTERN DIGITAL 

CORPORATION 

WD1002S-SHD Winchester Disk Controller 



FEATURES 

SASI HOST INTERFACE 

BAD TRACK MAPPING CAPABILITY 

MULTIPLE SECTOR READS AND WRITES 

SUPPORTS REMOVABLE MEDIA DRIVES 

AUTOMATIC FORMATTING 

ADJUSTMENT FREE DATA SEPARATOR 

IMPLIED SEEKS 

OVERLAPPED SEEKS 

3 1/2 INCH FORM FACTOR 

32-BIT ECC FOR WINCHESTER DATA 
CORRECTION 

256 OR 512 BYTES PER SECTOR 

CONTROL FOR EITHER ONE OR TWO 
WINCHESTER DRIVES, WITH UP TO SIXTEEN 
READ/WRITE HEADS EACH 

DIAGNOSTIC READS AND WRITES FOR 
CHECKING ERROR CORRECTION 

SELECTABLE INTERLEAVE 

BUILT-IN WRITE PRECOMPENSTION 

SUPPORTS UP TO 16 HEADS 



DESCRIPTION 

The WD1002S-SHD Is a stand alone, general purpose 
Winchester Disk Controller Board, incorporating the 
latest state-of-the-art surface mount technology and 
designed to interface up to two Winchester Disk 
Drives to a Host Processor. The Winchester Drive 
signals are based upon the Seagate Technology 
ST506 interface and other compatible drives. All 
necessary receivers and drivers are included on the 
board to allow direct connection to the drive. 

Communication to and from the Host are made via 
a separate computer access port. This port confomis 
to the Shugart Associates System Interface (SASI) 
and consists of control signals and an 8-bit, bi- 
directional bus. All data to be written to or read from 
the disk, status information, and command 
parameters are transferred via this bus. An on-board 
Sector Buffer allows bus transfers to be executed 
independently of the actual data transfer of the drive. 

ARCHITECTURE 

The WD1002S-SHD Winchester Disk Controller is 
based upon a Western Digital proprietary chip set 
consisting of a: WD1010A-05, WD10C20, WD1015, and 
the WD11C00-16, all specifically designed for Win- 
chester disk control. 



O 

-x 
O 
O 

GO 

X 

o 



TABLE 1. WD1002S-SHD INTERFACE CONNECTORS 



REFERENCE DESIGNATION 


INTERFACE FUNCTION 


MATING CONNECTOR 


PI 


POWER 


AMP1-480424-0 (Housing) 

AMP3500784 

4-pin connector 


J1 


HOST (SASI BUS) 


AMP88379-8 

50-pin vertical header 


J2-J3 


DRIVE DATA 


AMP88377-4 

20-pin vertical header 


J4 


DRIVE CONTROL 


AMP88373-3 

34-pin PC card edge connector 



Winchester Board Products 



6-51 



o 

o 
o 
ro 
(/) 

00 

I 
o 



WDnCOO-16 
ADDRESS 
COUNTER 



r 



» 



wDiicooie 

ECC 

GENERATOR 

& CHECKER 



I£ 



W01010A05 
WINCHESTER 

DISK 
CONTROLLER 



TLJLiOF 



ccJioVt r. ATV DRIVERS AND 4J\- 



WINCHESTER 
DISK DRIVES 



Ik 



W01015 12 

CONTROL 

PROCESSOR 



^'b 



WD11C00-16 

DRIVERS AND 

RECEIVER 







WD11C0O-16 

SASI 

BUS 
CONTROLLER 



t 

CONTROL 
SIGNALS 



CLOCK 
SIGNALS 



WD10C20 
CLOCK GENERATOR 



WD11C0016 

RESET CIRCUIT 

AND WRITE GATE 

DEGLITCHER 



FIGURE 1. WD1002S-SHD WINCHESTER DISK CONTROLLER BLOCK DIAGRAM 



6-52 



Winchester Board Products 



SPECIFICATIONS 

HOST INTERFACE 

Type 

Max Cable Length 

(Total Daisy Chain) 
Termination 
Addressing 

DRIVE INTERFACES 

Encoding Method 
Cylinders per Track 
Bytes per Sector 
Sectors per Tracl< 

Max Heads 

Drive Selects 

Stepping Rates/Algorythms 

Data Transfer Rate 

Write Precomp Time 

Max Cable Length: 

Control (Total Daisy-Chain) 

Data (Radial-each) 

POWER 

Voltage 
Current 
Ripple 

DATA SEPARATOR 

Read Margin 
Asymmetry 



SASI 

4.5 meters (15 ft.) 

Socketed 220/330 ohm resistor pack 
Jumper selectable to 7 



MFM 

Programmable 

Jumper selectable (256 or 512) 

32 (256 bytes/sector) 

17 (512 bytes/sector) 

16 

2 

Programmable 

5 M bits/sec 
12 nsec 

6 Meters (20 ft.) 
6 Meters (20 ft.) 



+ 5 VDC ± 5% and -f 12 VDC ± 5% 
800 ma typical (1.0 amps max) 
0.1 to 25 mv (0.1 VDC max) 



± 16 nsec 

30 nsec measured over 5 MHZ 

Raw MFM periods of 185, 215, nsec 



O 

o 
o 
ro 
CO 

GO 

I 
O 



PHYSICAL 

Length 

Width 

Height (max. including board, 

components & leads) 
MTBF 
MTTR 

ENVIRONMENTAL 

Ambient Temperature 
Relative Humidity 
Altitude 
Air Flow 



5.75 inches 
4.00 inches 
0.75 inches 

10,000 POH 
30 Minutes 



0°C (32°) to 55°C (131°F) 

10% to 90% non-condensing 

to 10,000 Feet (3,048 meters) 

150 linear feet per minute at 1/4 inch from competent surfaces. 



Winchester Board Products 



6-53 



o 

o 
o 

CO 
I 

C/) 

X 

a 



HOST INTERFACE 

The WD1002S-SHD Winchester Disk Controller is 
designed to interface with the Shugart Associates 
System Interface (SASI) Bus. All interfacing is done 
through the SASI connector (J1). The Host and seven 



other SASI connpatible devices can be daisy-chained 
to this bus. The last device in the daisy-chain must 
be terminated with a standard 220/330 ohm resistor 
pack. 



TABLE 2. HOST INTERFACE CONNECTOR (J1) PIN DESCRIPTIONS 



SIG. 


SIG. 










GND. 


PIN 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


1 


2 


DO 


DATAO 


I/O 


8-Bit, bi-directional bus used for the transfer 


3 


4 


thru 


thru 




of commands, status and data 


5 


6 


D7 


DATA 7 






7 


8 










9 


10 










11 


12 










13 


14 










15 


16 










17 th 
35 


ru 34 
36 


Spare 
BSY 







Falling edge acknowledges receipt of SEL 


BUSY 












and address. Rising edge indicates transac- 


37 


38 


ACK 




1 


tion complete. 

Handshake for byte transfers (both edges 


ACKNOWLEDGE 


39 
41 


40 
42 


RST 
MSG 




1 




used). 

Asserted for 100 nsec. 

Indicates type of bus transfer (see information 


RESET 


MESSAGE 


43 


44 


SEL 




1 


Transfer Phase). 

Asserted, gives control of bus to addressed 


SELECT 


45 


46 


C/D 







target. 

Indicates type of bus transfer (see information 


CONTROUDATA 


47 


48 


REQ 







Transfer Phase). 

Handshake for byte transfers (both edges 


REQUEST 












used). 


49 


50 


I/O 


IN/OUT 


I/O 


L = Input to the Host 

H = Output from Host 

(See information Transfer Phase) 



6-54 



Winchester Board Products 



DRIVE CONTROL INTERFACE 

The control signals are common to both drives and 
are daisy chained from a single 34-pin PC card edge 
connector (J4). To terminate the control signals 



properly, the last drive in the daisy-chain must not 
be more than 20 feet from the controller, and have 
a 220/330 ohm resistor pack installed. 



TABLE 3. DRIVE CONTROL CONNECTOR (J4) PIN DESCRIPTIONS 



SIG. 
GND. 


SIG. 
PIN 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


1 

3 
5 

7 

9 

11 
13 

15 
17 


2 

4 
6 

8 
10 

12 

14 

16 
18 


RWC 
HS3 

CHANGE 
CART 

HS2 

WG 

SC 


REDUCE 

WRITE CURRENT 











1 

1 

1 






RWC is asserted when the Present Cylinder 
Number Register is equal to or greater than 
the content programmed in the Write Precomp 
Register. It is used by the drive to reduce drift 
caused by greater bit density on the inner 
cylinders. 

HS3 is an optional Head Select line that 
allows the selection of eight additional heads. 

CHANGECART when activated, will stop the 

spindle motor. 

(Removable Media Drives only) 

HS2 is one of three Head Select signals 
encoded by the drive to select one of eight 
R/W heads. 

WG is asserted when valid data is to be 
written. It is used by the drive to enable the 
write current to the head. WD1002S-SHD de- 
asserts this signal when WF is asserted. 
WD1002S-SHD prevents WG from being 
asserted at power up, allowing the drive to 
remain ON while cycling the Controller ON or 
OFF. 

SC, when asserted, informs the WD1002S-SHD 
that the selected head has reached the desired 
cylinder and has stabilized. 

The drive asserts TKOOO when the heads are 
positioned over the outermost cylinder 
(Track 0). 

WF is asserted by the drive when a write error 
occurs. 

HSO is one of three Head Select signals 
encoded by the drive to select one of eight 
R/W heads. 

Not Used. 

HS1 is one of three Head Select signals 
encoded by the drive to select on of eight R/W 
heads. 


HEAD SELECT 3 


CHANGECART 


HEAD SELECT 2 


WRITE GATE 


SEEK COMPLETE 


TKOOO 

WF 
HSO 


TRACK 000 


WRITE FAULT 


HEAD SELECT 


RECOVER 

HS1 
WRTSERVO 


RECOVERY MODE 


HEAD SELECT 1 


WRITE SERVO 


WRTSERVO is used to write servo infomnation 
on a new cartridge. 



o 
o 
ro 

CO 



Winchester Board Products 



6-55 



TABLE 3. DRIVE CONTROL CONNECTOR (J4) PIN DESCRIPTIONS (CONT'D.) 



O 
O 

o 
ro 

CO 
00 

I 
o 



SIG. 
GND. 


SIG. 
PIN 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


19 

21 

23 

25 
27 
29 
31 
33 


20 

22 

24 

26 
28 
30 
32 

34 


INDEX 


INDEX PULSE 


1 

1 









This signal Indicates start of a track. It is used 
as a synchronization point during formatting 
and as a time out mechanism for retries. This 
signal pulses once for each revolution of the 
disl<. 


DRDY 


DRIVE READY 


The drive asserts DRDY when selected and 
the motor is up to speed. 


STEP 


STEP PULSE 


STEP, with DIRIN, positions the heads to 
the desired cylinder. 

DSELO is used to select drive 1. 


DSELO 


DRIVE SELECT 


DSEL1 

NC 

NC 


DRIVE SELECT 1 
Not Connected 
Not Connected 


DSEL1 is used to select drive 2. 


DIRIN 


DIRECTION IN 


DIRIN determines the direction the R/W heads 
take when stepped. 
Asserted = IN. 
De-asserted = OUT. 



DRIVE DATA INTERFACE 

The data Is differential and must be connected to 
each drive with its own cable (J2, J3). It should be 
a flat ribbon cable, or twisted pair, less than 20 feet 



long. The connector is a 20-pin vertical header on a 
0.1" center. 



TABLE 4. DRIVE DATA CONNECTORS (J2,J3) PINS 



SIGNAL 


SIGNAL 






GROUND 


PIN 


I/O 


SIGNAL NAME 


. 


1 




Not Connected 


2 


- 




Ground 


- 


3 





Reinitialize 


4 


5 


1 


Ground 


Write Protected 


6 


- 




Ground 


- 


7 




Not Connected 


8 


9 
10 


1 

1 


Ground 


Cartridge Changed 


Cartridge In 


11 


- 




Ground 


12 


- 




Ground 


- 


13 





+ MFM Write Data 


. 


14 





- MFM Write Data 


15 


- 




Ground 


16 


- 




Ground 


- 


17 


1 


+ MFM Read Data 


- 


18 


1 


- MFM Read Data 


19 


- 




Ground 


20 


- 




Ground 



6-56 



Winchester Board Products 



POWER CONNECTOR 

A 4-pin AMP connector (PI) provides power input to 
the WD1002S- SHD Controller. 



TABLE 5. POWER CONNECTOR (PI) PIN DESCRIPTIONS 



SIGNAL 


SIGNAL 




GROUND 


PIN 


SIGNAL NAME 




1 


+ 12 Volts (regulated) 


2 




Ground 


3 




Ground 




4 


+ 5 Volts (regulated) 



o 
o 
ro 
(/) 

GO 

I 
O 



DISK DRIVE CONFIGURATION 
PARAMETERS 

Table 6 lists the variable parameters for the major 
drives supported by the WD1002S-SHD Winchester 
Disk Controller. 



TABLE 6. DISK DRIVE CONFIGURATION PARAMETER VARIATIONS 











REDUCED WRITE 


WRITE PRECOMPENSATION 


MFGR 


MODEL # 


CYLINDERS 


HEADS 


CURRENT CYL. 


CYLINDER 


CMI 


CM-5205 


256 (100) 


2 


56 (100) 


256 (100) 


CMI 


CM-5410 


256 (100) 


4 


256 (100) 


256 (100) 


CMI 


CM-5616 


256 (100) 


6 


256 (100) 


256 (100) 


OLI 


HD561 


180 (B4) 


2 


128 (80) 


180 (84) 


OLI 


HD562 


180 (B4) 


2 


128 (80) 


180 (84) 


RMS 


503 


153 (99) 


2 


77 (4B) 


77 (48) 


RMS 


506 


153 (99) 


4 


77 (48) 


77 (48) 


RMS 


512 


153 (99) 


8 


77 (48) 


77 (48) 


SEA 


ST506 


153 (99) 


4 


128 (80) 


64(40) 


SEA 


ST412 


306 (132) 


4 


128 (80) 


64 (40) 


TAN 


TM602S 


153 (99) 


4 


128 (80) 


153 (99) 


TAN 


TM603S 


153 (99) 


6 


128 (80) 


153 (99) 


TAN 


TM603SE 


230 (E6) 


6 


128 (80) 


128 (80) 


Tl 


5 1/4 + 


153 (99) 


4 


64(40) 


64(40) 


RO 


101 


192 (CO) 


2 


96(60) 


0(0) 


RO 


102 


192 (CO) 


4 


96 (60) 


0(0) 


RO 


103 


192 (CO) 


6 


96 (60) 


0(0) 


RO 


104 


192 (CO) 


8 


96 (60) 


0(0) 


RO 


201 


321 (141) 


2 


132 (84) 


0(0) 


RO 


202 


321 (141) 


4 


132 (84) 


0(0) 


RO 


203 


321 (141) 


6 


132 (84) 


0(0) 


RO 


204 


321 (141) 


8 


132 (84) 


0(0) 


MS 


1-006 


306 (132) 


2 


153 (99) 


0(0) 


MS 


1-012 


306 (132) 


4 


153 (99) 


0(0) 


DMA 


360 


306 (132) 


2 


153 (99) 


0(0) 


SYQ 


312RO 


306 (132) 


2 


153 (99) 


0(0) 



Winchester Board Products 



6-57 



DRIVE MANUFACTURES ABBREVIATIONS: 



^ 


CMI 


Computer Memories Inc. 


a 


OLI 


Oliveti 


o 


RMS 


Rotating Memory Systems Inc 


o 
ro 
in 


SEA 


Seagate Technology Inc. 


TAN 


Tandon Inc. 


(/) 


Tl 


Texas Instruments 


I 


RO 


Rodime Ltd. 


u 


MS 


Miniscribe 




DMA 


DMA Systems 




SYQ 


Syquest Corp. 



COMMANDS 

Tlie WD1002S-SHD Winchester Disk Controller Board 
supports 26 different SASI commands; 21 operation 
commands and 5 diagnostic commands. Table 7 is 



a summary of the supported commands and their 
parameters. It also includes information about data 
transfers required during execution. All other SASI 
command codes are reserved. 



TABLE 7. WD1002S-SHD SUPPORTED COMMAND SUMMARY 















#SASI 












LOGICAL 


INTERLEAV 


CONTROL 


DATA 






COMMAND 


CLASS, 




SECTOR 


OR BLOCK 


BYTE 


BLOCK 


D.B. 


DIREC- 


NAME 


OPCODE 


LUN 


ADDRESS 


COUNT 


OPTIONS 


TRNSFRS 


SIZE 


TION 


Test Drive 


















Ready 


0,00 


W 






-- 





-- 




Restore to 


















Track 


0,01 


w 


— 













Req. Status 


0,03 


w 








1 


4 


To Host 


Frmt Drive 


0,04 


w 


L* 


1 


R,P,S,Z 









Chk Tr Frmt 


0,05 


w 


L* 


1 


R,S 









Format Track 


0,06 


w 


L* 


1 


R,P,S,Z 









Frmt Bad Trk 


0,07 


w 


L* 


1 


R,P,S,Z 









Read 


0,08 


w 


L 


B 


R,A,S 


B 


SCTR 


To Host 


Stop Drive 


0,13 


w 















Write 


0,0A 


w 


L 


B 


R,S 


B 


SCTR 


To CTLR 


Seek 


0,0B 


w 


L* 




R,S 









Set 


















Parameters 


O.OC 


w 


— 






1 


8 


To CTLR 


Last 


















Corrected 


















Burst 


















Length 


0,0D 


w 








1 


1 


To Host 


Frmt Alt Trk 


0,0E 


w 


L* 


1 


R,P,S,Z 


1 


3 


To CTLR 


Wr Sot Bfr 


0,0F 


- 


— 


— 




1 


SCTR 


To CTLR 


Rd Sot Bfr 


0,10 


- 








1 


SCTR 


To Host 


Write Servo 


6,00 


w 
















6-58 



Winchester Board Products 



TABLE 7. WD1002S-SHD SUPPORTED COMMAND SUMMARY (CONT'D) 















#SASI 












LOGICAL 


INTERLEAV 


CONTROL 


DATA 






COMMAND 


CLASS, 




SECTOR 


OR BLOCK 


BYTE 


BLOCK 


D.B. 


DIREC- 


NAME 


OPCODE 


LUN 


ADDRESS 


COUNT 


OPTIONS 


TRNSFRS 


SIZE 


TION 


Reinitialize 


















Cartridge 


6,02 


W 











-- 




RAM Diag 


7,00 


- 















Drive Diag 


7,03 


w 






R,S 









CTLR Diag 


7,04 


- 















RD Long 


7,05 


w 


L 


B 


R,S 


B 


SECT 
+ 4 


To Host 


WR Long 


7,06 


w 


L 


B 


R,S 


B 


SECT 

+ 4 


To CTLR 



o 
o 
to 
c/> 

if) 

I 
O 



W Winchester 

L* Logical sector address used only to specify tracl< 

L Logical sector address 

I interleave 

B Block count 

R Retry enable/disable 

A Attempt immediate ECC enable/disable 

S Stepping algorithm 

P Used with Format commands for determining data field patterns function should be performed. 

Z Used with Format commands for determining if a Write Sen/o function should be performed. 



COMMAND BLOCKS 

A transaction is initiated by the Host to instruct the 
WD1002S- SHD Winchester Disk Controller to execute 
a given command. During the Command Block 



Transfer Phase, six bytes of information specifying 
the command are transferred to the WD1002S-SHD 
Winchester Disk Controller. This is the Command 
Block and is illustrated in Figure 2. 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code 


1 


Logical Unit Num 


Logical Sector Address(High) 


2 


Logical Sector Address (Middle) 


3 


Logical Sector Address (Low) 


4 


Interleave or Block Count 


5 


Control Byte 



FIGURE 2. COMMAND BLOCK FORMAT 



Winchester Board Products 



6-59 



o 

o 
o 
ro 
(/) 

GO 

X 

o 



Byte is transferred first and must be specified for 
all commands. Depending upon tfie value of Byte 0, 
each parameter in bytes 1 through 5 may require 
specification. 

LOGICAL UNIT NUMBER (LUN) 

The LUN is contained in the three MSBits of Byte 1. 
The allowed values are and 1. The designators in 
the command table are: Drive (LUN = 0) or Drive 
1 (LUN = 1). 

LOGICAL SECTOR ADDRESS 

The Logical Sector Address (High, Middle, and Low) 
is a 21-bit field contained in Bytes 1, 2, and 3. It is 
computed from the Cylinder Addres (C), Head Address 
(H), and Sector Address (S), as well as the drive 
parameters Heads per Cylinder (HC) and Sectors per 
Track (ST): 

L = a(C X HC) + H] X ST) + S 

C, H, and S can be derived from L, HC and ST 
as follows: 

S = L Modulo ST 

H = [(L-S) /ST] Modulo HC 

C = ([(L-S /ST] -H) /HC 



This field specifies a sector (or beginning sector) for 
the Read and Write drive commands. It specifies a 
tracl< for the Format and Seek commands (indicated 
by L* in Table 7). When only a track specification is 
required, the sector number implied by the Logical 
Sector Address Is ignored. 

INTERLEAVE OR BLOCK COUNT 

The Interleave or Block Count comprise Byte 4. The 
Interleave ratio (I in Table 7) is specified in the five 
Format commands. The maximum ratio is equal to 
the Sector-per-Track minus 1. 

The Block Count (B in Table 7) is specified in the 
Read, Write, Read Long, and Write Long commands. 
B specifies the number of Logical Sectors to be 
transferred. 

Both Interleave ratio and Block Count use all 8-bits 
to specify their respective parameters. 

CONTROL BYTES 

Table 8 defines the Control Byte fields: 



TABLE 8. CONTROL BYTE FIELDS 



FIELD 


BIT (S) 


FUNCTION 


STEP 

Z 
P 

A 
R 


0-3 

4 
5 

6 
7 


Used in all commands that contain code corresponding to seek stepping 
algorithm. See Fast Step Options. 

Write Servo Information 

Format Data (P) is used in the Format commands. If P = 0, the WD1002S- 
SHD fills the data field with 6C Hex. If P = 1, data field is filled with the pat- 
tern in the Sector Buffer. 

Immediate ECC (A) is used in the Read command. If A = 0, no immediate 
ECC is performed. If A = 1, immediate ECC is performed. 

Retry (R) Is used in all commands that read the ID field. If R = 0, (normal), 
a maximum of 3 non-restore retries are performed, then Restore, Seek, and 
1 more read is performed. If R = 1 Retry is disabled then no retries are 
performed. 



NOTE 

If one or more of the above fields are required for 
a command, then all other fields In that Control Byte 
must be set to 0. If none of the above are required, 
all bits in the Control Byte are interpreted as 'don't 
care' bits (X). 



FAST STEP OPTIONS 

The Fast Step Option field contains an unsigned 
3-bit integer. These integers correspond to the Fast 
Step Algorithms listed in Table 9. 



6-60 



Winchester Board Products 



TABLE 9. FAST STEP OPTION ALGORITHMS 



OPTION 


ALGORITHM 





Default: 3 msec, per step 




1 


Reserved 




2 


Reserved 




3 


Reserved 




4 


200 usee, per step. This is appropriate for buffered steps on 
Computer Memories Inc. and Rotating Memories Inc. 


drives made by 


5 


70 usee, per step 




6 


30 usee, per step 




7 


15 usee, per step 




8 


12fi's per step 




9-F 


Spare (3 msec, per step) 





o 
o 
to 

(p 

CO 

X 

o 



COMMAND STATUS BYTE 

At the completion of any command execution, a Com- 
mand Status Byte is sent by the WD1002S-SHD to the 
Host, whether the command was successful or 
aborted. The LUN returned is the contents of the LUN 
field in the drive control block. For those commands 
that do not use LUN as an input parameter, the LUN 
returned in the Command Status Byte is meaningless. 
Figure 3 illustrates the contents of the Command 
Status Byte. 



COMMAND COMPLETION BYTE 

The Command Completion Byte is an all zero byte 
sent by the WD1002S-SHD Winchester Disk Controller 
to the Host immediately following each Command 
Status Byte. It indicates to the Host that the 
WD1002S-SHD has freed the SASI Bus. 



BITS 



7 


6 


5 


4 


3 


2 


1 





LUN 








P 


EF 


CC 



EF (Error Flag): = no error 

1 = error 
P (Write Protected) = 1 

(Removable Media Only) 
CC (Cartridge Changed) = 1 

= Default 

1 = CC 

FIGURE 3. COMMAND STATUS BYTE 



Winchester Board Products 



6-61 



COMMAND DESCRIPTIONS 



O 

O 

(/) 
GO 

I 
O 



TEST DRIVE READY 
(CLASS 0,OP CODE 00) 

This command selects a drive and verifies that it is 
ready. The following is the Test Drive Ready com- 
mand block format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code 00 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 


X 


X 


X 


X 


X 


X 


X 



Possible Error Codes 
Action 



No Error, Invalid Command, No Seek Complete, Drive Not Ready, or Write Fault. 

Select the drive and determine If it is ready. For a Winchester drive, read its 
status register and test the ready bit and the busy bit. For Winchester drives 
supporting buffered seeks, this command is useful for determining the first 
drive to reach its target track. 



6-62 



Winchester Board Products 



RESTORE TO TRACK 
(CLASS 0, OPCODE 01) 

This command positions the read/write heads to 
Track 0. 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code 01 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 











X 


X 


X 


X 



o 

—J. 

o 

o 

(/) 

GO 

X 

o 



Possible Error Codes 
Action 



No Error, Invalid Command.Track Not Found, Drive Not Found, or write Fault. 
Position the read/write heads to track 0. 



REQUEST STATUS 
(CLASS 0, OPCODE 03) 

The Host must send this command immediately after 
it detects an error. The command causes the 
WD1002S-SHD Winchester Disk Controller to return 
four bytes of drive and Controller status. When an 
error occurs during a multiple sector data transfer 
(read or write), the Request Status command returns 
the Logical Sector Address of the failing sector in 
bytes 1, 2, and 3. If the Request Status command is 



issued after any of the format commands of the 
Check Track Format command, then the Logical Sec- 
tor Address points to one sector beyond the last track 
formatted or checked if there was no error. If there 
was an error, then the Logical Address returned points 
to the track in error. The following is the Request 
Status command block format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code 03 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 


X 


X 


X 


X 


X 


X 


X 



Possible Error Codes 
Action 



No Error or Invalid Command. 

Send the Host 4 bytes; the error byte and a 3-byte Logical Sector Address for 
the specified drive. 



Winchester Board Products 



6-63 



o 

o 
o 

(/) 

I 

a 



ERROR/STATUS RESPONSE TO HOST 

The following non-drive error codes are treated as 
Drive errors: RAM Failure (30); ROM Failure (31), ECC 
Hardware Failure (33). If the RAM Diagnostic 



command or Controller Diagnostic command detects 
an error, then status for Drive should be 
requested. 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








LSA 





Error Codes 


1 


LUN 


Logical Sector Address Bits 16-20 


2 


Logical Sector Address Bits 8-15 


3 


Logical Sector Address Bits 0-07 



ERROR CODES 

A. DISK DRIVE ERROR CODES 

00 = No Error 

03 = Write Fault 

04 = Drive Not Ready 

06 = Track Not Found 

07 = Write Protected 

09 = Function Not Supported By Drive 

B. CONTROLLER ERROR CODES 

01, 02, 10/14 = Not used because the 
WD1010A-05 groups CRC 
with other errors in ID field 
as ID not found. During 
implied seeks, these are 
called SEEK errors. 
Code 15. 

11 = Uncorrectable Data Error 

12 = Address Mark Not Found 
15 = Seek Error 

18 = Error Burst Corrected 

19 = Bad Track 
1A = Format Error 

1C = Illegal (Direct) Access to an Alternate 

Track 
ID = Alternate Track Already Used 
1 E = Alternate Track Not Marked as Alternate 
IF = Alternate Track Equals Bad Track 

C. COMMAND ERROR CODES 

OA = Controller Not Initialized 

20 = Invalid Command 

21 = Invalid Sector Address 

22 = Illegal Parameter 



D. MISCELLANEOUS ERROR CODES 

30 = RAM Failure 

31 = ROM Failure 

32 = ECC Hardware Failure 

If the most recent non-request-status command to the 
specified drive required a Logical Sector Address, 
then the LSA flag is 1; otherwise it is and the Logical 
Sector Address is meaningless. 

ERROR CODE DESCRIPTIONS 

No Error (00) 

No error detected during the previous operation. 

Write Fault (03) 

Indicates that there is Write Current to the head when 
WG is deasserted. This is a very serious problem and 
should be remedied immediately. 

Drive Not Ready (04) 

The drive does not respond with a Drive Ready signal 
after being selected by the WD1002S-SHD. 

Track Not Found (06) 

This error is only returned by the Restore To Track 
command. It indicates that Track status from the 
drive was not asserted within the maximum number 
of steps towards cylinder 0. 

Write Protected (07) 

Function Not Supported By Drive (09) 



6-64 



Winchester Board Products 



Controller Not Initialized (OA) 

This occurs when user falls to Issue Initialize Format 
command before issuing any command that 
accesses the drive. 

Uncorrectable Data Error (11) 

This error indicates that one or more error bursts 
within the data field (Winchester) were beyond the 
Error Correction capabilities of the WD1002S-SHD. 
The sector data for this sector Is not sent to the Host. 

Address Mark Not Found (12) 

This error Indicates that the header for the Target Sec- 
tor was found, but its Address Mari< was not detected. 

Seek Error (1 5) 

The WD1002S-SHD detects an Incorrect cylinder or 
track, or both. 

Error Burst Corrected (18) 

indicates that ECC was used to successfully correct 
an error.The corrected sector data Is sent to the Host. 

Bad Track (19) 

This error usually Indicates access of a track that was 
formatted as a bad track. However, there Is a very 
small chance that It Indicates that a track formatted 
as a bad track with alternate Is so faulty that none 
of the multiple, duplicate pointers to the alternate 
track can be read. 



Alternate Track Not IVIarked as an Alternate (IE) 

This error code Indicates that access of a bad-track- 
wlth-alternate caused access to an alternate track 
that was not marked as an alternate. 

Alternate Track Equals Bad Track (1 F) 

This error code Is returned only by the Format Alter- 
nate Track command. It Indicates that the same track 
was specified as the bad track and the alternate track. 

Invalid Command (20) 

This error code Indicates that the Command Code, 
Interleave Factor, or Fast Step Option was Invalid. 

Invalid Sector Address (21) 

This error code Indicates that the WD1002S-SHD 
detected a sector address beyond the maximum 
range. 

Illegal Parameter (22) 

When Controller detects an invalid parameter or 
invalid combination of parameters. 

RAM Failure (30) 

This error code Indicates one of the following 
conditions: 

1. The program memory RAM checksum does not 
match the calculated checksum. 

2. The RAM In the Control Processor failed. 

3. The Control Processor CPU failed. 



o 
o 

(/) 

GO 

I 

a 



Format Error (1 A) 

This error code Is returned by the Check Track For- 
mat command, it Indicates that the track is not for- 
matted with the specified Interleave factor, or at least 
one sector header Is unreadable. This error code Is 
returned by the Drive Diagnostic command to Indicate 
that bad-track-wlth-alternate does not contain valid 
pointer to the alternate track. 

Illegal (Direct) Access to an Alternate Track (1C) 

Alternate Track Already Used (ID) 

This error code Is only returned by the Format Alter- 
nate Track command. It Indicates that the specified 
alternate track is already an alternate, or bad track. 



ROM Failure (31) 

This error code indicates that a ROM checksum error 
occurred during internal diagnostics. 

ECC Hardware Failure (32) 

This error code indicates that the ECC Support Device 
failed during internal diagnostics. 



Winchester Board Products 



6-65 



o 

o 
o 

<p 

C/) 

a 



FORMAT DRIVE 
(CLASS 0, OPCODE 04) 

This command formats all sectors with ID and data 
fields according to the selected interleave factor. This 
command also writes 6C Hex into the data fields. The 
starting address is passed into the Control Byte which 



is read by the WD1002S-SHD Winchester Disk Con- 
troller. The Controller then formats from this address 
to the end of the disk. The following is the Format 
Drive command block format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code 04 


1 


LUN 


Logical Sector Address Bits 16-20 


2 


Logical Sector Address Bits 8-15 


3 


Logical Sector Address Bits 0-07 


4 


Interleave Factor 


5 


R 





P 


Z 


Fast Step Option 



R Retry Disable: 
P Format Data: 
Z Write Servo: 



= No Disable 

1 = Disable 

= 6C Hex 

1 = Contents of Sector Buffer 

= Do Not Write Servo 

1 = Write Servo Information 



NOTE 

This is used only for removable media drives that 
implement the Write Servo function. 

Possible Error Codes 

No Error, Invalid Command, Invalid Sector Address, 
Drive Not Ready, Seek Error, or Write Fault. 

Action 

Fomriat from the specified track to the end of the disk. 
The previous contents of the formatted tracks are 
ignored. 



6-66 



Winchester Board Products 



CHECK TRACK FORMAT 
(CLASS 0,OPCODE 05) 

This command checks the format on the specified 
track for correct ID and interleave. The command does 
not read the data field. The following is the Check 
Track Format command block format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code 05 


1 


LUN 


Logical Sector Address Bits 16-20 


2 


Logical Sector Address Bits 8-15 


3 


Logical Sector Address Bits 0-07 


4 


Interleave Factor 


5 


R 











Fast Step Option 



a 

o 
o 

U) 

X 

o 



R Retry Disable: 



= No Disable 

1 = Disable 



Possible Error Codes 

No Error, Invalid Command, Invalid Sector Address, 
Seek Error,Format Error, Drive Not Ready, or Write 
Fault. 

Action 

Verify that the specified track is formatted with the 
specified interleave factor. Do not read the sector data 
fields. 



Winchester Board Products 



6-67 



o 

o 
o 
ro 

<P 
0) 

X 

a 



FORMAT TRACK 
(CLASS 0, OPCODE 06) 

This comand formats a specified tracl< and can be 
used to ciear bad-sector flags in aii sectors on tlie 
specified track that was previously fomriatted with the 



Format Bad Track command. The command writes 
6C Hex into all data fields specified. The following 
is the Format Track command block format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code 06 


1 


LUN 


Logical Sector Address Bits 16-20 


2 


Logical Sector Address Bits 8-15 


3 


Logical Sector Address Bits 0-07 


4 


Interleave Factor 


5 


R 





P 


Z 


Fast Step Option 



R Retry Disable: 
P Format Data: 
Z Write Servo: 



= No Disable 

1 = Disable 

= 6C Hex 

1 = Contents of Sector Buffer 

= Do not Write Servo 

1 = Write Servo Information 



Possible Error Codes 

No Error, Invalid Command, Invalid Sector Address, 
Drive Not Ready, Seek Error, or Write Fault. 

Action 

Format the specified track, ignoring the previous 
contents. 



6-68 



Winchester Board Products 



FORMAT BAD TRACK 
(CLASS 0, OPCODE 07) 

This command formats the specified track and sets 
the bad-sector flag in the iD fields. It does not write 



to the data fields. The following illustrates the Bad 
Track command block format. 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code 07 


1 


LUN 


Logical Sector Address Bits 16-20 


2 


Logical Sector Address Bits 8-15 


3 


Logical Sector Address Bits 0-07 


4 


Interleave Factor 


5 


R 








Z 


Fast Step Option 



a 

o 

o 

lO 

X 
O 



R Retry Disable: 
Z Write Servo: 



= No Disable 

1 = Disable 

= Do not Write Sen/o 

1 = Write Servo Information 



Possible Error Codes 

No Error, Invalid Command, Invalid Sector Address, 
Drive Not Ready, or Write Fault. 

Action 

Format the specified track with a bad block mark in 
each sector header, ignoring the previous contents. 
The contents of a bad track are not accessible. 



Winchester Board Products 



6-69 



D 

O 

o 

CO 

X 

o 



READ 

(CLASS 0, OPCODE 08) 

This command reads the specified number of sectors, 
starting with the initiai Sector Address contained 



in the Control Byte. The following is the Read com- 
mand block format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code 08 


1 


LUN 


Logical Sector Address Bits 16-20 


2 


Logical Sector Address Bits 8-15 


3 


Logical Sector Address Bits 0-07 


4 


Interleave Factor 


5 


R 


A 








Fast Step Option 



R Retry Disable: 
A Attempt ECC 



= No Disable 

1 = Disable 

= No Immediate Correction 

1 = Immediate ECC 



Possible Error Codes 

No Error, Invalid Command, Invalid Sector Address, 
Drive Not Ready, Seek Error, Bad Track, Illegal (direct) 
Access To Alternate Track, Alternate Track Not 
Marked As Alternate, Address Mark Not Found, Error 
Burst Corrected, Uncorrectable Data Error, or Write 
Fault. 

Action 

Read the specified number of consecutive sectors 
beginning with the specified Sector Address con- 
tained in the Control Byte. 



6-70 



Winchester Board Products 



WRITE 

(CLASS 0, OPCODE OA) 

This command writes the specified number of sec- 
tors, beginning with the initiai sector address 



contained in the Control Byte. The foiiowing is the 
Write command biock format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code OA 


1 


LUN 


Logical Sector Address Bits 16-20 


2 


Logical Sector Address Bits 8-15 


3 


Logical Sector Address Bits 0-07 


4 


Interleave Factor 


5 


R 











Fast Step Option 



o 

o 
o 
ro 

C/) 

X 

o 



R Retry Disable: 



= No Disable 

1 = Disable 



Possible Error Codes 

No Error, Invalid Command, Invalid Sector Address, 
Drive Not Ready, Seek Error, Bad Track, Illegal (direct) 
Access to Alternate Track, Alternate Track Not 
Marked As Alternate, Address Mark Not Found, or 
Write Fault. 



Action 

Write the specified number of sectors beginning with 
the specified Sector Address contained in the Con- 
trol Byte. 



Winchester Board Products 



6-71 



a 

O 
O 
lO 

<p 

c/> 
o 



SEEK 

(CLASS 0, OPCODE OB) 

This command initiates a seek to ttie track specified 
in the Control Byte. The drive must be formatted. 



The following is the Seek command block format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code OB 


1 


LUN 


Logical Sector Address Bits 16-20 


2 


Logical Sector Address Bits 8-15 


3 


Logical Sector Address Bits 0-07 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


R 











Fast Step Option 



R Retry Disable: 



= No Disable 

1 = Disable 



Possible Error Codes 

No Error, Invalid Command, Invalid Sector Address, 
Drive Not Ready, or Write Fault. 

Action 

Move the read/write head to the specified cylinder. 
Do not read any sector header to verify start or end 
position. 



6-72 



Winchester Board Products 



SET PARAMETERS 
(CLASS 0, OPCODE OC) 

This command enables the Host to configure the 
WD1002S-SHD Winchester Disk Controlier to worl< 
with drives that have different capacities and 
characteristics. However, both Drive and Drive 1 



must be of the same manufacturer and model 
number. The following is the Set Parameters com- 
mand block format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code OC 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 


X 


X 


X 


X 


X 


X 


X 



o 

o 
o 

<0 

C/) 

X 

o 



Possible Error Codes 

If parameters are out of range, an Invalid Command 
error will be set. 

Action 

Set the following parameters for both Winchester 
drives (LUN and 1): Number of cylinders, Number 
of heads; Starting Reduced Write Current cylinder, 
Starting Write Precompensation cylinder, and the 
maximum length of an error burst to be corrected. 
These parameters are sent by the Host to the 
WD1002S-SHD Winchester Disk Controller in a 
parameter block with the following format: 



Winchester Board Products 



6-73 



D 

-A 
o 
o 

lO 

<0 

CO 

O 



PARAMETER BLOCK 

After the Host sends the Set Parameters command 
block to the WD1002S-SHD Winchester Disk Con- 
troller, it then sends an 8-byte block of data that con- 
tains the required drive parameters. Some parameters 



occupy two bytes; all two-byte parameters are 
transferred with the Most Significant Byte first. The 
following is the 8-byte Parameter block format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








IVISByte of Number of Cylinders 


1 


LSByte of Number of Cylinders 


2 














Number of Heads 


3 


l\/ISByte of Starting RWC Cylinder 


4 


LSByte of Starting RWC Cylinder 


5 


IVlSByte of Starting Write Precomp Cylinder 


6 


LSByte of Starting Write Precomp Cylinder 


7 











RD 


Max ERR Burst Corrected 



RD (Removable Media Drive) 



= Fixed 

1 = Removable 



The following parameter defaults are set by Power-UP 
and Reset: 



Number of cylinders 


= 153 


Number of heads 


= 4 


Starting Reduced Write 




Current Cylinder 


= 128 


Starting Write Precompensation 




Cylinder 


= 64 


Maximum length of an error burst to 




be corrected 


= 11 



The acceptable ranges of the following parameters are 
as follows: 

Number of cylinders = 1 - 1024 

Number of heads =1-16 

Starting Reduced Write 

Current Cylinder = 1 - 1023 

Starting Write Precompensation 

Cylinder = - 1023 

Maximum length of an error 

burst to be corrected = i - ii 

If one of the parameters is out of range, then all 
parameters up to, but not including the parameter in 
error, are set for Drive and no parameteres are set 
for Drive 1. The error code for this error is Invalid 
Command. 



Starting Reduced Write Current Cylinder 

The specified starting Reduced Write Current cylinder 
number is reduced to the nearest integer multiple of 
four (i.e., 0, 4, 8, 12,. . .1020). 

IVIaximum Length of Error Burst To Be Corrected 

For practically all applications,the maximum length 
of the error burst to be corrected should be five. Cor- 
recting longer burst greatly increases the chance of 
miscorrecting. 



6-74 



Winchester Board Products 



LAST CORRECTED BURST LENGTH 
(CLASS 0, OPCODE OD) 

This command transfers one byte to the Host con- 
taining the values of the ECC burst length detected 
by the WD1002S-SHD during the last Read command. 



This byte is valid only after a correctable ECC error 
(18). 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code OD 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 


X 


X 


X 


X 


X 


X 


X 



o 

o 
o 

% 
o 



Possible Error Codes 

No Error. 

Action 

Send the Host one byte of data containing the length 
of the most recently corrected error burst. If no error 
burst has been corrected since the last Power-UP or 
Reset, then a byte of zeros is sent to the Host. 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Number of bits in Last Corrected Error Burst 



FIGURE 4. ERROR BURST LENGTH BLOCK 



Winchester Board Products 



6-75 



FORMAT ALTERNATE TRACK (CLASS 0, OPCODE OE) 



D 

o 
o 

CO 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code OE 


1 


LUN 


Logical Sector Address Bits 16-20 


2 


Logical Sector Address Bits 8-15 


3 


Logical Sector Address Bits 0-07 


4 


Interleave Factor 


5 


R 





P 


Z 


Fast Step Option 



R Retry Disable: 
P Format Data: 

Z Write Servo: 



= No Disable 

1 = Disable 

= 6C Hex 

1 = Contents of Sector Buffer 

= Do not Write Servo 

1 = Write Servo Information 



Possible Error Codes 

No Error, Invalid Command, Invalid Sector Address, 
Drive Not Ready, Seek Error, Alternate Track Already 
Used, Alternate Track Equals Bad Track, or Write 
Fault. 



Action 

Format the specified track as a bad-track-with- 
altemate. Format the specified alternate track with 
the specified Interleave factor. The Bad Block Mark 
is written in each sector header with the alternate 
address block written Into each sector data field. This 
Is done to all sectors of the track. It is not known to 
the user which sector of the track might be bad. The 
alternate track is specified by the Host by sending 
an alternate sector address block to the WD1002S- 
SHD after the command block. The alternate track 
is formatted after the bad track-with-alternate is for- 
matted. Once the altemate is fomnatted, the bad track 
to altemate seeking is transparent to the user. 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 

















Logical Sector Address Bits 16-20 


1 


Logical Sector Address Bits 8-15 


2 


Logical Sector Address Bits 0-07 



FIGURE 5. ALTERNATE SECTOR ADDRESS BLOCK 



6-76 



Winchester Board Products 



WRITE SECTOR BUFFER (CLASS 0, OPCODE OF) 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code OF 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 


X 


X 


X 


X 


X 


X 


X 



o 

O 
O 

CO 

X 

o 



Possible Error Codes 

No Errors. 

Action 

Write data from the Host to the WD1002S-SHD Win- 
chester Disl< Controller Sector Buffer. The Host must 
send as many bytes as there are in a sector on Drive 
0. These data are not written to any drive. This com- 
mand is used to initialize the format data optionally 
used by the Format commands. 

READ SECTOR BUFFER (CLASS 0, OPCODE 10) 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code 10 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 


X 


X 


X 


X 


X 


X 


X 



Possible Error Codes 

No Error. 

Action 

Send the Host the present contents of the WD1002S- 
SHD Winchester Disk Controller Sector Buffer. The 
Host must accept as many bytes as there are in a 
sector on Drive 0. 



Winchester Board Products 



6-77 



o 

—A 

o 
o 

CO 

X 

o 



STOP DRIVE 

(CLASS 0, OPCODE 13) 

This command causes a removable cartridge disl< 
drive to spin down and stop so the user can change 
the cartridge. After the cartridge is changed, the drive 
must be started by external means. Software can 



checl< for completion of the cartridge change by using 
the Test Drive Ready command. The format for the 
Stop Drive command is as follows: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 


Operation Code 13 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 


X 


X 


X 


X 


X 


X 


X 



Possible Error Codes 

Function Not Supported By Drive. 



Action 

Spins down drive to allow user to change removable 
cartridge. 



WRITE SERVO 
(CLASS 6, OPCODE 00) 

The Write Servo command completely erases the 
existing servo information and all other data on the 
disl<, then rewrites the servo information. This pro- 
vides optimum alignment between cartridge and drive 



(and may enhance seel< performance) as each car- 
tridge can be servo written by the drive in which it 
is to be used. 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 6 


Operation Code 00 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 


X 


X 


X 


X 


X 


X 


X 



Possible Error Codes 

Function Not Supported By Drive. 



6-78 



Winchester Board Products 



REINITIALIZE CARTRIDGE 
(CLASS 6, OPCODE 02) 

This command provides a servo reinitialization cycle 
wherin track location and disk runout information are 
reprogrammed in the drive microprocessor. This 



function may be employed by the Host system to 
improve Seek en"or rate, and is automatically provided 
on a power-UP sequence or after a cartridge change. 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 6 


Operation Code 02 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 


X 


X 


X 


X 


X 


X 


X 



a 

o 
o 
ro 

<P 
CO 

X 

a 



Possible Error Codes 

Function Not Supported By Drive. 

RAM DIAGNOSTIC 
(CLASS 7, OPCODE 00) 

This command performs a data pattern test on the 
Sector Buffer. The Host does not preserve the 



contents of the Sector Buffer.The following is the 
RAM Diagnostic command block format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 7 


Operation Code 00 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 


X 


X 


X 


X 


X 


X 


X 



Possible Error Codes 

No Error or RAM failure. 



Action 

Test the Sector Buffer by writing and reading various 
patterns into it. 



Winchester Board Products 



6-79 



o 

-ik 

o 
o 

X 

o 



DRIVE DIAGNOSTIC 
(CLASS 7, OPCODE 03) 

This command tests both the drive and the drive-to- 
Controller interface. The WD1002S-SHD Winchester 
Disl< Controller sends Restore to Track and Seel< 
commands to the selected drive and verifies Sector 
of all tracks on the disk. The WD1002S-SHD 



Winchester Disk Controller does not perform any write 
operations during this command; the disk is 
understood to be previoulsy formatted. The following 
is the Drive Diagnostic command block format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 7 


Operation Code 03 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


R 











Fast Step Option 



Possible Error Codes 

No Error, Invalid Command, Drive Not Ready, Seek 
Error, Format Error, or Write Fault. 

Action 

Recalibrate the target drive, then scan ID on each 
track. This command does not write to the disk, nor 

CONTROLLER DIAGNOSTIC 
(CLASS 7, OPCODE 04) 

This command initiates the WD1002S-SHD self-test 
diagnostic routine. The WD1002S-SHD tests its Con- 
trol Processor, Sector Buffer, ECC circuitry, Win- 
chester Controller/Formatter, and the checksum of the 



does it send any sector data to the Host. The effect 
of the Drive Diagnostic command is to verify that at 
least one sector header can be read on each track. 
It does not report an error when it encounters a track 
that has been formatted as a 'Bad Track', 'Bad-Track- 
With-Alternate', or 'Alternate Track'. 



Program Memory. The WD1002S-SHD does not 
access the drive during this command. The follow- 
ing is the Controller Diagnostic command block 
format. 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 7 


Operation Code 04 


1 


LUN 


X 


X 


X 


X 


X 


2 


X 


X 


X 


X 


X 


X 


X 


X 


3 


X 


X 


X 


X 


X 


X 


X 


X 


4 


X 


X 


X 


X 


X 


X 


X 


X 


5 


X 


X 


X 


X 


X 


X 


X 


X 



Possible Error Codes 

No Error, ROM Failure, RAM Failure, or ECC Hard- 
ware Failure. 



Action 

Calculate a checksum for the program ROM, test the 
Control Processor, test the Sector Buffer, and test the 
ECC hardware. This command does not access any 
disk drive. 



6-80 



Winchester Board Products 



READ LONG 

(CLASS 7, OPCODE 05) 

This command transfers the target sector and four 
bytes of data ECC to the Host. If an ECC error occurs 
during Read, the WD1002S- SHD does not attempt to 
correct the data field. The command is useful in 



recovering data from a sector that contains an uncor- 
rectable ECC error. It is also useful during diagnostic 
operations. 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 7 


Operation Code 05 


1 


LUN 


Logical Sector Address Bits 16-20 


2 


Logical Sector Address Bits 8-15 


3 


Logical Sector Address Bits 0-07 


4 


Sector Count 


5 


R 











Fast Step Option 



R Retry Disable: 



D 

o 
o 

lO 

v> 

0) 

X 

o 



= No Disable 

1 = Disable 



Possible Error Codes 

No Error, Invalid Command, Invalid Sector Address, 
Drive Not Ready, Seek Error, Bad Track, Illegal (direct) 
Access To An Alternate Track, Alternate Track Not 
Marked As Alternate, Address Mark Not Found, or 
Write Fault. 

WRITE LONG 

(CLASS 7, OPCODE 06) 

This command transfers a sector of data and four 
appended ECC bytes to the disk drive. During this 
write operation, the Host supplies the four ECC bytes 
instead of the usual hardware generated ECC bytes. 



Action 

Read the specified number of consecutive sectors 
and their ECC bytes beginning with the specified sec- 
tor contained in the Control Byte. There are four ECC 
bytes per sector. This command is only useful for 
diagnostic purposes. 



This command is useful only for diagnostic routines. 
The following is the Write Long command block 
format: 





BITS 


BYTES 


7 


6 


5 


4 


3 


2 


1 








Command Class 7 


Operation Code 06 


1 


LUN 


Logical Sector Address Bits 16-20 


2 


Logical Sector Address Bits 8-15 


3 


Logical Sector Address Bits 0-07 


4 


Sector Count 


5 


R 











Fast Step Option 



R Retry Disable: 



= No Disable 

1 = Disable 



Winchester Board Products 



6-81 



a 

o 
o 

in 

o 



Possible Error Codes 

No Error, Invalid Command, Invalid Sector Address, 
Drive Not Ready, Seek Error, Bad Track Illegal (direct) 
Access To Alternate Track, Alternate Track Not 
Marked As Alternate, Address Mark Not Found, or 
Write Fault. 



Action 

Write the specified number of consecutive sectors 
beginning with the specified sector. Following each 
sector, the Host sends four ECC bytes to the 
WD1002S-SHD Winchester Disk Controller to be writ- 
ten to the disk as the ECC bytes for the sector. This 
command is useful for diagnostic purposes. It allows 
the generation of a sector containing a correctable 
ECC error. 



TIMING 

Figure 6 Illustrates a typical Host-Controller bus 
transfer, complete with Controller selection. 



DATA 
CONTROL 

sil 

BUSY 
REQ 

ACK 
1/0 

C/D 
MSG 








BYTE* 




#: 


> 


#3 


#4 


00 TERMINATES COMMAND 7 

#5 #6 }f 




^-"X 


'.^\ 


VALID V VALID V VALID V 
AND IF COMMAND HAS A DAI 


VALID V V 


T HAPPENS HERE^ 


VALID V VALID V\\ 


LER ADDRESS-^ 


lOFCOMM 


PA TRANSFER 1 


' ^ — STATUS 






■ 
















f / 










\ 


^ 










— 




















2 L. 


J 4 L 


- 


- 


- 


- 


/ / 




- 


- 






\m\ / 




\ 










\ 


y \ 


/ 




w 






































J 



FIGURE 6. TYPICAL HOST-CONTROLLER BUS TRANSFER TIIVIING 



6-82 



Winchester Board Products 



HOST/CONTROLLER SELECTION TIMING 

Prior to either command or data transfer, the Host 
must perform a handshake operati on in selecting the 
Controller. The Host first asserts SEL and places 
the Controller address bit on the bus (the address bit 
is preset to DBO at the factory but can be any bit from 
DBO to DB7 in a multiple-Controller environment). 

Afte r the controller recognizes Its address bit and 
SEL being asserted, it then asserts BUSY. During 
this selection phase, the Host takes full control of 
the data bus by ass erting O (I/O). Once the Con- 
troller has asse rted BUSY, the selection process is 
complete. SEL must be de-asserted by the Host at 
or before the first Command byte to the Controller. 
Figure 7 illustrates the Controller Select Timing. 
Figure 8 illustrates the Controller Select Timing Flow. 

NOTE 



No restriction on sequence of SEL and DADR fal- 
ling edges. Both must be low to ensure controller 
selection. 



DADR 



>260NS j 

« ^1 



< 520 NS 



NOTE: 

No restriction on sequence of SEL and DADR fall- 
ing edges. Both must be low to ensure controller 
selection. 



ISSUE 

(OPTIONAL) 

RESET 



o 

O 

o 

<p 

C/) 

X 

a 



SEND SELECT BIT 



SEND CONTROLLER ADDRESS BIT 



CONTROLLER SHOULD GO BUSY WITHIN 
520 nsec. 




FIGURE 8. 
CONTROLLER SELECT FLOW DIAGRAM 



FIGURE 7. CONTROLLER SELECT TIMING 



Winchester Board Products 



6-83 



D 

o 
o 

CO 

X 

o 



COMMAND MODE 

After Controller selection, the Host can transmit its 
first command. The Controller receives a command 
form the Host using a sequence of handshake 
recognition signals. The Controller asserts C (C/D) 
to notify the Host that It Is ready to receive a com- 
mand and assets O (I/O) to indicate that the dlrec- 
tion i s from the Host to the Controller. At this time, 
MSG Is In the de-asserted state. 

The Controller assert^ REQ w ithin 10 usee. After 
asserting O (I/O), C (C/D), and MSG is In the de- 
asserted state. The Host then answers by asserting 
ACK when It is ready to send a command byte to 
the Controller. The command byte must be stable on 
the bus within 250 nsec. of ACK being asserted 
and remain stable until the Contro ller d e-asserts 
REQ. After the Controller de-asserts REQ, the Host 
de-asserts ACK completing the handshake sequence 
for the first command byte. The complete handshake 
sequence must be repeated for each successive com- 
mand byte frqrn the H ost. Ta ble 9 lists the relation- 
ships of I/O, C/D, and MSG. 

TABLE 9. HOST BUS SIGNAL STATUS 



I/O 


C/D 


MSG 


BUS STATUS 


1 





1 


The Controller receives a 
command from the Host. 


1 


1 


1 


The Controller receives 
data from the Host. 





1 


1 


The Controller sends data 
to the Host. 








1 


The Controller sends an 
error status byte to the 
Host. 











The Controller informs the 
Host that It has completed 
the command in process. 



DATA TRANSFER 

Figures 9 and 10 illustrate the required timing for 
Host-to-Controller and Controller-to-Host data 
transfers respectively. These diagrams include the 
required handshake signals. Tables 10 and 11 provide 
the timing parameters for these diagrams. 



■tCY 



'RAL 



ACK 



'RAH 
<ARH — »| ^ »l |-«- 'ARL 

I I 1 



»i tADV !♦ ♦] !-•— 'RDH 

^ W/////////////M X 



FIGURE 9. 

HOST-TO-CONTROLLER 

DATA TRANSFER TIMING 



TABLE 10. 
HOST-TO-CONTROLLER 
TIMING PARAMETERS 



PARAMETER 


MIN* 


MAX* 


^CY 


1152 




tRALt 







Urh 


600 


840 


tpAHtt 







Url 


200 


448 


Udv 




375 


tpDH 








LEGEND: 



nsec 



If conditions in t and ft are met, then tcvtyp = 
1200 nsec and toy max = 1248 nssec. 
t If tRAL < 89 nsec, then no wait states are inserted. 
tt If tRAH < 97 nsec, then no wait states are inserted. 



6-84 



Winchester Board Products 





►- 




1 1 


'RAL 'RAH 


— 'arl »>j 




1^ 


'SUR 
-•H j^ ^ 'RDH 

DO.D7'/0( 


w/m 





STATUS BYTES 

After every command, the Controller sends two status 
bytes to the Host. The first byte of information con- 
tains the error status code for that command and the 
second byte contains all zeros, indicating that the 
command has been completed. Figure 11 Illustrates 
the timing sequence for Command Termination. 
Figure 12 illustrates the timing flow for sending and 
terminating a command, and Figure 13 illustrates 
Status Request Timing Flow. 



O 

O 
O 

C/) 

X 

a 



FIGURE 10. 

CONTROLLER-TO-HOST 

DATA TRANSFER TIMING 



TABLE 11. 
CONTROLLER-TO-HOST 
TIMING PARAMETERS 



PARAMETER 


MIN' 


MAX* 


^CY 


1152 




tpAlt 







Urh 


200 


448 


tpAHtt 







^RAL 


200 


848 


^SUR 


125 




^RDH 


152 





LEGEND: 

* nsec 

If conditions in f and ft are met, then tcvtvp = 

120 nsec and tcv max = 1248 nsec. 
t If tRAL < 497 nsec, then no wait states are 

inserted. 
tt If tpAH < 200 nsec, then no wait states are 

inserted. 



Winchester Board Products 



6-85 











BUSY 
1/0 

REQ 
ACK 

MSG 

C/D 

DX 








O 

o 








wwwwwwww 








TYP 440^8 T^'' 








n - 
















1 

1 
1 






1 
_l U 1 

— ► ■* — 


260^8 WD1002S-SHO 






























X LAST DATA BYTE Y STATUS BYTE Y 


^i x////////// 













FIGURE 11. COMMAND TERMINATION TIMING 



6-86 



Winchester Board Products 



SEND (NON-DATA TRANSFER) COMMAND 



SELECT CONTROLLER 



SET 6-BYTE COMMAND COUNTER 



NO 




REQUEST 
ACTIVE 



YES 



REQUEST, C/D = C, 1/0 = 



SEND COMMAND BYTE TO CONTROLLER 



DECREMENT BYTE COUNTER 




REQUEST. C/D = 0,1/0 = I 



YES 



REQUEST, C/D-C, 1/0. 
MESSAGE 



READ A BYTE 
■ S/B = 
j;0MMAND COMPLETED 



D 



FIGURE 12. 

COMMAND SEQUENCE 

TIMING FLOW DIAGRAM 



SEND REQUEST SENSE STATUS COMMAND 



SELECT CONTROLLER 




NO y REQUEST 
ACTIVE 



READ IN 4 SENSE BYTES 
(WAIT FOR REQUEST EACH TIME) 



READ COMMAND STATUS AND MESSAGE BYTES 



c 



DONE 



3 



FIGURE 13. 

REQUEST STATUS COMMAND 

TIMING FLOW DIAGRAM 

MISCELLANEOUS TIMING 

The following is a list of specific timing parameters 
that must be met for proper operation of the 
WD1002S-SHD: 

A. CONTROLLER RESET - P ower-On-Res et (POR) is 
less than 120 msec, and Reset (RST) is less 
than 120 usee. During either of these periods, the 
Host is inhibited from selecting the Controller. If 
selection is attempted, the Controller does not 
assert BUSY. 

B. SELECT TO C/D - After RST or POR, the Con- 
troller runs its internal diagnostic routines until it 
is selected by the Host, at which point the Con- 
troller exits the diagnostic routine being run. While 
in the diagnostic loop, the controlle r can t ake as 
long as 340 msec. After it asserts BUSY, before 
asserting C (C/D). However, once the Controller 
has left the diagnostic loop, no more than_80_usec. 
is re quired for the Controller to assert C (C/D) 
after BUSY is asserted. 

C. C/D TO FIRST REQ TIM!NG_PULSE - When the 
Cont roller first asserts C (C/D) until the first 
REQ pulse is asserted is typically 120 usee. 

D. WAIT STATE - One wait state equals 200 nsec. 

NOTE 

All SAS I protocol must be adhered to (i.e., a 
RE/ACK handshake must precede every byte 
transferred). 



a 

o 
o 
10 

<^ 

C/) 

X 

a 



Winchester Board Products 



6-87 



6-88 Winchester Board Products 



WESTERN DIGITAL 

CORPORATION 

WD1002C-WX2 
Winchester Controller Board 



O 
O 

O 

X 



FEATURES 

• IBM XT WINCHESTER CONTROLLER 
EMULATION, IBM PC HOST INTERFACE. 

• EITHER 50 PIN EXTERNAL CONNECTOR 
OR 62 PIN EXTERNAL CONNECTOR. 

• SUPPORTS MULTIPLE STEPPING RATES, 
INCLUDING 18 USEC. 

• DYNAMICALLY CONFIGURABLE BIOS ROM 

• SUPPORTS TWO ST506 TYPE DRIVES WITH UP 
TO 1024 CYLINDERS AND 16 R/W HEADS. 

• ERROR DETECTION AND CORRECTION ON 
DATA FIELD USING 32-BIT ECC POLYNOMIAL 



AUTOMATIC FORMATTING. 

WD10C20-05 SELF-ADJUSTING LSI DATA 
SEPARATOR. 

SECTOR INTERLEAVE CAPABILITY. 

OVERLAPPED SEEK CAPABILITY ON 
BUFFERED-STEP DRIVES. 

SUPPORTS IMPLIED SEEKS ON ALL 
COMMANDS. 

DMA TRANSFER CAPABILITY. 



DESCRIPTION 

The WD1002C-WX2 is an IBM XT compatible Win- 
chester controller board based on the design of the 
WD1002S-WX2. The WD1002C-WX2 is a 10 inch x 3.90 
inch board and includes either a 50 pin external con- 
nector or a 62 pin external connector. The connector 
allows the user to configure a system easily with 
external Winchester drives. The board contains one 
internal connector and one external connector and 
a maximum of 2 drives can be attached. The 50 pin 
external connector will control one external drive con- 
figured as Drive or Drive 1. The 62 pin connector car- 
ries all the signals required to control up to two 
external drives. In either case, the maximum number 
of drives supported is two, so if the 62 pin connector 
has 2 drives attached, no drive may be attached to 
the internal connector. 



The WD1002C-V\/X2 supports drives with up to 16 
heads and supports the following stepping rates: 3 
msec, 18 ^isec, 30 jisec, 45 j^sec, 60 ^sec, 75 f/sec and 
210 Msec. 

The WD1002C-WX2 interfaces directly to the Host I/O 
via the IBM PC bus. Data transfer to and from the con- 
troller can be either programmed I/O or DMA. 

The BIOS is dynamically configurable at the time of 
formatting the drive. The user has two options: to use 
a resident set of drive tables, or to define through the 
keyboard a new set of customized tables. 



Winchester Board Products 



6-89 



6-90 Winchester Board Products 



WESTERN DIGITAL 

CORPORATION 

WD1002S-WX2 Winchester Disk Controller 



FEATURES 

8-BIT BI-DIRECTIONAL BUS HOST INTERFACE. 

IBM XT WINCHESTER CONTROLLER 
EMULATION, IBM PC HOST INTERFACE 

WD10C20 WINCHESTER DATA SEPARATOR AND 
WRITE PRECOMPENSATION DEVICE 

WD11C00-17 LOGIC ARRAY 

DATA RATES UP TO 5 MBITS/SEC 

CONTROLS UP TO 2 DRIVES USING SEAGATE 
TECHNOLOGY ST506/ST412 

SUPPORTS DRIVES OF ANY CONFIGURATION 
UP TO 1024 CYLINDERS AND 16 R/W HEADS 
WITH THE WD1015-24 OR 8 R/W HEADS WITH 
THE WD1015-14 

THE CONTROLLED DRIVES NEED NOT BE OF 
THE SAME CAPACITY OR CONFIGURATION 

ERROR CORRECTION ON DATA FIELD ERRORS, 
CRC ID FIELD VERIFICATION 

32-BIT ECC POLYNOMIAL FOR ERROR 
DETECTION AND CORRECTION 

READ AND WRITE LONG COMMANDS FOR 
CHECKING ERROR CORRECTION CIRCUITRY 

SELECTABLE AUTOMATIC RETRIES ON ALL 
ERRORS 

AUTOMATIC RESTORE AND RE-SEEK ON ALL 
SEEK ERRORS 

AUTOMATIC FORMATTING 

512 BYTES PER SECTOR 

SECTOR INTERLEAVE CAPABILITY 

MULTIPLE SECTOR READS AND WRITES 

OVERLAPPED SEEK CAPABILITY ON 
BUFFERED-STEP DRIVES 

SUPPORTS IMPLIED SEEKS ON ALL 
COMMANDS 

INTERNAL DIAGNOSTICS 

DMA TRANSFER CAPABILITY 

SUPPORTS INTERRUPTS, INTERRUPT 
REQUESTS, AND DMA REQUEST SHARING 

INCLUDES SOCKET FOR USER SUPPLIED 2716, 
2732, OR 2764 ROM 

BIOS AVAILABLE 



DESCRIPTION 

The WD1002S-WX2 is a stand-alone, general purpose 
Winchester Disk Controller. The WD1002S-WX2 inter- 
faces up to two Winchester disk drives and a Host 
Processor, e.g. an IBM XT. 

The Winchester interface conforms to the Seagate 
Technology ST506/ST412 interface. All necessary 
receivers and drivers are included on the board, allow- 
ing direct connection to the disk drive(s). 

A separate computer access port enables com- 
munications between the Host and disk controller. 
An 8-bit bi-directional bus and appropriate control 
signals comprise this port. Disk read or write data, 
status information, and command parameters are 
transferred via this bus. An on-board data buffer 
allows bus transfers to be executed independently 
of the drive's data transfer. 

ARCHITECTURE 

The WD1002S-WX2 architecture is based on a pro- 
prietary chip set consisting of the WD11C00-17, 
WD1010A-05, WD10C20, and WD1015. As illustrated 
in Figure 1, the WD1002S-WX2 consists of the follow- 
ing components: 

Bi-directional Control/Data Bus 

Address Decoding Logic 

Configuration Switches 

Basic Input/Output System (BIOS) ROM 

WD11C00-17 

WD10C20 

Sector Buffer RAM 

WD1010A-05 

WD1015 

Reset Logic 

BI-DIRECTIONAL CONTROL/DATA BUS 

The 8-bit, bi-directional bus transmits addresses, com- 
mands, data, and status information. This bus links 
the WD1002S-WX2 to the Host. Specifically, this bus 
transmits data between the Host and Sector Buffer 
RAM. 

ADDRESS DECODING LOGIC 

The purpose of this logic is to decode a valid device 
address from the Host. 

CONFIGURATION JUMPERS 

These jumpers configure the WD1002S-WX2 for dif- 
ferent disk drive capacities. 



O 

o 
o 

t 

X 

lO 



Winchester Board Products 



6-91 



a 

o 

o 

X 




FIGURE 1. WD1002S-WX2 FUNCTIONAL BLOCK DIAGRAM 



6-92 



Winchester Board Products 



BIOS ROM 

The Host, after powering up, interrogates its ports to 
determine what devices are connected. The Host uses 
information suppiied by the BiOS ROiVl to perform an 
install operation. Then, during normal operation, the 
BIOS operates much like a driver that is resident in 
the Host's memory space. The BIOS ROM is 
addressed at Host memory locations C8000 - C8FFF. 
The BIOS is addressed by the AO through A19 bus. 
Outputs to the Host are via the Intraboard Com- 
mand/Status bus (BDO through BD7) and Host Inter- 
face Data/Command bus (DO through D7). 

WD11C00-17 

The WD11C00-17 incorporates several functions in a 
single package. Implementation of these functions 
occurs by combining random logic and specialized 
circuits. The WD11C00-17 contains the following 
circuits: 

Status ports 

Read and write ports 

Sector Buffer RAM addressing and control 

ECO 

Reset timing 

The WD11C00-17 connects directly to the Host Inter- 
face Data/Command and Intraboard Command/Data 
(AD0-AD7) buses. 

WD10C20 

The WD10C20 performs phase-locked loop data syn- 
chronization on read data from the Winchester drives. 
This device also conditions write data to be recorded 
on the disk. The WD10C20 includes both frequency 
and phase detection. Zero phase error start-up cir- 
cuitry eliminates problems due to asymmetry. The 



WD10C20 requires no adjustments and contains all 
data synchronization and write precompensation cir- 
cuitry in a single device. 

SECTOR BUFFER RAM 

The Sector Buffer RAM is a 2K x 8 RAM. The Sector 
Buffer allows Host data transfers independent of the 
actual drive data transfer rate. The Sector Buffer tem- 
porarily stores the following information: 

Sector data during Read and Write Commands 

Disk format information during a Format 

Command 

Drive characteristics during a Set Parameters 

Command 

WD1010A-05 

The primary function of the WD1010A-05 is to con- 
trol data transfers between the disk and the Sector 
Buffer. Data transfers take place after the WD1015 
Buffer Manager Control Processor positions the 
selected head over the desired track. The WD1010A-05 
receives the parameters and commands from the 
WD1015 via the ADO through AD7 bus. The 
WD1010A-05 interprets the parameter or command, 
determines which sectors are involved, and whether 
a read, write, or format function is required. 

WD1015 

The WD1015 manages and controls all commands 
and communications between the Host and 
WD1010A-05. The WD1015 controls ECC and CRC 
functions. 

There are two versions of the WD1015. Table 1 
describes the differences between the two versions 
of the WD1015. The acronym WD1015 refers to both 
versions. When a specific reference is made to a 
specific version, the appropriate acronym is used. 



g 

o 
o 
to 

CO 

k 

X 

lO 



Table 1. WD1015 DESCRIPTION 



FUNCTION 


WD1015-14 


WD1015-24 


REMARKS 


Execution of automatic 
self-test after Reset 
command or power-up 


Yes 


No 




Supports 16 heads 


No 


Yes 


The WD1015-14 supports up to eight heads. The 
WD1015-14 uses the REDUCED WRITE CURRENT 
(RWC) signal. The WD1015-24 supports up to 16 
heads. The WD1015-24 uses the RWC pin on J1 
as HEAD SELECT 3 (HS3). Refer to Table 10 for 
further details. 


3.5 seconds time-out on 
single track steps 


No 


Yes 


3.5 time-out allows removable/sen/o drives time to 
create servo map. WD1015-14 allows 1 second. 


Bit 4 of opcode In 
Command Control 


Valid 


Don't care 


Refer to Figure 2 for further details. 


Step rates 






Refer to Table 8 for further details. 


Format Bad Track 






Refer to Command Section for further details. 



Winchester Board Products 



6-93 



o 

o 
o 

c/) 
X 



RESET LOGIC 

The Reset Logic Initializes the Internal circuitry of the 
WD1002S-WX2 during the power-up process or 
a lo w voltage cond ition. The Reset Lo gic also disable s 
the WRITE GATE signal. Disabling WRITE GATE 
prevents writing spurious data to the disk drive dur- 
ing power up, power down or a low voltage conditon. 

INTERFACE CONNECTIONS 

The WD1002S-WX2 has four on-board connectors for 
user application. 

P1 Host interface: 62-pin IBM PC connpatible 

card edge connector. 

J1 Drive control: 34-pin dual row header con- 

nector daisy-chained to two drives. The 



J2,J3 



control signals at the second drive from 
the WD1002S-WX2 (no more than a total 
length of 10 feet or 3 meters) are ter- 
minated with a 220 ohm resistor to + 5V 
and a 330 ohm resistor to ground. 

Drive data: 20-pin dual row header connec- 
tors, radially connected each to its own 
drive. 



HOST INTERFACE 

Connector P1 pins A1 through A31 are on the com- 
ponent side of the board and B1 through 831 are on 
the artwork side. Table 2 describes the Host interface 
Connector, PI. 



TABLE 2. HOST INTERFACE CONNECTOR (PI) PIN DESCRIPTION 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


A1 




NOT CONNCECTED 






A2 
thru 
A9 


D7 
thru 
DO 


DATA 7 

thru 

DATAO 


I/O 


8-Bit, tri-state, bi-directional bus. It is used to 
transmit data between the Host and Sector Buffer, 
and Command Block to the WD1015, status and 
drive configuration to the HosL The BIOS transmits 
parameter information and commands to the Host 
via this bus. 


A10 




NOT CONNECTED 






All 


AEN 


ADDRESS ENABLE 


1 


AEN Is asserted during a DMA mode of operation 
making the I/O ports 320 hex thru 323 hex inaccessi- 
ble to the Host. Data transfers and intrabus con- 
trol is initiated by asserting DACK3. The BIOS 
ROM can still be addressed via A0-A19. 


A12 
thru 
A31 


A19 
thru 
AC 


ADDRESS BUS 
A19 thru AO 


1 


AO thru A9 are used during programmed I/O mode 
of operation to address ports 320 hex thru 323 hex. 
They are inhibited during DMA by AEN. AO thru A19 
addresses the BIOS ROM regardless of the state 
of AEN. 


81 


GND 


GROUND 






82 


RST 


RESET 


1 


When asserted, RST places the WD1002S-WX2 into 
its initial power-up state. 


83 


-1-5VDC 


-hSVDC 




-hSVDC 


84 


IRQ2 


INTERRUPT 
REQUEST 
LEVEL 2 





The WD1002S-WX2 asserts IRQ2 to interrupt the 
Host upon the completion of a command. Use of 
IRQ2 is jumper selectable. Use of IRQ5 is standard. 
Refer to Table 10 for further details on jumper selec- 
table options. 


85 

thru 

88 




NOT CONNECTED 






89 


+ 12VDC 


-H2VDC 




-M2VDC 


BIO 


GND 


GROUND 






811 




NOT CONNECTED 







6-94 



Winchester Board Products 



TABLE 2. HOST INTERFACE CONNECTOR (P1) PIN DESCRIPTION (CONT'D.) 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


B12 


MEMR 


MEMORY READ 


1 


The Host , to read the BIOS ROM places the address 
on AO thru A19, asserts MEMR and receives the 
data via DO thru D7 data bus. 


B13 


low 


I/O WRITE 


1 


The Host or DMA controller asserts lOW when a 
data byte is to be written to the WD1002S-WX2. 


B14 


lOR 


I/O READ 


1 


The Host or DMA controller asserts lOR when a 
data or status byte is to be read from the 
WD1002S-WX2. 


815 


DACK3 


DMA 

ACKNOWLEDGE 
CHANNEL 3 


1 


The DMA controller asserts DACK3 in response 
to DRQ3 sent by the WD1002S-WX2. DACK3 en- 
ables DMA data transfer, bypassing port 320 which 
was disabled by AEN. 


816 


DRQ3 


DMA 

REQUEST 
CHANNEL 3 





WD1002S-WX2 asserts DRQ3 to inform the DMA 
controller that data is available for transfer. 


817 
thru 
822 




NOT CONNECTED 






823 


IRQ5 


INTERRUPT 
REQUEST 
LEVEL 5 





The WD1002S-WX2 asserts IRQ5 to interrupt the 
Host upon the completion of a command. 


824 
thru 
828 




NOT CONNECTED 






829 


+ 5VDC 


+ 5VDC 




+ 5VDC 


830 




NOT CONNECTED 






831 


GND 


GROUND 







DRIVE INTERFACE 

DRIVE CONTROL 

Control signals are common to all drives and are 
daisy-chained to the drives from a single connector, 



J1. To terminate the control signals properly, the last 
drive in the daisy-chain must have a 220/330 ohm 
resistor pack installed. Table 3 describes the drive 
control connector, J1. 



D 

_^ 
o 
o 

IV3 
CO 

X 



Winchester Board Products 



6-95 



TABLE 3. DRIVE CONTROL CONNECTOR (J1) PIN DESCRIPTION 



O 

o 
o 
to 

CO 
X 

IN3 



SIG. 
GND. 


SIG. 
PIN 


MNEMONIC 


SIGNAL NAME 


I/O 


DESCRIPTION 


1 


2 


RWC/HS3 


REDUCE 
WRITE 

CURRENT/HEAD 
SELECT 3 





The WD1015-14 allows this pin to be used as the RWC 
pin. The WD1015-24 uses this pin as HS3. Refer to 
Table 10 for further details. RWC is used by the drive 
to reduce the write current on the inner cylinders. This 
lessens the bit shift caused by the greater bit density 
on these cylinders. RWC is asserted when the speci- 
fied cylinder is reached. HS3 is one of four Head 
Select signals decoded by the drive to select one of 
16 R/W heads. 


3 


4 


HS2 


HEAD 
SELECT 2 





HS2 is one of three (or four) Head Select signals de- 
coded by the drive to select one of eight (or 16) RA/V 
heads. 


5 


6 


WG 


WRITE GATE 





WG is asserted when valid data Is to be written. It is 
used by the drive to enable the write current to the head. 
WD1002S-WX2 de-asserts this signal when a WF is 
detected. Circuitry is included to ensure the output does 
not glitch during power on, power down or power 
failure. 


7 


8 


SC 


SEEK 
COMPLETE 


1 


SC informs the WD1002S-WX2 that the selected head 
has reached the desired cylinder and has stabilized. 
Since SC is not checl<ed after a Seek Command, 
overlapped seeks are allowed. 


9 


10 


TKOOO 


TRACK 000 


1 


The drive asserts this signal when the heads are posi- 
tioned over the outermost cylinder, cylinder 0. 


11 


12 


WF 


WRITE FAULT 


1 


WF is asserted by the drive when a write error 
occurs. The command in progress aborts and no other 
comand can be executed while this signal is asserted. 


13 


14 


HSO 


HEAD 
SELECT 





HSO is one of three (or four) Head Select signals de- 
coded by the drive to select one of eight (or 16) R/W 
heads. 


15 




GND 


GROUND 








16 




NOT CONNECTED 






17 


18 


HS1 


HEAD 
SELECT 1 





HS1 is one of three (or four) Head Select signals 
decoded by the drive to select one of eight (or 16) RA/V 
heads. 


19 


20 


INDEX 


INDEX PULSE 


1 


This signal indicates the start of a track. It is used as 
a sychronization point during formatting and as a time 
out mechanism for retries. This signal pulses once for 
each revolution of the disk. 


21 


22 


DRDY 


DRIVE READY 


1 


The drive asserts this signal when the motor is up to 
speed. No Read or Write commands can be performed 
if this signal is not asserted. 



6-96 



Winchester Board Products 



TABLE 3. DRIVE CONTROL CONNECTOR (J1) PIN DESCRIPTION (CONT'D.) 



SIG. 
GND. 


SIG. 
PIN 


MNEMONIC 


SIGNAL NAME 


I/O 


DESCRIPTION 


23 


24 


STEP 


STEP PULSE 





STEP along with DIRIN positions the heads to the 
desired cylinder. STEP pulses the stepping motor at 
the rate specified by the SP bits in the Command 


Block and is controlled by the WD1015. DIRIN speci- 
fies the direction. 


25 


26 


DSELO 


DRIVE SELECT 





DSEL is the decoded output of the SDH Register 
within the WD1010A-05, latched and sent to the drive 
by the WD1015 to select drive 0. 


27 


28 


DSEL1 


DRIVE SELECT 1 





DSEL 1 is the decoded output of the SDH Register 
within the WD1010A-05, latched and sent to the drive 
by the WD1015 to select drive 1. 


29, 
31 


30, 
32 




NOT CONNECTED 






33 


34 


DIRIN 


DIRECTION IN 





DIRIN determines the direction the RA/V heads take 
when stepped. Asserted = in, de-asserted = out. 



D 

_i 
o 
o 

C/) 

X 

ro 



DRIVE DATA CONNECTOR 

The data is differential in nature and must be con- 
nected to each drive with its own cable, drive to J2 
and drive 1 to J3. It should be a flat ribbon cable, 



or twisted pair, less than 3 meters (10 feet) in length. 
The connector is a 20-pin vertical header on 0.25 cen- 
timeter (0.1 inch) center. Table 4 describes the drive 
data connectors, J2 and J3. 



TABLE 4. DRIVE DATA CONNECTORS - J2, J3 



SIG. 


SIG. 






GND. 


PIN 


I/O 


SIGNAL NAME 




1 




NC 


2 






GND 




3 




NC 


4 






GND 




5 




NC 


6 






GND 




7 




NC 


8 






GND 




9 




NC 




10 




NC 


11 






GND 


12 






GND 




13 





-1- MFM Write Data 




14 





- MFM Write Data 


15 






GND 


16 






GND 




17 


1 


-1- MFM Read Data 




18 


1 


- MFM Read Data 


19 






GND 


20 






GND 



COMMAND DESCRIPTION 

This section provides a detailed description of the 
Command Block format and function of the 19 com- 
mands supported by the WD1002S-WX2. 



Fourteen of the commands are operational and five 
are diagnostic. Table 5 lists a summary of the 
commands. 



Winchester Board Products 



6-97 



o 

o 
o 

lO 
CO 



X 

lO 



TABLE 5. COMMAND SUMMARY 


COMMAND 


PARAMETERS (Refer to Figure 2) 


OP CODE 


DRV 


HD 


CYL 


SEC 


BLK/INT 


R1 


R2 


STEP 


TEST DRIVE READY 


00 


V 


n 


n 


n 


n 


n 


n 


n 


RECALIBRATE 


01 


V 


n 


n 


n 


n 


V 


n 


n 


READ STATUS OF 
LAST OPERATION 


03 


V 


n 


n 


n 


n 


n 


n 


n 


FORMAT DRIVE 


04 


V 


V 


V 


DR 


V(INT) 


V 


n 


V 


VERIFY SECTORS 


05 


V 


V 


V 


V 


V(BLK) 


V 


V 


V 


FORMAT TRACK 


06 


V 


V 


V 


DR 


V(INT) 


V 


n 


V 


FORMAT BAD TRACK 


07 


V 


V 


V 


DR 


V(INT) 


V 


n 


V 


READ SECTOR 


08 


V 


V 


V 


V 


V(BLK) 


V 


V 


V 


WRITE SECTORS 


OA 


V 


V 


V 


V 


V(BLK) 


V 


n 


V 


SEEK 


OB 


V 


V 


V 


DR 


n 


V 


n 


V 


INITIALIZE DRIVE 
PARAMETERS 


OC 


V 


n 


n 


n 


n 


n 


n 


n 


READ ECC BURST 
ERROR LENGTH 


OD 


V 


n 


n 


n 


n 


n 


n 


n 


READ SECTOR BUFFER 


OE 


n 


n 


n 


n 


n 


n 


n 


n 


WRITE SECTOR BUFFER 


OF 


n 


n 


n 


n 


n 


n 


n 


n 


EXECUTE SECTOR 
BUFFER DIAGNOSTIC 


EO 


n 


n 


n 


n 


n 


n 


n 


n 


EXECUTE DRIVE 
DIAGNOSTIC 


E3 


V 


n 


n 


n 


n 


V 


n 


V 


EXECUTE CONTROLLER 
DIAGNOSTIC 


E4 


n 


n 


n 


n 


n 


n 


n 


n 


READ LONG 


E5 


V 


V 


V 


V 


V(BLK) 


V 


n 


V 


WRITE LONG 


E6 


V 


V 


V 


V 


V(BLK) 


V 


n 


V 



LEGEND 

V 
DR 



n 

INT 

BLK 



Must be a valid parameter 

Not used but must be within a valid parameter 

range 

Not used (should be for future compatibility) 

Interleave 

Block Count 



I/O PORT DESCRIPTION 

There are four contiguous I/O ports addressed 320 
hexidecimal through 323 hexidecimal. Each port is 
bi-directional. The functions of the I/O ports are listed 
In Table 6. These ports are used for all communica- 
tion between the Host and Controller. 



TABLE 6. I/O PORT DESCRIPTIONS 



ADDRESS 


READ PORT FUNCTION 


WRITE PORT FUNCTION 


320 


READ DATA 


WRITE DATA 


321 


READ WD1002S-WX2 HRDWR STATUS 


WD1002S-WX2 RESET* 


322 


READ DRIVE CONFIGURATION INFO 


WD1002S-WX2 SELECT 


323 


Not Used 


WRITE DMA AND INTERRUPT MASK 
REGISTER 



•NOTE 

The WD1015-14 automatically executes self-tests after either a Reset command or upon power-up. The WD1015-24 
DOES NOT automatically execute self-test after either a Reset command or upon power-up. A WD BIOS performs 
an Execute Controller Diagnostic command as part of the install sequence after power-up regardless of the version 
of WD1015 on-board. If the Host software interrogates WD1015-24 after a Reset; the WD1015-24 returns good status. 
The Host must issue an Execute Controller Diagnostic command to perform the WD1015-24 self-test. 



6-98 



Winchester Board Products 



PORT 320 

This is a bi-directional path over which data, com- 
mands, parameters, and status are passed. 

PORT 321 

The Host reads this port to interrogate the hardware 
status. This status byte can be read at any time, 
including command execution. The status bits are 
identified in Table 7. 

TABLE 7. HARDWARE STATUS 



BIT 


7 


6 


5 4 3 2 


1 





d 


d 


IRQ DRQ BSY C/D 


I/O 


REQ 



d Not used 

IRQ Interrupt Request. Assertion (set to 1) 
signifies that an interrupt is pending. 

DRQ DMA request bit. Assertion (set to 1) 

signals the Host that the WD1002S-WX2 is 
ready for a DMA transfer to take place. The 
direction of the transfer is defined by the 
I/O bit. 

BSY Busy bit. Assertion (set to 1) signals the 
Host that the WD1002S-WX2 is busy 
executing a command and is unable to 
accept another command. 

C/D Control/Data. Tells the Host which type of 
transfer the WD1002S-WX2 is expecting. 1 
= command or status byte. = data. 

I/O Input/Output. Identifies the direction of 
transfers between the Host and WD1002S- 
WX2. The terms input and output are 
relative to the Host. 1 = input, = output. 

REQ Request bit. A handshake signal for data 
transfers between the Host and WD1002S- 
WX2. The WD1002S-WX2 asserts (sets to 1) 
this bit when it is ready for data to be 
transferred between it and the Host. REQ 
must be valid for every byte transferred to 
the Host. 

The Host writes to this port to generate a MR (Master 
Reset) on the WD1002S-WX2. When writing to this 
port, the data byte is ignored. 

Resetting a WD1002S-WX2 with a WD1015-14 causes 
automatic execution of a self-test. Automatic execu- 
tion of self-test does not occur with the WD1015-24. 
If the Host software interrogates WD1015-24 after a 
Reset; the WD1015-24 returns good status. The Host 
must issue an Execute Controller Diagnostic com- 
mand to perform the WD1015-24 self-test. 

PORT 322 

Reading Port 322 returns a 4-bit drive configuration 
code in bits through 3. The two least significant bits 
correspond to drive 0, the two most significant bits 



to drive 1. The configuration of these bits is 
established with jumpers on the controller at SW1. 
Western Digital sets the configuration jumpers to one. 
Table 11 shows how to set them up for a specific 
drive. 

The two bits associated with each drive is capable 
of addressing one of four different configuration 
tables. Both drives can address the same or different 
tables. The table required by the drive is determined 
by its formatted capacity. Table = 5MB, 1 = 24MB, 
2 = 15MB, 3 = 10MB (default table) with 62-000042- 
01 and 62-000042-11 WD BIOS. Table = 20MB, Table 
1 = 10MB, Table 2 = 20MB, Table 3 = 10MB with 
62-000042-12 WD BIOS. 

The parameters established by these tables are: 

Number Of Cylinders 

Number Of Heads 

The Starting Cylinder For RWC (Reduced 

Write Current). 

The Starting Cylinder For Write Precomp 

Maximum Correctable Error Burst Length 

Retries Allowed, Stable or Immediate ECC 

Correction, Step Rate 

Writing to port 322 selects the WD1002S-WX2, sets 
the Busy bit in the Status Register and prepares it 
to receive a command. When writing to port 322, the 
data byte is ignored. 

PORT 323 

Reading this port has no function. 

Writing to this port controls the enabling of the inter- 
rupt and DMA request signals to the Host. The bits 
in this port are defined as follows: 



BIT 


7 


6 


5 


4 3 


2 1 


d 


d 


d 


d d 


d IRQEN DRQEN 



IRQEN Interrupt Request Enable. When asserted 
(set to one), enables interrupts to the Host. 

DRQEN DMA Request Enable. When asserted (set 
to one), enables DMA requests to the Host. 

COMMAND BLOCK 

The Host first selects the WD1002S-WX2 by asser- 
ting l/OW while at the same time addressing port 
322 with the AO through A19 address bus. The 
WD1002S-WX2 then asserts the BSY (BUSY) bit in the 
Status Register. The Host by asserting I/OR and 
addressing port 321 reads the status, finding REQ 
asserted transmits the first byte of the six byte Com- 
mand Block to the WD1015. REQ is de-asserted at 
the end of the first byte transfer. REQ must be re- 
asserted for the second byte of the Command Block 
transfer. Assertion and de-assertion of REQ must 
occur for each byte transferred. Figure 2 defines the 
bytes within the Command Block. 



D 

o 
o 

NJ 
C/) 

X 



Winchester Board Products 



6-99 



o 

o 
o 
ro 

lO 







BITS 


BYTE 


7 


6 


5 


4 


3 


2 


1 








OP CODE 


1 





D 





HEAD NUMBER 


2 


CYL NUMBER MSB 





SECTOR NUMBER 


3 


CYLINDER NUMBER LSB 


4 


BLOCK COUNT OR INTERLEAVE 


5 


R1 


R2 











SP 


SP 


SP 



OP Code: 



NOTE 



FIGURE 2. COMMAND BLOCK DESCRIPTION 

Operation Code identifies tfie type and function of tlie command. Bits 7, 6, and 5 designate 
whether the command is operational (0) or diagnostic (5). Bits 4 through select the func- 
tion of the command, i.e. Read, Write, etc. 



The WD1015-24 firmware ignores bit four of byte (op code). 

D Drive number, selects one of two drives zero or one. 



Head Number 

Cylinder Number 
MSB and LSB 

Sector Number 

Block Count or 
Interleave 



R1 



R2 



SP 



Designates the head to be used on the selected drive. through 15. Selection of heads 
8 through 15 requires WD1015-24. 

Designates the cylinder containing the sector(s) to be used by the command. through 
1024. 

Specifies the starting sector used by the command. 

Block count specifies the number of sectors to be used by a Read, Write, Read Long, 
or Write Long command. A block count of zero equals 256 sectors. Interleave is used 
by the Format commands. The maximum interleave is equal to the sectors-per-track minus 
one. 

General disk error retry disable bit. R1 controls the retry for all errors except a Data ECC 
error. With R1 asserted, the WD1002S-WX2 makes no attempt to retry an error operation. 
Instead, it aborts the command and sets the appropriate status in the Status Register. 
Because the disk is soft sectored, an ID field error may cause the WD1002S-WX2 to per- 
form two retries. With R1 de-asserted, the WD1002S-WX2 retries the operation approx- 
imately ten times before aborting the command and setting the status bit. In the case 
of an ID Not Found Error, the WD1002S-WX2 does' a restore to track zero and seeks back 
to the desired track after the first ten tries and then makes ten more tries before abor- 
ting and setting the error status. 

ECC Error retry bit. With R2 = 1, an attempt is made to correct the error on the first 
syndrome. R2 = there must be two consecutive like syndromes before an attempt is 
made to correct the error. 

The Step Code is used to select the rate at which step pulses are issued to the drive. 
Table 8 defines the rates corresponding to each step pulse code. 



6-100 



Winchester Board Products 



TABLE 8. STEPPING RATE CODES 


BITS 


STEPPING RATES 


2 


1 





WD1015-14 


WD1015-24 











3 msec, per step* 


3 msec, per step* 








1 


3 msec, per step 


45 /iSec. per step 





1 





3 msec, per step 


60 Msec. per step 





1 


1 


3 msec, per step 


18 fisec. per step 


1 








200 /isec. per step 


210 fisec. per step 


1 





1 


70 fisec. per step 


75 /isec. per step 


1 


1 





3 msec, per step 


30 fisec. per step 


1 


1 


1 


3 msec, per step 


18 ^(sec. per step 



*This is the preferred 3 msec, step code. 

TEST DRIVE READY (OP CODE 00) 

This command seiects the drive specified by the 

DRV b i t in t he Command Block and interrogates the 

DRDY, WF. and SC signals returned by that drive. If 

WF and SC are de-asserted and DRDY asserted, 

the command returns an error code of 00 No Error 

Detected. 

POSSIBLE ERROR CODES 

03 Write Fault 

04 Drive Not Ready 
08 Drive Still Seeking 

RECALIBRATE (OP CODE 01) 

This command moves the ReadAA/rite heads to track 
0. The SC signal from the drive controls the stepping 
rate of this command. Therefore, this command is 
slower than commands that implement the implied 
seek and make use of the stepping rate designated 
by the SP bits in the Command Block. 

NOTE 

Timeout on each step during a Recalibrate command 
is 1 second with a WD1015-14. Timeout on each step 
during a Recalibrate Is 3.5 seconds with a WD1015-24. 
The 3.5 second timeout supports removable Win- 
chesters. 

POSSIBLE ERROR CODES 

03 Write Fault 

04 Drive Not Ready 

06 Track Zero Not Found 



READ STATUS OF LAST OPERATION (OP CODE 03) 

Upon termination of a command the WD1002S-WX2 
develops a Command Completion Byte, de-asserts 
the BSY bit, if IRQEN had been enabled, asserts IRQ5. 
If IRQEN had not been asserted, it is the responsibility 
of the Host to read port 321 to determine that a 
WD1002S-WX2 is no longer busy. Once the Host 
determines that a command has terminated, it must 
read the Command Completion Byte to learn which 
drive has terminated and whether an error had occur- 
red. To do this, the Host reads port 320. The format 
of the Command Completion Byte is as follows: 



BIT 


7 


6 


5 


4 


3 


2 


1 











D 











E 






D = Number of the drive terminating. = drive 0. 

1 = drive 1 

E = 1 if an error occurred 

If the Command Completion Byte indicates the 
occurence of an error, issue a Read Status command 
for the drive indicating the error. Preformance of a 
Read Status command before any other command 
execution prevents loss of the error status. When a 
Read Status of the last operation is written to port 
320, the WD1002S-WX2 responds with four bytes of 
status as shown in Figure 3. 



BYTE 


BITS 




7 


6 


5 


4 


3 


2 


1 








AV 





ERROR CODE 


1 








D 





HEAD NUMBER 


2 


CYL NUMBER MSB 





SECTOR NUMBER 


3 


CYLINDER NUMBER LSB 



Indicates that the Head, Cylinder, and Sector fields are valid. 



O 

o 
o 
to 
C/) 

X 

lO 



AV Address valid bit. 

Error Codes are shown in Table 9 

All other bits are the same as those defined in the Command Block definitions. 



FIGURE 3. FOUR STATUS BYTES 



Winchester Board Products 



6-101 



a 

o 
o 

CO 

X 

ro 



When an error occurs during a multiple sector data 
transfer (read or write), this command returns the 
address of the failing sector. If the Read Status com- 
mand Is issued after any of the format commands 
or the Verify Desired Sectors command, the address 

TABLE 9. CONTROLLER RETURNED ERROR CODES 



returned by the WD1002S-WX2 points one sector 
beyond the last track formatted or blocked, if there 
was no error. If there was an error, then the address 
returned points to the track in error. 



HEX 
CODE 



DEFINITION 



00 
02 

03 

04 
06 
08 
11 
12 
15 
18 

19 

20 
21 

30 
31 
32 



No error detected. 

No SC signal from the drive. The WD1002S-WX2 has not received a SC from the drive within one 
second (3.5 seconds with WD1015-24) following the last step pulse of a non-buffered seek operation. 

Write Fault signal received from the drive. This error is reported when the WD1002S-WX2 detects WF 
asserted by a drive either at the completion of a Sector Data Transfer or after initially selecting 
a drive and the drive indicates ready. 

Drive Not Ready. The WD1002S-WX2 reports this error when DRDY is not received from the drive 
at the time selection is attempted, or is de-asserted after the drive has been selected. 

Track Not Found. This error is reported during a Recalibrate command if TKOOO is not receiv- 
ed from the drive before stepping the ReadA/Vrite Heads 1024 steps. 

Drive Still Seeking. This status is returned in response to a Test Drive Ready command when a 
drive performing a buffered seek has not yet asserted SC. 

Uncorrectable Data Error. The ECC logic detected an error burst greater than its correction 
capabilities. The data in the Sector Buffer is not sent to the Host. 

Data Address Mark Not Found. The proper Sector ID was read by the drive but failed to detect 
the Data Address Mark. 

Seek Error. The desired Sector ID field could not be found on the selected track, or a CRC error 
occurred on the ID field. 

Correctable Data Error. An error occurred in the data field that was within the tolerance of the 
ECC logic and was corrected. The data in the Sector Buffer is transmitted to the Host. This status 
is set as a warning to the Host that a marginal condition may exist. 

Track Is Flagged Bad. A sector had been encountered that has the Bad Block Mark set in the ID 
Field. The Format Bad Track command records this bit in all sectors of the designated flagging 
them all as bad. No retries are attempted in response to this error. 

Invalid Command. The WD1002S-WX2 has received a command with an invalid class or Op code. 
Interleave Factor. 

Illegal Sector Address. This error is asserted when a command attempts to address a sector beyond 
the capacity of the drive. This could be at the time the command is issued, or in the case of a 
multiple sector transfer, after the last available sector has been used. 

Sector Buffer Error. An error occurred while preforming Sector Buffer Diagnostics (Command Code 
EO and E4). A disk drive is not involved in this test. 

Controller ROM Checksum Error. A ROM checksum error was detected during the Controller 
Diagnostic command (E4). 

ECC Polynomial Error. During the Controller Diagnostic command (E4), the hardware ECC generator 
(WD11C00-17) failed its test. 



FORMAT DRIVE STARTING AT DESIRED TRACK 
(OP CODE 04) 

The WD1002S-WX2 first positions the Read/Write 
heads to track zero. Using the parameters specified 
in the Command Block, the WD1002S-WX2 positions 
the heads to the desired track. Formatting always 
starts with the first sector of the track, regardless of 
the value of SEC. Even so, SEC must be within the 
allowable limits. A sample of what is recorded in 



each sector is shown in Figure 4. The data recorded 
in the Data Field is defaulted to whatever is in the 
Sector Buffer at the time. The logical sector number- 
ing is specified by the interleave value (INT) included 
in the Command Block. If a hard error occurs while 
formatting a track, the WD1002S-WX2 stops the for- 
mat operation and returns an error code. 



6-102 



Winchester Board Products 





















1 


1 — 1 








lELD- 














/ 




IN'OEX 


1 


,, 






1 ' 


,, 




f 






f 

GAPJ 
<1E 


GAPl 
4E 

1 


KBYTES 

•00- 


A 

1 


1 
D 

E 
N 

T 


C L 
Y 
L W 


H 
E 
A 
D 


S 
E 
C 


c 

R 
C 
1 


c 

R 
C 
2 


3 3VTES 


12 BYTES 
00' 


A 

1 


F 
8 


USER DATA 


4ECC 


3 BYTES 
00 


GAP3 
iE 
1 


/ 


1 










1 !■ 

' 11 


i 1 


1 


• 






1 1 




1 








> 1 1 
1 1 1 




1 

1 






DRUN 




1 
1 


/ 


^/// 


WM 


/// 


W/i 


/ 
/, 




/////////// 


WIl 
























1 
1 












2 








3 


1 


7 















































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ID FIELD 



A1 = A1 Hex with 

OA Hex clock 

IDENT = Bits 1,0 = Cylinder High 

FE =0-255 Cylinders 
FF = 256-511 Cylinders 
FC = 512 = 767 Cylinders 
FD - 768-1023 Cylinders 

HEAD = Bits 0,1,2 = Head Number 

Bits 3,4, = 00 
Bits 5,6, = Sector Size (10) 
Bit 7 = Bad Block Mark 



Sec# = 


Logical Sector Number 


DATA FIELD 




A1 = 


A1 Hex with OA Hex clock 


F8 = 


Data Address Mark; Normal 




Clock 


USER = 


Data Field 512 Bytes 



NOTES: 

1. GAP 1 and 3 length equals 22 bytes. 

2. The decision to assert RG is made 2 bytes after 
the start of DRUN. 

3. RG de-asserted: 

• If DRUN does not last until A1 

• When any part of ID does not match the one 
expected. 

• After CRC if correct ID has been read. 

4. Write splice recorded on disk by asserting WG. 

5. RG is suppressed until after write splice. 

6. Not a proper A1 or F8, set DAM error. 

7. Sector size as stated in ID field, plus four for ECC. 



FIGURE 4. FORMAT 



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6-103 



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INTERLEAVING 

When physically sequential sectors on the disk are 
to be read, each sector reaches the read/write head 
before a read or write operation can be set up. The 
disk must then make a complete rotation to pick up 
the next sector. When an attempt is made to read all 
17 sectors on a particular track, 17 rotations or 
approximately one fourth of a second per 8K bytes 
are required. This performance can be significantly 
improved by interleaving, a technique that allows the 
system to read or write more than one sector per rota- 
tion. 



For a system requiring less than two sector times to 
proccess the data it has read and to set up for the 
next read operation, the second logical sector is 
physically placed three sectors away from the first. 
The controller can now read the second sector with 
minimal delay. This three-to-one interleave factor 
allows a potential reading of the entire track in less 
than three rotations. In the example given, the 
throughput is increased by a factor of 5.6. 



r 

OB 00 



INDEX 
PULSE 




FIGURE 5. 17 SECTORS WITH A 3:1 INTERLEAVE 



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The simplest way to determine the optimum interleave 
for any particular system is through experimentation. 
If the system maintains its directories or virtual 
memory-swapping areas in a certain place of the disk, 
it sometimes makes sense to have more than one 
interleave. 

To simplify driver software, the WD1002S-WX2 
automatically writes the logical sector number of 
each sector in its ID field. Figure 5 is an example of 
an interleave table for a 17-sector track with 3:1 
interleave. The WD1002S-WX2 accepts any interleave 
value between zero and one less than the number of 
sectors per track. An interleave of zero is 
automatically converted to one, and a value out of 
range results in an error code 20, Invalid Command 
Error. 



VERIFY SECTORS (OP CODE 05) 

This command reads from 1 to 256 sectors, as 
specified by BLK in the Command Block, beginning 
at the sector specified by HD CYL and SEC. If an error 
occurs during a multiple sector read, the heads 
remain positioned at the track containing the error. 
The Host then issues a Read Status of Last Disk 
Operation command to determine the error code. To 
continue the operation, the Host calculates the dif- 
ference between the number of sectors desired and 
the number of sectors completed and issues another 
Seek command to access the remaining sectors. 

POSSIBLE ERROR CODES 

02 No Seek Complete 

03 Write Fault 

04 Drive Not Ready 

06 Track Zero Not Found 

12 Data Address Mark Not Found 

15 Seek Error 

19 Track Flagged Bad 

21 Illegal Disk Address 

FORMAT TRACK (OP CODE 06) 

This command is identical to the Format Drive com- 
mand, except that only the track specified by the com- 
mand is formatted. This command can be used to 
clear the Bad Track Flag, or reformat individual tracks. 



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FORMAT BAD TRACK (OP CODE 07) 

This command is the same as the Format Tracl< com- 
mand, except that the Bad Tracl< Fiag is set in the 
ID field. 

READ SECTORS (OP CODE 08) 

This command reads from 1 to 256 sectors as spec- 
ified by BLK in the Command Block, beginning at the 
sector defined by CYL SEC and Head. An uncorrec- 
table error during a multiple sector read causes the 
operation to terminate at the error sector. The Host 
then issues a Read Status of Last Disk Operation 
command to determine the type of error. To continue 
the operation, the Host calculates the difference 
between the number of sectors desired and the 
number of sectors completed, then issues another 
Read commend to access the remaining sectors. Er- 
ror code 06 can only be asserted if the R1 bit = and 
ten consecutive attempts have failed to read the ID 
Field. This causes the WD1002S-WX2 to recalibrate 
the heads and seek back to the desired track. If track 
zero is not detected within 1024 steps. Error Code 
06 is set. If R1 = 1, the WD1002S-WX2 aborts the 
command after a maximum of two tries to read the ID 
field. Therefore no attempt is made to position the 
heads to track zero. 

POSSIBLE ERROR CODES 

02 No Seek Complete 

03 Write Fault 

04 Drive Not Ready 

06 Track Zero Not Found 

11 Uncorrectable ECC Error 

12 Data Address Mark Not Found 
15 Seek Error 

18 Correctable ECC Error 

19 Track Flagged Bad 

21 Illegal Sector Address 



WRITE SECTORS (OP CODE OA) 

This command writes from 1 to 256 sectors as 
specified by BLK in the Command Block. The multi- 
ple sector transfer scheme works the same as the 
Read command. Error code 06 can only be asserted 
if the R1 bit is and ten consecutive attempts have 
failed to read the ID Field. This causes the WD1002S- 
WX2 to recalibrate the heads and seek back to the 
desired track. If track zero is not detected within 1024 
steps. Error Code 06 is set. If R1 is 1, the WD1002S- 
WX2 aborts the command on the first failure to read 
an ID Field. Therefore, no attempt to position the 
heads to track zero is made. 

POSSIBLE ERROR CODES 

02 No Seek Complete 

03 Write Fault 

04 Drive Not Ready 

06 Track Zero Not Found 

12 Data Address Mark Not Found 

15 Seek Error 

19 Track Flagged Bad 

21 Illegal Disk Address 



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SEEK (OP CODE OB) 

This command selects the head and initiates a seek 
to the track specified by HD and CYL in the Command 
Block. The SC signal line is sampled to allow 
buffered seeks. The cylinder must be in range. The 
drive must be formatted. Drives employing buffered 
steps can be issued step pulses at a high speed, free- 
ing the WD1002S-WX2 for other operations. The 
WD1002S-WX2 does not w/ait for the drive to complete 
the seek to return a Command Completion Status. 
If the return status shows no error, the seek was 
issued correctly. If there is an error, the seek was not 
issued. After transferring the status, another com- 
mand can be issued to either drive. If the WD1002S- 
WX2 receives a command other than Test Drive Ready 
for a drive that is still seeking, it asserts BSY and 
waits for SC to be asserted before executing the 
command. If the command is a Test Drive Ready, it 
executes and returns an 08 Drive Still Seeking Error. 
The time-out for non-buffered seeks is 1 second for 
a WD1002S-WX2 with a WD1015-14. A WD1002S-WX2 
with a WD1015-24 times out for 3.5 seconds for non- 
buff ered_seeks. For buffered seeks, the WD1015 
checks SC before a Read or Write (next command). 

The rate at which the Step Pulses are issued to the 
drive is controlled by the SP bits in the Command 
Block. The drive buffers these pulses and steps at 
its own rate. This allows the WD1002S-WX2 to con- 
tinue about its own business, possibly starting the 
other drive seeking to a new track, without having to 
wait for the SC from the first drive. Refer to Table 
8 for the available stepping rates. 

POSSIBLE ERROR CODES 

03 Write Fault 

04 Drive Not Ready 
15 Seek Error 



INITIALIZE DRIVE PARAMETERS (OP CODE OC) 

The WD1002S-WX2 is capable of controlling two 
drives with different formatted capacity. The BIOS 
contains four Winchester parameter tables. The con- 
figuration jumpers address the proper Winchester 
parameter table during the BIOS install cycle at power 
up. Refer to Table 1 1 for details on these jumper set- 
tings. When the Host reads port 322 and discovers 
a change in drives, it issues this command, followed 
by the 8-byte block of drive parameters listed below: 

Maximum Number of Cylinders (2 bytes, 1024 

max.) 
Maximum Number of Heads (1 byte, 8 or 16 heads) 
Starting Reduced Write Current Cylinder (2 bytes, 

1024 max.) 
Starting Write Precompensation Cylinder (2 bytes, 

1024 max.) 
Maximum ECC Data Burst Length (I byte, max.) 

A typical set of parameters for a 10MB drive is as 
follows: 

306 cylinders 

4 heads 

RWC at cylinder 153 

Write Precomp at cylinder 153 

11-bit burst error length (Western Digital Corp. 
recommends using a maximum ECC burst 
length of five or less to ensure optimum 
integrity of data recovered). 

For the exact parameters, it is necessary to refer to 
the specifications for the BIOS in use on the specified 
board. 



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READ ECC BURST ERROR LENGTH 
(OP CODE OD) 

This command is oniy vaiid foilowing a correctable 
ECC error. It transfers one byte indicating the length 
of the error. The error length is determined by coun- 
ting the first through last bit in the error. 

READ SECTOR BUFFER (OP CODE OE) 

This command transfers the 512 bytes of data cur- 
rently residing in the Sector Buffer to the Host. 

WRITE SECTOR BUFFER (OP CODE OF) 

This command writes 512 bytes of data from the Host 
into the WD1002S-WX2 Sector Buffer. 

EXECUTE SECTOR BUFFER DIAGNOSTIC 
(OP CODE EO) 

This command executes a 9-pass test that uses a 
0-byte pattern (0, 1, 2, 4, 8, 10, 20, 40, and 80 hex) that 
is written to the Sector Buffer, then read back. After 
each successful completion, the whole pattern is 
shifted one byte postition and repeated. 

NOTE 

The WD Fonnat Drive Utility in the WD BIOS executes 
this command before physical formatting of the drive. 
Thus, the data fields are formatted with this 0, 1, 2, 
4, 8, 10, 20, 40, and 80 hex pattern. 



POSSIBLE ERROR CODES 

30 Data error 

EXECUTE DRIVE DIAGNOSTIC 
(OP CODE E3) 

This command tests both the drive and the drive-to- 
WD1002S-WX2 interface. The WD1002S-WX2 sends 
Recalibrate and Seek commands to the selected drive 
and reads sector zero of each track verifying both ID 
and data fields. The WD1002S-WX2 does not perform 
any write operations. 

5.19.1 POSSIBLE ERROR CODES 

02 No Seek Complete 

03 Write Fault 

04 Drive Not Ready 

06 Track Zero Not Found 

12 Data Address Mark Not Found 

15 Seek Error 

EXECUTE CONTROLLER DIAGNOSTICS 
(OP CODE E4) 

Regardless of the version of the WD1015 on the 
WD1002S-WX2, the WD1002S-WX2 executes this com- 
mand when the Host issues a command code of E4 
hex to the CCB. The WD1015-14 automatically 
executes this command after system Reset (RST on 
connector PI B2 asserted), write to port 321 Hex, or 
power-up. The WD1015-24 oniy automatically 
executes this command when an on-board WD BIOS 
performs an install sequence after power-up. 



6-108 



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Once started, this command continues to run until 
an en-or occurs, or tlie Host selects the WD1002S-WX2 
by writing to port 322. If an error occurs when this 
command has been started at power up, an en^or code 
Is output at pins 27, 28, and 29 of the WD1015. These 
are the Head Select 0, 1, and 2 signals and can be 
monitored at the Drive Control Connector J1 pins 14, 
18, and 4. The error codes generated under this con- 
dition are not the same as those reported by a Read 
Status command. 

1 - WD1010A-05 Error 
2-WD11C00-17 ECC Error 

3 - Sector Buffer Error 

4 - WD1015 RAM Error 

5 - WD1015 ROM Error 

WD1010A-05TEST 

A pattern is written to and read from the 
WDIOIOA-05's Sector Count and Sector Number 
Registers. 

WD11C00-17 ECC TEST 

The WD11C00-17 Is enabled during the read portion 
of the Sector Buffer Test. After the contents of the 
Sector Buffer have been read, the ERR (pin 1) of the 
WD11C00-17 is monitored, it should be asserted 
Indicating non-zero Check Bytes. The internal check 
pattern is then fed back into the chip and pin 1 
monitored again. This time it should not be asserted. 
Indicating a Check Byte pattern of zero. 



SECTOR BUFFER TEST 

The hex pattern 00, 01, 02, 04, 08, 10, 20, 40, 80 is writ- 
ten throughout the entire Sector Buffer and then read 
to make sure it is correct. The entire contents of the 
Sector Buffer is then shifted one byte position and 
read again. This procedure is repeated nine times veri- 
fying that every bit in the Sector Buffer can be set 
and reset. 

The WD11C0O-17 is enabled during the read functions 
to verify the operability of that device. 

WD1015 RAM TEST 

This tests the 100 bytes of internal RAM in the same 
manner as the Sector Buffer test. 

WD1015 ROM TEST 

This test verifies the ability to address and read all 
2K bytes of internal ROM, using an add and rotate 
algorithm to generate a single byte result. This result 
is then compared with the Sumcheck located in the 
last page of memory. 

POSSIBLE ERROR CODES 

30 Sector Buffer Error 

31 ROM Sumcheck Error 
3 ECC Error 



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READ LONG (OP CODE E5) 

The Host first performs a normal Write command, 
writing known data, that produces a predictable ECC 
character, then performs a Read Long command. This 
command reads the data from the disk without 
generating a ECC bytes of its own. Instead, it reads 
the four ECC bytes from the disk, as though reading 
data, resulting in 512 plus 4 for a total of 516 bytes 
of data. The Host, knowing what the data and ECC 
bytes are supposed to be, can now determine whether 
any errors that have occurred are a result of a data 
or ECC failure. 

POSSIBLE ERROR CODES 

02 No Seek Complete 

03 Write Fault 

04 Drive Not Ready 

06 Track Zero Not Found 

12 Data Address Mark Not Found 

15 Seek Error 

19 Track Flagged Bad 

21 Illegal Disk Address 

WRITE LONG (OP CODE E6) 

After performing the Write normal/Read Long routine 
to determine that the WD1002S-WX2 is able to write 
data and generate correct ECC bytes, the Host can 
execute a Write Long and Read normal routine. This 
verifies the ability of the WD1002S-WX2 to read the 
data correctly and generate 4-zero ECC bytes or if an 
error was forced, correct it. The Write Long command 
does not generate ECC bytes. Instead the Host sup- 
plies them along with a known data pattern. Then, 
performing a normal Read command, the Host can 
determine whether non-zero ECC bytes are caused 
by a Read failure or ECC generation failure. (This 
procedure could be performed prior to the Write 
normal/Read Long). 

POSSIBLE ERROR CODES 

02 No Seek Complete 

03 Write Fault 

04 Drive Not Ready 

06 Track Zero Not Found 

12 Data Address Mark Not Found 

15 Seek Error 

19 Track Flagged Bad 

21 Illegal Disk Address 



INSTALLATION 

HARDWARE AND SOFTWARE INSTALLATION 

This section briefly describes installation of the 
WD1002S-WX2 in an IBM PC or IBM-compatible 
computer. 

1. Ensure system power is off. 

2. Insert WD1002S-WX2 in computer chassis and 
connect drive cables. 

(J1 = control cable, J2 = drive cable, J3 = drive 
1 cable) 

3. Power up the system. 

4. Insert IBM PCDOS 2.0 or IBM PCDOS 2.1 diskette. 

CAUTION 

Performing steps 5 through 9 destroys any data 
presently on the disk. 

5. Load DEBUG utility by typing "debug" and ENTER 
after the DOS prompt. 

6. Initiate the WX2FMT (format) program by typing 
the following command line: g = c800:5 

7. Press "y" to begin formatting drive (logical 
drive C.) 

8. To format drive 1 or second drive in a daisy chain, 
reload DEBUG utility. Type "RAX" and ENTER. 
Prompt returns "AX 0000". Type "0103", ENTER 
which defines relative drive number and interleave 
factor (01 = relative drive number; 03 = interleave 
factor). Type "G = C800:5", ENTER, and type "y" 
to begin formatting drive 1 (logical drive D). 

9. Run standard DOS utilities, FDISK and FORMAT. 

JUMPER INSTALLATION AND LOCATIONS 

The WD1002S-WX2 is configured for the standard IBM 
PC XT with jumper plugs installed at W3, W4, and W6. 
No jumpers are required at W5 and W7. To change 
the configuration, a jumper plug can be installed in 
the appropriate block. Installation of jumpers on W5 
and W7 requires carefully cutting an etch and plac- 
ing a jumper plug onto the Jumpered position. To 
restore the standard setting, move the jumper plug 
to the Standard position. Table 10 describes these 
jumpers and options. Table 11 describes the drive 
configuration jumpers and an INTERRUPT REQUEST 
(IRQ) jumper in SW1. Figure 6 illustrates the locations 
of W1 through W7 and SW1. 



6-110 



Winchester Board Products 



TABLE 10 JUMPER SELECTABLE OPTIONS (W1 THROUGH W5) 



JUMPER 


FUNCTION 


PIN 


DESCRIPTION 


W1,W2 






For Western Digital Manufacturing use only. 


W3 


Standard: 


1-2 


Closed by etch or jumper. Enables BIOS ROM 






1-2 


Open. Disables BIOS ROM. 


W4 


Standard: 


2-3 


Selects primary port 320 Hex. 




Jumpered: 


1-2 


Selects secondary port 324 Hex. Requires 
custom BIOS. 

NOTE 

The WD1002S-WX2 provides two sets of I/O 
ports. The primary port addresses are 320 
through 323 Hex. The secondary port 
addresses are 324 through 327 Hex. However, 
secondary ports on the WD1002S-WX2 are 
NOT supported by many versions of DOS. 


W5 


Standard: 


1-2 


Selects 2732 or 2764 BIOS ROM size. 




Jumpered: 


2-3 


Selects 2716 BIOS ROM size. W5 pin 1-2 etch 
must be cut. 


W6 


Standard: 


2-3 


8 head configuration, RWC used. 




Jumpered: 


1-2 


16 head configuration, RWC not used, requires 
custom BIOS ROM and WD1015-24. 


W7 


Standard: 


1-2 


Selects IRQ5. 




Jumpered: 


2-3 


Selects IRQ2. SW1 position 5 must also be 
jumpered (closed) and W7 pin 1-2 etch must 
be cut. 



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TABLE 11 SW1 JUMPER BLOCK DESCRIPTION 

WD BIOS 62-000042-01 (ROM) or 62-000042-11 (EPROM) 



BIOS 
TABLE 


FORMATTED 
CAPACITY 


PCS TION 


DRIVE 
TYPE 


HEADS 


NUMBER OF 
CYLINDERS 


PRE-COMP 
RWC 


1 2 
DRIVE 1 


34 
DRIVE 


3 


10MB 


1 1 


1 1 


ST412 
Seagate 


4 


306 



None 


2 


15MB 


01 


01 


ST419 
Seagate 


6 


306 


256 
RWC = 128 


1 


26MB 


1 


1 


5820 
Evotek 


8 


375 



None 





5MB 


00 


00 


ST506 
Seagate 


2 


306 



None 






WD BIOS 62-000042-12 (EPROM) 






3 


10MB 


1 1 


1 1 


ST412 
Seagate 


4 


306 



None 


2 


20MB 


01 


1 


ST225 
Seagate 


4 


612 


128 
None 


1 


10MB 


1 


1 


3012 
MiniScribe 


2 


612 


128 
RWC =128 





20MB 


00 


00 


HH725 
Microsclence 


4 


612 


None 
None 



Factory sets jumper for BIOS Table 3. Position 5 of SW1 select IRQ5 (factory setting) or IRQ2. 1 = IRQ5. 
= IRQ2. Positions 6, 7, and 8 of SW1 are reserved. 

LEGEND: 1 = no jumper Installed, ties input to +5vdc. = jumper installed, ties input to ground. 



6-112 



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FIGURE 6. JUMPER LOCATIONS 



7.3 BIOS ROM INSTALLATION 



The WD1002S-WX2 firmware driver routines, supplied 
by Western Digital Corporation, reside in a 4KB x 8 
bit EPROM. Tfiis BIOS ROM is available in ttiree sizes 
as follows: 

2716 2KB X 8 bit 

2732 4KB x 8 bit (standard from the factory) 

2764 8KB x 8 bit 

The WD1002S-WX2 provides a 28 pin DIP socket for 
the BIOS ROM. This socket accomodates a 2732 or 



2764 JEDEC EPROM. Figure 7 illustrates the standard 
connections for the 2732 or 2764. These connections 
can be modified to support a 2716. Perform the follow- 
ing steps to modify the standard connections: 

1. Cut the etch between pads 1 and 2 on W5 

2. Jumper pad 3 to pad 2 

3. Wire pin 20 and 26 as shown. 

4. Plug BIOS in the socket. Pin 1 of the 2716 BIOS 
should be in position 3 of the socket. 



E2(A11) 




FIGURE 7. BIOS ROM SOCKET CONNECTIONS 



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SPECIFICATIONS 

This section contains the overail specifications for 
the WD1002S-WX2 Winchester Disk Controller. 

ELECTRICAL 



HOST INTERFACE 

Type 

Host Interface Connector 



DRIVE INTERFACE 

Encoding Method 
Cylinders per Drive 
Sectors per Track 
Bytes per Sector 
Heads 



Drive Selects 
Stepping Rates 



Data Transfer Rate 
Write Precomp Time 
Sectoring 
CRC Polynomial 
ECC Polynomial 

Reciprocal ECC Polynomial 

Miscorrection Prob. 
Non-detection Prob. 
Correction Span 
Max Cable Length: 

Control (Total Daisy 3 Meters 

(10 ft.) Chain) 

Data (Radial-each) 

WD10C20 

Acquisition Time 
Capture Range 
Bit Jitter Tolerance 
Asymmetry Tolerance 

POWER 

Voltage 

Current 

Ripple 

Voltage 

Current 



IBM PC 

P1 connects directly to Host motherboard with a 62-pin card edge 

connector 



MFM 

Up to 1024 

17 

512 

8 w/ith WD1015-14 

16 with WD1015-24 

2 

70 Msec, 200 ^sec, 3 msec (WD1015-14) 

18 Hsec, 30 Msec, 45 fisec, 60 jusec, 

75 Msec, 210 ^sec, 3 msec (WD1015-24) 

5 M bits/sec (ST506) 

12 nsec 



Soft 
xi6 

v15 



,13 



x^ + 1 



^26 



19 



+ X'^ + 



X^ + X^ -f 1 



^26 



+ 



x'' + x'* -t- 1 



22 



5-bit correction = <1.6 E- 

<2.3 E-10 

Up to ll-bit burst 

3 Meters (10 ft.) 

3 Meters (10 ft.) 



< or = 12. 8 fis 

± 2.2% to Ins after 12.8 pjs acquisition 
± -34ns (min. of 40 db after acquisition) 

± -34ns (write precompensation turned off; as measured over con- 
stant RCLK pattern) 



5V ±5% 

0.8 amps max. 

0.1 volts max., 25 mV typical 

-f12 ±10% 

10 mA. max. 



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PHYSICAL 

Form factor 

Length 

Width 

Height (max including board, 

components, & leads) 

ENVIRONMENTAL 

Ambient Temperature 

Relative Humidity 

Altitude 

Air Flow 

MTBF 

MTTR 

INTERFACE TIMING 



IBM PC 

20.6 centimeters (8.1 inches) 
9.78 centimeters (3.85 inches) 
1.27 centimeters (0.50 inches) 



0°C (32°F) to 55°C (131°F) 

10% to 95% non-condensing 

to 3000 meters (10,000 ft) 

100 lin ft/min. at 0.5" from component surfaces. 

10,000 POH 

30 Minutes 



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Timing diagrams are shown in Figures 8 through 11 
and their values are listed in Tables 12 through 15 
respectively. Since the Controller I/O ports can be 
accessed by either the Host system DMA Controller 
or the Host processor, timing is given for both cases. 



The processor executes I/O and memory reads from 
the ports and the on-board BIOS ROM, and writes to 
the ports. The DMA is used for data transfers between 
the data I/O port and the Host RAM. 



A19-A0, 
AEN 

fOR , HEW • 



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ADDRESS WILL BE VALID 



07 - DO 



h-*Asi-*^»^ 



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< 



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DATA MUST 
BE VALID 



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FIGURE 8. HOST I/O OR BIOS READ TIMING 



TABLE 12. HOST I/O OR BIOS READ TIMING 









UNITS IN NSEC. 


SYMBOL 


CHARACTERISTIC 


MIN 


MAX 


Usi 


Address Setup Time 


50 




Ucc 


Address Access Time 




250 


toE 


Output Enable Time 




175 


^DHI 


Data Hold Time 








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X V 








DATA MUST BE VALID — ^ 







FIGURE 9. DMA I/O READ TIMING 



TABLE 13. DMA I/O READ TIMING 









UNITS IN NSEC. 


SYMBOL 


CHARACTERISTIC 


MIN. 


MAX. 


toDRQ 


DRQ3 De-assert Delay 


20 


45 


tpsu 


Read Setup Time 


7 




toOE 


Data Output Enable 




175 


^DHS 


Data Hold Time 








6-776 



Winchester Board Products 



M9-A0, / " 



lOM 



D7 - DO 



« 



ADDRESS WILL BE VALID 



X 



t 1 J 


_ 








_ 








^ASU2 1^ 






"WP 














J 










h — 


f 










^DSU 






*l 


'■DHZ 



I 



DATA WILL BE VALID 



> 



o 

o 
o 

in 

X 

ro 



FIGURE 10. HOST I/O WRITE TIMING 



TABLE 14. HOST I/O WRITE TIMING 







UNITS IN NSEC. 


SYMBOL 


CHARACTERISTIC 


MIN. 


Usua 


Address Setup Time 


50 


twp 


Write Pulse Time (I/O) 


100 


bsu 


Data Setup Time 


50 


^DH2 


Data Hold Time 






Winchester Board Products 



6-117 



a 

o 
o 
ro 
CO 

X 

ro 



DACK3 
























^ 


RQ2 














'^DD 






DRQ3 


*^ 


, 








h^^w 




* • 








su • 




-WP 








Tow 


















■*- 


_l 






^DS 




r^'^DH4~n 





D7 - DO 



< 



I. 



DATA WILL BE VALID 



> 



FIGURE 11. DMA I/O WRITE TIMING 



TABLE 15. DMA I/O WRITE TIMING 



UNITS IN NSEC. 



SYMBOL 


CHARACTERISTIC 


MIN. 


MAX. 


toDRQ 


DRQ3 De-assert Delay 


20 


45 


twsu 


Write Setup Time 


7 




twp 


Write Pulse Width 


100 




tDS 


Data Setup Time 


50 




tDH4 


Data Hold Time 








6-118 



Winchester Board Products 



WESTERN DIGITAL 

CORPORATION 

WD1002-WAH WINCHESTER DISK CONTROLLER 



FEATURES 

• PC AT COMPATIBLE WINCHESTER 
CONTROLLER 

• CONTROLS UP TO TWO WINCHESTER 
DRIVES (16 R/W HEADS EACH) 

• HARDWARE DESIGN ALLOWS TWO 
WD1002-WAH CONTROLLERS IN ONE 
SYSTEM 

• 8-BIT, BI-DIRECTIONAL BUS HOST 
INTERFACE (FOR CONTROL AND 
STATUS TRANSFERS) 

• 16-BIT, HIGH-SPEED PIO DATA 
TRANSFERS 



32-BIT ECC FOR WINCHESTER ERROR 
DETECTION AND CORRECTION 

MULTIPLE SECTOR READ/WRITE 
COMMANDS (MAY CROSS HEAD AND 
CYLINDER BOUNDARIES) 

IMPLIED AND BUFFERED SEEK 
COMMANDS 

READ/WRITE DIAGNOSTIC AND VERIFY 
COMMANDS 

PROGRAMMABLE FORMAT AND ERROR 
RECOVERY ALGORITHMS 

WD10C20 SINGLE CHIP DATA SEPARATOR 



O 

— k 
o 
o 



DESCRIPTION 

The WD1002-WAH is an IBM PC AT bus compatible 
Winchester controller board designed to interface up 
to two drives. The drive interface is based upon the 
Seagate Technology ST506. The drives need not be 
of the same capacity or configuration. All necessary 
receivers and drivers are included on the board to 
allow direct connection to the drive(s). 

ARCHITECTURE 

The WD1002-WAH is based on the WD1014-01 Error 
Detection/Support Logic device, WD1015-03 Buffer 
Manager Control Processor, WD1010A-05 Winchester 
Disk Controller, and WD10C20 Data Separator. The 
WD1002-WAH also uses two 2K x 8 static RAM 
memory devices as a Sector Buffer. 

The WD1014-01 provides error correction for the 
WD1002-WAH. The WD1014-01 generates four ECC 
bytes and appends these bytes to the sector data 
field. The maximum error correction span is 5-bits. 
The WD1014-01 sets the error correction span. The 
WD1014-01 also selects the proper drive and head. 

The WD1015-03 is an 8-bit microprocessor that con- 
trols and coordinates the activity of the disk drives, 
WD1010A-05, and WD1014-01. The WD1015-03 
receives and sends command or status information 
over the internal WD1002-WAH multiplexed 



address/data bus, HDO through HD7. Controlling firm- 
ware resides in the WD1015-03's 2K internal ROM. 

The WD1010A-05 controls ail data transfers between 
the Sector Buffer and the drives. The WD1010A-05 per- 
forms multiple sector ReadA/Vrite, Implied and Buf- 
fered Seek commands. The WD1010A-05 also 
executes programmable format and error recovery 
algorithms. All commands are executed through the 
seven Task Files of the WD1010A-05 after limited 
intervention by the WD1015-03 and WD1014-01. 

The WD10C20 performs phase-locked loop data syn- 
chronization on read data from the Winchester drives. 
This device also conditions write data to be recorded 
on the disk. The WD10C20 includes both frequency 
and phase detection. Zero phase error start-up cir- 
cuitry eliminates problems due to asymmetry. The 
WD10C20 requires no adjustments and contains all 
data separation circuitry in a single device. 

The Sector Buffer is two 2KB x 8 RAMs. Since the 
WD1010A-05, WD1014-01, and WD1015-03 are 8-bit 
devices, two RAMs are used because the Host pro- 
vides data in 16-bit words. An onboard PAL selects 
the proper RAM. The Sector Buffer RAMs never con- 
tain more than 512 bytes. 

Figure 1 is a block diagram of the WD1002-WAH. 



Winchester Board Products 



6-119 



o 

—1 

o 
o 

I 








M«£ UP (BUST) 






* 


HWO DISK S£L 


^ 




lOM REG COKIHOl ^ 






I/O BUTFER CONIRO 


^ 


INTESFACf 




fHASlE STATUS 


* 


1ASK rilE ADOR I! 






FAST 10 16 














1 



®i d 



X © 



FIGURE 1. WD1002-WAH BLOCK DIAGRAM 



INTERFACE CONNECTORS 

The WD1002-WAH has five interface connectors: 

P1-62-pin card edge connector 

Component side -Pins A1 through A31 
Conductor side -Pins B1 through B31 

P2-36-pin card edge connector 

Component side -Pins C1 through CIS 
Conductor side -Pins D1 through D18 

J1-controi cable connector 

J2- drive data cable connector 

J3- drive 1 data cable connector 

The pin description of the connectors are given in 
Tables 1 through 4. 



HOST INTERFACE CONNECTORS 

The WD1002-WAH Controller interfaces with the 
16-bit, bi-directional data bus by means of the two 
card edge connectors P1 and P2. The pin descriptions 
for P1 are given in Table 1 and for P2, in Table 2. 



6-120 



Winchester Board Products 



TABLE 1. HOST INTERFACE CONNECTOR (P1) PIN DESCRIPTION 



PIN 










NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


A1,A10, 


NC 








A12 










thru 










A21 










A2 


SD7 


DATA BIT 7 


I/O 


Bi-directional, 8-bit data bus for data and status 


thru 


thru 


thru 




communication between the controller and the 


A9 


SDO 


DATA BIT 




Host. 


A11 


AEN 


ADDRESS 
ENABLE 


1 


When AEN Is asserted, the DMA controller 
assumes control of the Host address bus, control 
bus, and data bus. I/O port addresses are no longer 
generated for I/O port access. 


A22 


SA9 


ADDRESS 


1 


A 10-bit address bus for I/O addressing by the Host. 


thru 


thru 


BITS A9 






A31 


SAO 


thru AO 






B1,B10 


GND 


Ground 






B31 










B2 


RST 


RESET 


1 


When asserted, RST forces the WD1002-WAH board 
into the initial power-up state. 


B3,B29 


+ 5VDC 


+ 5VDC 




+ 5VDC 


B9 


+ 12VDC 


+ 12VDC 




+ 12VDC 


B4 


NC 








thru 










B8,B11, 










B12 










B13 


low 


I/O WRITE 


1 


Assertion causes the WD1002-WAH to read a data. 


814 


lOR 




1 


status or control byte from the Host data bus. 
Assertion causes the WD1002-WAH to drive data 


I/O READ 










unto the Host data bus. 


B15 


NC 








thru 










B27,B30 










B28 


ALE 


ADDRESS 

LATCH 

ENABLE 


1 


Assertion enables the WD1002-WAH to latch a valid 
board address from the Host address bus. 



o 

o 
o 

lO 

i 



Winchester Board Products 



6-121 



TABLE 2. HOST INTERFACE CONNECTOR (P2) PIN DESCRIPTION 



D 

o 
o 

I 



PIN 
NUMBER 


MNEMONIC 


SIGNAL NAME 


I/O 


FUNCTION 


C1 
thru 
C10 


NC 








C11 
thru 
C18 


D8 

thru 

DO 


DATA BIT 8 

thru 

DATA BIT 15 


I/O 


Bi-directional, 8-bit data bus for data tranfers only 
between the controller and the Host. 


D1 
D2 


NC 
I/0CS16 




1 


Assertion signals the system board that the cur- 
rent data transfer is a 1 wait-state, 16-bit I/O cycle, 
derived from an address decode. 


I/O 16 BIT 

CHIP 

SELECT 


D3 
thru 
D6 


NC 








D7 


IRQ14 


INTERRUPT 
REQUEST 14 





Assertion indicates that the WD10Q2-WAH request 
execution of the Host interrupt service routine. 


D8 
thru 
D18 


NC 









DRIVE CONTROL CONNECTOR J1 

The drive control connector is a 34-pin printed circuit 
card edge connector daisy-chained to each drive in 
the system. To terminate the control signals on the 
WD1002-WAH properly, the last drive on the daisy 



chain must have a 220/330 ohm resistor 
pack installed. Pin descriptions and control signals 
for the drive control connector J1 are given in Table 3. 



TABLE 3. DRIVE CONTROL CONNECTOR (J1) PIN DESCRIPTION 



SIGNAL 


I/O 


FUNCTION 


GND. 


PIN 


MNEMONIC 


NAME 


1 

3 
5 

7 


2 

4 
6 

8 


HS3/RWC 

HS2 
WG 

SC 


HEAD 
SELECT 3 
REDUCE 
WRITE 
CURRENT 







1 


The WD1002-WAH uses HS3 to select one of 16 
R/W heads. RWC is not used with 16 head drives. 
RWC is used by drives with 8 RA/V heads. RWC 
reduces the write current on the inner cylinders. 
This lessens the bit shift caused by greater den- 
sity on these cylinders. 

HS2 is one of the head select signals decoded 
by the drive to select one of eight (or 16) R/W heads. 

WG is asserted when valid data is to be written 
on disk. The WD1002-WAH de-asserts WG when 
WF is detected. Special circuitry is included to 
ensure the system output is free of glitches dur- 
ing power-on. 

SC informs the WD1002-WAH that the head of a 
selected drive has reached the desired cylinder and 
has stabilized. 


HEAD 
SELECT 2 


WRITE 
GATE 


SEEK 
COMPLETE 



6-722 



Winchester Board Products 



TABLE 3. DRIVE CONTROL CONNECTOR (J1) PIN DESCRIPTION (cont'd) 



SIGNAL 


I/O 


FUNCTION 


GND. 


PIN 


MNEMONIC 


NAME 


9 
11 

13 
15 

17 
19 

21 
23 

25 

27 

29, 
31, 
33 

33 


10 
12 

14 

16 
18 

20 

22 

24 

26 
28 

30, 
32 

34 


TKOOO 
WF 

HSO 

GND 

NC 

HS1 


TRACK 000 






1 

1 








TKOOO Is asserted when the RAA/ heads are posi- 
tioned over the outermost cylinder. 

WF is asserted by the selected drive when a write 
error occurs. While this signal is being asserted, 
the command In progress aborts and no other disl< 
command can be executed. 

HSO is one of the head select signals decoded by 
the drive to select one of eight (or 16) R/W heads. 

HS1 is one of the head select signals decoded by 
the drive to select one of eight (or 16) R/W heads. 


WRITE 
FAULT 


HEAD 
SELECT 


HEAD 
SELECT 1 


INDEX 


INDEX 
PULSE 


INDEX indicates the start of a track. Used as a 
synchronization point during formatting and as a 
time-out mechanism for retries. Pulses once each 
disl< revolution. 


DRDY 


DRIVE READY 


DRDY Informs the controller that the drive motor 
is up to speed. 


STEP 

DSO 
DS1 
GND 

NC 


STEP PULSE 


STEP, with DIRIN, positions the heads to the 


desired cylinder. STEP pulses once for each step. 
DIRIN determines the step direction. 

DSO is used to select drive 0. 
DS1 is used to select drive 1. 


DRIVE 
SELECT 


DRIVE 
SELECT 1 


DIRIN 


DIRECTION 
IN 


DIRIN determines the direction in which the RA/V 
heads move when the step line is pulsed. De- 
asserted = out; asserted = in. 



o 

o 
o 

1 



Winchester Board Products 



6-123 



o 

o 
o 

I 



DATA CONNECTORS 

The data lines between the WD1002-WAH and the two 
disk drives are connected to J2 and J3. As the data 
lines are not identical, J2 must be connected to the 
cable from drive 0, and J3 to the cable from drive 1. 
Each drive is radially connected with a maximum 



cable length of 3 meters (10 feet). Each data connec- 
tor is a 20-pin vertical header on 0.25mm (0.01 inch) 
center. Data connector pin descriptions and signals 
are listed in Table 4. 



TABLE 4. DRIVE DATA CONNECTORS (J2,J3) PIN DESCRIPTION 



SIGNAL 


SIGNAL NAME 


GND 


PIN 


I/O 




1 




NC 


2 






GND 




3 




NC 


4 






GND 




5 




NC 


6 






GND 


7 




NC 




8 






GND 




g 




NC 




10 




NC 


11 






GND 


12 






GND 




13 





+ MFM Write Data 




14 





-IVIFM Write Data 


15 






GND 


16 






GND 




17 




+ MFM Read Data 




18 




-MFIV1 Read Data 


19 






GND 


20 






GND 



6-124 



Winchester Board Products 



FORMAT 

The format used for Winchester disk track formatting 
is shown in Figure 2. The ID and data fields on any 
disk are Initialized by the Format command. 





























1 


n 










lELO 












' 




•-, 


' 1 


' 








~1 




. 






\ GAP4 


GAPl 
4E 

1 


14 BYTES 
•00' 


A 
1 


1 
D 
E 
N 

T 


C L 
Y 
L H 


H 

E 
A 



S 
E 
C 
1 


C 
R 
C 

1 


C 
R 
C 
? 


3 BYTES 
■00' 


1? BYTES 
•CO' 


A 
1 


F 
8 


USER DATA 


4ECC 


3 BYTES 
'00' 


GAP3 
4E 

1 


1 


/ 

ORUN 
READ GATE 










1 1 
1 

WRITE GATE 

1 1 
1 1 
1 1 


1 
1 


1 
1 






' 1 










I 
1 
1 
1 










1 




% 


V/M 


^ 


^ 


^ 




w///m 


^1 




1 

1 


















1 

1 






2 










3 5 




' 


L 


1 



































o 

.JL 

o 
o 

% 



NOTES 

1. GAP 1 and 3 length equals 22 bytes. 

2. Decision to assert RG is made two bytes after the 
start of DRUN. 

3. RG is de-asserted: 

• If DRUN does not last until A1. 

• When any part of the ID does not match 
the one that is expected. 

• After ORG, if correct ID has been read. 

4. Write splice recorded on disk by asserting WG. 

5. RG is suppressed until after write splice. 

6. Not a proper A1 or F8, set DAM error. 

7. Sector size as stated in ID field, plus four for ECC. 



ID FIELD 

A1 = A1 hex with OA hex clock 

IDENT = Bits 1,0 = Cylinder High 

FE = 0-255 Cylinders 
FF = 256-511 Cylinders 
FC = 512-767 Cylinders 
FD = 768-1023 Cylinders 

HEAD = Bits 0, 1, 2 = Head Number 
Bits 3,4 = 
Bits 5, 6 = Sector Size 
Bit 7 = Bad Block Mark 

Sec # = Logical Sector Number 

DATA FIELD 

A1 = A1 hex with 01 hex clock 

F8 = Data Address Mark; Normal Clock 

USER = Data Field 512 Bytes 



FIGURE 2. WINCHESTER DISK FORMAT 



Winchester Board Products 



6-125 



o 

o 
o 
to 



REGISTER ADDRESS MAP 

The WD1002-WAH contains seven ReadAA/rite task file 
registers in the WD1010A-05 and three hardware 
registers external to the WD1010A-05. These registers 
are mapped into either a primary of secondary I/O 
address. All data, control, and status information pass 
between the task files and the Host. 

All data transfers are word transfers except ECC 
bytes in Read Longs and Write Longs. These ECC 
bytes are transferred in byte- mode. Control and sta- 
tus bytes are also transferred between the Host in 
byte mod e. T he 7 task file registers are multiplexed 
with lOR and lOW to give 14 possible parts. Five of 
the eight task file registers are bi-directional. Two of 
the task file registers have different definitions for 
read and write operation. Jumpers select the pri- 
mary and secondary address. This allows two con- 
trollers in the same Host system. However, second- 
ary ports on the WD1002-WAH are not supported by 
any version of DOS. 

Table 5 summarizes the WD1002-WAH I/O port 
address map. Figure 3 summarizes the WD1010A-05 
task file registers and bit assignments. Figure 4 sum- 
marizes the other three I/O registers and bit 
assignments for the WD1002-WAH. Bit assignments 



are with respect to the Host lower byte bus terms, 
SD7 through SDO. The fixed size/drive/head (SDH) and 
status registers in the WD1010A-05 desciptions 
slightly differ from the standard descriptions in the 
WD1010-05 data sheet. Please note that the SDH 
register is set for the ECC option mode and 512 bytes 
per track. The SDH register also limits the number 
of heads to 16. Bit 2 of the WD1010A-05 status register 
is designated as the Corrected Data bit. Assertion 
(setting to 1) of this bit indicates the sector read from 
the drive resulted in a correctable ECC error. Soft 
errors do not end multiple sector transfers. Bit 1 of 
the WD1010A-05 status register is designated as the 
Index bit. Assertion of this bit occurs each revolution 
of the currently selected drive. Refer to the WD1010-05 
data sheet for a complete description of all other 
WD1010A-05 bit assignments. Table 6 describes the 
bit assignments for the other WD1002-WAH control 
and status registers. 

NOTE 

Where differences exist, the values and descriptions 
for Figure 3 take precedence over the WD1010-05 data 
sheet. 



TABLE 5. WD1002-WAH REGISTER ADDRESS MAP 



I/O ADDRESS 


READ 


WRITE 


PRIMARY 


SECONDARY 


WD1010A-05 TASK FILE REGISTERS 


1F1 


171 


ERROR REGISTER 


WRITE PRE-COMP 


1F2 


172 


SECTOR COUNT 


SECTOR COUNT 


1F3 


173 


SECTOR NUMBER 


SECTOR NUMBER 


1F4 


174 


CYLINDER NUMBER 


CYLINDER NUMBER 






(low byte) 


(low byte) 


1F5 


175 


CYLINDER NUMBER 


CYLINDER NUMBER 






(high byte) 


(high byte) 


1F6 


176 


SDH REGISTER 


SDH REGISTER 


1F7 


177 


STATUS REGISTER 


COMMAND REGISTER 




CONTROL AND ST 


ATUS REGISTERS EXTERNAL TO Th 


^E WD1010A-05 


1F0 


170 


DATA REGISTER 


DATA REGISTER 






(16 bits) 


(16 bits) 


3F6 


376 




FIXED DISK REGISTER 


3F6 


376 


ALTERNATE STATUS 
REGISTER 




3F7 


377 


DIGITAL INPUT 
REGISTER 





6-726 



Winchester Board Products 



REGISTER 


7 


6 


5 


4 


3 


2 


1 





WRITE PRE-COMP 


CYLINDER NUMBER DIVIDED BY 4 


ERROR 


BB 


ECC 





ID 





AC 


TK 


DM 


SECTOR COUNT 


NUMBER OF SECTORS 


SECTOR NUMBER 


SECTOR NUMBER 


CYLINDER NO. 


CYLINDER NUMBER (LOW BYTE 


) 


CYLINDER NO. 




















CYL. NO. MSB 


SDH 


1 





1 


DS 


HS3 


HS2 


HSl 


HSO 


COMMAND 


COMMAND 


STATUS 


BSY 


RDY 


WF 


SC 


DRQ 


CRD 


IDX 


ERR 



FIGURE 3. WD1010A-05 TASK RLE REGISTER BIT ASSIGNMENT 



REGISTER 


7 


6 


5 


4 


3 


2 


1 





ALTERNATE STATUS 


BSY 


RDY 


WF 


SC 


DRQ 


CRD 


IDX 


ERR 


DIGITAL INPUT 


X 


WTG 


HS3/ 
RWC 


HS2 


HSl 


HSO 


DS2 


DS1 


FIXED DISK 














HS3EN 


RST 


lEN 






FIGURE 4. WD1002-WAH CONTROL AND STATUS REGISTERS 



TABLE 6. 


WD1002-WAH CONTROL AND STATUS REGISTER BIT DEFINITIONS 


REGISTER 


BIT MNEMONIC 


BIT NAME 


ALTERNATE STATUS 


BSY 


Controller Busy Flag 




RDY 


Ready from selected drive 




WFT 


Write Fault from selected drive 




SKC 


Seek Complete from selected drive 




DRQ 


Data Transfer Request Flag 




CRD 


Corrected Data Flag from WD1015-03 




IDX 


Index pulse from selected drive 




ERR 


Error Flag from WD1015-03 


DIGITAL INPUT 


X 


Reserved. System bus signal SD07 tri-stated 




WTG 


Write Gate on 




HS3 (RWC) 


Drive head select or RWC (bit 5) for drives using 




throuah HSO 


RWC 




DS2, DS1 


Drive select 


FIXED DISK 


HS3EN 


Set to 1: Enables HS3 
Set to 0: Enables RWC 




RST 


Reset. Program controlled reset to board. This bit 
maintains the WD1002-WAH logic reset as long as this 
is on. This bit must be on for a. minimum of 5.0 fisec. 
After the bit is on for the minimum time, the bit must 






be turned off to complete reset function. 




lEN 


Interrupt Enable. Enables or disables IRQ14. This bit 
does not clear the interrupt level in the disabled state. 
A pending interrupt would occur when the interrupt is 
enabled again. A system master reset clears the inter- 
rupt but leaves the interrupt enabled. 



Winchester Board Products 



6-127 



o 

o 
o 



COMMANDS 

The WD1002-WAH command set contains eight com- 
mands. Five commands (Restore, Seel<, Read Sector, 
Write Sector, and Format Track) are executed through 
the WD1010A-05 command register. (A sixth 
WD1010A-05 command, Scan ID is not directly 
available to the Host. Scan ID may be executed by 
the WD1015-03 transparently to the Host.) The three 
remaining commands (Read Verify, Diagnose, and Set 
Parameters) are executed through the WD1015-03. 



Table 7 describes the eight WD1002-WAH commands 
and their bit assignments. The next section describes 
a typical command sequence. Each command is 
described following the command sequence. 



TABLE 7. COMMANDS AND COMMAND CODES 



COMMAND 


BITS 


Restore 













R3 


R2 


R1 


RO 


Seek 





1 


1 




R3 


R2 


R1 


RO 


Read Sector 








1 











L 


T 


Write Sector 








1 










L 


T 


Format Track 





1 



















Read Verify 





1 

















T 


Diagnose 


1 






















Set Parameters 


1 



















1 



LEGEND 

R3 through RO 



Step rate selection bits. Refer to 
Table 8 for more detailed 
information. 

Read or Write Long bit. Set to 1 
enables Read or Write Long 
mode. 

Retry bit. Set to 1 disables retries. 



The stepping rates for the commands that perform 
implied seeks are set in the least significant nibble 
of the last executed RESTORE or SEEK command. 
The stepping rate is given in Table 8. 



6-128 



Winchester Board Products 



TABLE 8. STEPPING RATE 











STEPPING 












STEPPING 


R3 


R2 


R1 


RO 


RATE 




R3 


R2 


R1 


RO 


RATE 














35 /isec 















4.0 msec 











1 


0.5 msec 












1 


4.5 msec 








1 





1.0 msec 









1 





5.0 msec 








1 


1 


1.5 msec 









1 


1 


5.5 msec 





1 








2.0 msec 






1 








6.0 msec 





1 





1 


2.5 msec 






1 





1 


6.5 msec 





1 


1 





3.0 msec 






1 


1 





7.0 msec 





1 


1 


1 


3.5 msec 






1 


1 


1 


7.5 msec 






Note: After Diagnose or reset, 


stepping rate defaults to 7.5 msec 





o 

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COMMAND SEQUENCE DESCRIPTION 

Tfiis section describes a typicai command execution 
sequence. This description illustrates the relationship 
beween Host and the major components of the 
WD1002-WAH during command execution. 

In the idle state: the WD1010A-05 drive control 
signals are off. The controller status indicates 
ready. Drive status is valid. Controller Interrupt is 
enabled but not asserted. The WD1015-03 is idle 
and is monitoring the WAKEUP signal input. 

The Host outputs the command parameters to the 
WD1010A-05 task file, the operation command 
(Seek, Read or Write) and the command attributes 
(Long mode, retry control, etc.). For write opera- 
tions, the Host also outputs the sector or format 
data. 

The command byte is intercepted by the 
WD1014-01 and is held for later interpretation by 
the WD1015-03. 

A Read command output sets the module Wakeup 
latch that causes the controller status to indicate 
Busy and the WD1015-03 WAKEUP signal to be 
asserted. Write and Format commands first set 
the data request status signal DRQ. This initiates 
the Host data transfer. Completion of the data 
transfer (512 or 516 bytes) sets the WD1015-03 
WAKEUP signal and Busy status. 

The WD1015-03 examines the command, verifies 
command parameters, and passes the command 
to the WD1010A-05 for execution. 

The WD1010A-05 executes the command providing 
drive positioning, data transfer control, error 



monitoring and completion status. The WD10C20 
provides drive read and write data control for com- 
mands that require data transfers. 

On command completion, the WD1010A-05 inter- 
rupts the WD1015-03. The WD1015-03 examines 
the command, status, etc. for any additional 
requirements. If completion is indicated, the 
WD1015-03 sets the controller status to indicate 
ready and interrupts the Host. 

The WD1002-WAH returns to the idle state and the 
Host may examine drive and controller status, read 
input data, etc., as required to complete the 
operation. 

COMMAND DESCRIPTION 

Restore 

The Restore command is used to move the RA/V 
heads to the Track 000 position. The controller issues 
step pulses to the drive until the Track 000 indicator 
from the drive is asserted. If Track 000 is not asserted 
within 1023 steps, the Error bit in the Status Register 
is set and a Track 000 error is posted in the Error 
Register. The implied seek step rate may be set up 
according to Table 8 by the Restore command. The 
restore step rate is established by the seek complete 
signal from the drive, i.e., each step pulse is issued 
only after seek complete i s asserted by th e drive from 
the previous st ep. If the DRIV E READY signal is 
de-asserted or WRITE FAULT is asserted, this com- 
mand terminates with the error bit set In the status 
register and the error register reports an aborted 
command. 



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Seek 

This command moves the RA/V heads to the cylinder 
specified in the tasl< fiie cylinder specified in the task 
file cylinder high and low registers. The implied seek 
step rate is also set by this command. The lower order 
four bits of the command are used to select one of 
16 available step rates. An interrupt I s generated at 
the completion of the co mmand. If the D RIVE READY 
signal is de-asserted or WRITE FAULT is asserted, 
this command is terminated with the error bit set in 
the status register and the error register reports an 
aborted command. 

Read Sector 

A number of sectors (1 - 256) can be read from the 
selected drive with this command. The sector count 
register in the task file determines the number of sec- 
tors to be transferred. Multiple sector reads may cross 
head and cylinder boundaries. 

If the Read command is issued prior to initializing a 
step rate, the default value of 7.5 msec is selected 
and a Recalibrate is performed prior to the Read. 

If the RAA/ heads are not positioned over the target 
track, the controller performs an implied seek to the 
proper cylinder. The stepping rate used during the 
implied seek is the value specified during the previous 
Seek or Restore command. 

The optional long bit (L set to 1 enables Read Long.) 
informs the WD1002-WAH whether or not to include 
the four ECC bytes. These four ECC bytes are 
transferred as individual bytes, not words, as is the 
data field information. The data request bit in the 
status register must be valid before each byte 
transferred and at least 2 ^isec will pass between each 
byte transferred. 

Data errors up to 5 bits in length will be automatically 
corrected on normal Read commands. If an uncor- 
rectable error occurs, the data transfer will still take 
place, a multi- sector read, however, will terminate 
after the sector in error is read by the system. 

The optional retry bit (T set to 1 disables retries.) 
disables or enables retries. The WD1010A-05 
automatically retries for ten disk revolutions when the 
retry bit is enabled. The WD1010A-05 properly sets the 
error and status registers if the retries are unsuc- 
cessful. Disabling retries allows only two disk revolu- 
tions before the WD1010A-05 sets the error and status 
registers. 

For ECC errors, eight retries are made at reading 
before a soft uncorrectable error is reported. A retry 
results in the reissuing of the WD1010A-05 Read Sec- 
tor command. The WD1010A-05 Read Sector com- 
mand attempts to verify the sector ten times, if T is 
set to 1, before returning an error. ECC correctable 



data errors are corrected after two consecutive mat- 
ching ECC syndromes are detected. If the error is an 
uncorrectable error or an error is reported by the 
WD1010A-05, the command terminates. 

Interrupts occur as each sector is ready to be read 
by the system. No interr upt is generate d at the end 
of the com mand. If the DR IVE READY signal is de- 
asserted or WRITE FAULT asserted, this command 
terminates with the error bit set in the status register 
and the error register reports an aborted command. 

Write Sector 

A number of sectors (1 - 256) can be written to the 
selected drive. The sector count register in the task 
file determines the number of sectors to be transfer- 
red. Multiple sector writes may cross head and 
cylinder boundaries. 

If the Write command is issued prior to initializing a 
step rate, the default value of 7.5 msec is selected 
and a Recalibrate is performed prior to the Write. 

If the heads are not positioned at the cylinder 
specified in the cylinder high and low registers, the 
controller performs an implied seek. The step rate 
used is determined by the step rate field of the most 
recently executed Restore or Seek command. 

The optional long bit (L set to 1 enables Write Long.) 
informs the WD1002-WAH whether or not to append 
the Host supplied ECC bytes. These four bytes are 
transferred as individual bytes, not words, as is data 
field information. The data request bit in the status 
register must be valid before each byte transferred 
and at least 2 /^sec will pass between each byte 
transferred. 

The optional retry bit (Tset to 1 disables retries.) 
disables or enables retries. The WD1010A-05 
automatically retries for ten disk revolutions when the 
retry bit is enabled. The WD1010A-05 properly sets the 
error and status registers if the retries are unsuc- 
cessful. Disabling retries allows only two disk revolu- 
tions before the WD1010A-05 sets the error and status 
registers. 

The WD1002-WAH interrupt is generated as the data 
for each sector is required to be transferred into the 
Sector Buffer (except the first sector) and at the end 
of the command. The first sector may be written to 
the buffer immediately after the command ha s been 
sent, an d the data request status is set. If the DR IVE 
READY signal is de-asserted or WRITE FAULT is 
asserted, this command terminates with the error bit 
set in the status register and the error register reports 
an aborted command. 



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Format Track 

The track specified by tlie task file is formatted with 
ID and data fields according to the interleave table 
transferred to the buffer. The interleave table, consists 
of tvjo bytes per sector as follows: 

00 PHYSICAL SECTOR 1 
00 PHYSICAL SECTOR 2 
00 PHYSICAL SECTOR 3 



00 PHYSICAL SECTOR 17 

The data transfer must be 512 bytes even though the 
table may be only 34 bytes. The sector count register 
must be loaded with the number of sectors per track 
before each Format Track command. The Format 
Track command supports on error reporting. A bad 
block may be specified by replacing a 00 table entry 
with and 80 Hex. When switching between drives, a 
Restore command must be executed prior to attemp- 
ting a format. Command completion will leave all data 
fields initialized to zeroes. The completion interrupt 
is generated after each track has been formatted. 

Read Verify 

This command funtions similarly to a normal Read 
command except that data is not output to the Host. 
One of 256 sectors may be verified at one time. The 
generated ECC bytes are compared with the recorded 
ECC bytes for data verification. A single interrupt is 
generated upon completion of the command or in the 
event of an error. 

If the Read Verify command is issued prior to initializ- 
ing a step rate, the default value of 7.5 msec is 
selected and a recalibrate is performed prior to the 
Read Verify. 

For ECC errors, eight retries are made at reading 
before a soft uncorrectable error is reported. 

A retry results in the reissuing of the WD1010A-05 
Read Sector command. The WD1010A-05 Read Sec- 
tor command attempts to verify the sector ten times, 
if T is set to 1, before returning an error. ECC correc- 
table data errors are corrected after two consecutive 
matching ECC syndromes are detected. If the error 
is an uncorrectable error or an error is reported by 
the WD1010A- 05, t he command terminates. The 
WRITE FAULT and DRIVE READY inputs are check- 
ed throughout the command's execution. 

Diagnose 

The Diagnose command causes the Controller to per- 
form an onboard diagnostic and to report the result 
in the Error Register. An interrupt is performed upon 
completion of the command. 



The Diagnose command performs tests on the 
WD101&O3's internal ROM and RAM, the WD1014-01, 
WD1010A-05, and the Sector Buffer. If any component 
fails, the appropriate error code is loaded into the error 
register. Error codes are as follows: 

01 No errors 

02 WD1010A-05 register access error 

03 Sector Buffer RAM data error 

04 WD1014-01 register access error 

05 WD1015-03 ROM checksum or 
RAM data error 

00,06-FF Not used. Undefined. 

In addition, the Diagnose command sets the write pre- 
comp task file register to 32. This causes write pre- 
compensation to begin at cylinder 128. (Since the 
write pre-comp register holds the desired value 
divided by four.) The sector count register is reset to 
one while the cylinder high, cylinder low, and SDH 
registers are all set to zero. 

Set Parameters 

This command sets up the drive parameters regar- 
ding the maximum number of heads and sectors per 
track. The WD1002- WAH uses these two paramenters 
when perfonning multiple sector operations. The SDH 
task file register specifies the drive affected. The sec- 
tor count and SDH registers must be set up before 
this command is issued. An interrupt is set at the 
completion of the command. 

This command must be issued before any multiple 
sector operations are undertaken. By setting the SDH 
register for each of the two possible drives, this com- 
mand allows the WD1002-WAH to support two drives 
with different characteristics. 

JUMPER OPTIONS 

The WD1002-WAH does not provide configuration 
switches for drive parameters, interrupt selection, or 
drive selection. The attached drive or drives must be 
configured for drive select 1 or 2. The available jumper 
options are as follows: 

W 1 : Primary and secondary I/O address jumper 
allows two controllers in one chassis. 
Jumpering positions 1-2 selects base 
primary address 1F0. Jumpering positions 
2-3 selects base secondary address 170. 

W2: LATCHED status register jumper. L = lat- 
ched. In this mode, the WD1002-WAH 
diagnostics registers located at 1/0 address 
BASE + 7, 3F6 Hex, and 3F7 Hex present 
latched status to the Host. This mode is 
IBM PC AT compatible. Drive select line is 
semi-static. 



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NON-LATCHED NL = non-latched. This has 
centain timing implications for the disk drives. 
DRIVE SELECT low to status valid is 355 nsec as 
measured at the drive interface. The drive select 



lines are activated only when the controller is 
executing a command, or reading status at 3F6 
or 3F7 Hex. 

Figure 5 illustrates the location of W1 and W2. 




FIGURE 5. WD1002-WAH JUMPER LOCATIONS 



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SPECIFICATIONS 

PHYSICAL 

Form factor 

Length 

Width 

Height (maximum including 

board, components, and leads) 

POWER AND ENVIRONMENT 

Power 

+ 5V ± 5% 

+ 12V ± 10% 



IBM PC 

20.6 centimeters (8.1 inches) 

10.7 centimeters (4.2 inches) 
1.27 centimeters (0.05 inches) 



Current 

1.5A 

0.5mA 



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ENVIRONMENTAL 

Temperature 
Operating 
Non-operating 

Humidity 
Operating 
Non-operating 

Shock and Vibration 
Shock 
Vibration 

Altitude 
Operating 
Non-operating 



0°C (32°F) to 55°C (131°F) 
-40°C (-40°F) to 60°C (140°F) 

8% to 85% non-condensing 
5% to 95% non-condensing 

35G/20MS square wave maximum 

1G/0-600 Hz, dwell not to exceed 30 seconds at any resonance 

to 3000 meters maximum (10,000 Ft) 
to 5000 meters maximum (15,000 Ft) 



RECORDING SPECIFICATIONS 

Encoding method 
Data rate 
Sector format 



Interleave 
Drives supported 
Heads supported 
Tracks supported 
Hard error rate 
Soft error rate 
Seek error rate 



MFM 

5.0Mbs 

512 bytes/sector 

17 sectors/track (sectors number 01 through 17) 

track soft sectored format 

2:1 

2 maximum 

16 maximum 

1024 maximum 

less than 1 per 10(E12) bits read 

less than 1 per lO(EIO) bits read 

less than 1 per 10(E06) seeks 



READ/WRITE CONTROL SPECIFICATIONS 

Maximum acquisition time 
Capture range 
Drive Margin 
Asymmetry tolerance 



12.8 us @ 5.0Mbs 

> ± 2.2% 

± 16 ns (with pre-comp off) 

30nsec 



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ERROR CORRECTION SPECIFICATIONS 



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Method 


Polynomial division 




Degree 


32 




Forward polynomial 


X17 + X1° + X06 + X02 + 1 




Reciprocal polynomial 


X32 + X30 + X26 + X22 + 

X15 + X13 + X06 + X°^ + 1 




Record length (r) 


516 by 8 bits maximum 




Correction span (b) 


5 bits 




Single burst detection span 


r = 516 by 8 bits 




with b = 


32 bits 




with b = 5 


19 bits 




Single burst detection span 


r = 516 by 8 bits 




with b = 


> 3 bits 




with b = 5 


3 bits 




Non-detection probability 


2.3 (E-10), r = 516 by 8, b = 


: 5 


Miscorrection probability 


1.57 (E-5), r = 516 by 8, b = 


z 5 



TIMING 

Timing diagrams are shown in Figures 6 through 
8, and the timing values are given in Table 9. 



FAST I/O 16 



SA1-SA9 



SAO 



lOR.IOW 



FIGURE 6. I/O CHANNEL TIMING 



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SD00-SD15 
(DATA REGISTER) 




-V 




DATA VALID 




V READ 
> DATA 


SD0-SD7 




DATA VALID 









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FIGURE 7. DATA REGISTER READ DATA I/O TIMING 



SD00-SD15 
(DATA REGISTER) 




•N 




DATA VALID 


. WRITE 
r DATA 


SD0-SD7 




DATA VALID 









FIGURE 8. DATA REGISTER WRITE DATA I/O TIMING 



TABLE 9. TIMING 



DEFINITION 


I/O 


16 BIT 


8 BIT 


SA1-SA9 -> Fast I/O 16 


93 nsec max 


N/A 


SAO -> Fast I/O 16 


73 nsec max 


N/A 


SA1-SA9 -> lOR/lOW 


97 nsec min 


97 nsec min 


SAO-> lOR/lOW 


77 nsec min 


77 nsec min 


lOR/lOW Pulse Width 


167 nsec min 


542 nsec min 


lOR/lOW -> Fast I/O 16 


93 nsec max 


N/A 


lOR -> Data Valid 


132 nsec max 


498 nsec max 


Data Valid -> l/OW 


71 nsec min 


491 nsec min 


Data Hold from lOW 


54 nsec min 


46 nsec min 


Addr Hold from lOR/IOR 


47 nsec min 


47 nsec min 


lOR/lOW -> lOR/lOW 


375 nsec min 


375 nsec min 



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6-136 Winchester Board Products 



WESTERN DIGITAL 

CORPORATION 

WD1002-WA2 Winchester/Floppy Disk Controller 



FEATURES 

• AT COMPATIBLE WINCHESTER AND FLOPPY 
CONTROLLER 

• CONTROLS UP TO TWO WINCHESTER DRIVES 
(ST506/ST412, 16 R/W HEADS EACH) 

• CONTROLS UP TO TWO FLOPPY DISK DRIVES 

DOUBLE-SIDED 

DOUBLE DENSITY (360kB, 250kbs, MFM) 

QUAD DENSITY (1.2MB, 500kbs, MFM) 

FOUR DATA RATES {500kbs, SOOkbs, 250kbs, 

and 125kbs) 

SUPPORTS 360 AND 300 RPM SPINDLE 

SPEEDS 

BASED ON INDUSTRY STANDARD WD1010A-05 
WINCHESTER DISK CONTROLLER 

8-BIT, BI-DIRECTIONAL BUS HOST INTERFACE 
FOR CONTROL AND STATUS TRANSFERS 

HIGH-SPEED, 16-BIT PIO DATA TRANSFERS 

32-BIT ECC FOR WINCHESTER ERROR DETEC- 
TION AND CORRECTION, CRC FOR ID FIELDS 

DIAGNOSTIC MODE FOR ERROR CHECKING 

WRITE PRECOMPENSATION LOGIC 

SINGLE CHIP WINCHESTER DATA SEPARATOR 
(WD10C20) 

ALLOWS CONCURRENT OPERATION OF ONE 
FLOPPY AND ONE WINCHESTER DRIVE 

DESCRIPTION 

The WD1002-WA2 is an AT bus compatible Win- 
chester/Floppy disk controller designed to interface 
up to two Winchester and up to two floppy disk drives. 
The board permits the concurrent operation of one 
floppy and one fixed disk drive. The Winchester drive 
interface is compatible to the Seagate Technology 
ST506 standard interface for 5Mbs hard disk drives. 
The floppy disk drive interface supports 1.2MB, 360 
RPM drives as well as 360kB (SA450) drives. The 
WD1002-WA2 includes all necessary receivers and 
drivers to allow direct connection to the drive(s). 

ARCHITECTURE 

The WD1002-WA2 is based on the WD1014-01 Error 
Detection/Support Logic device, WD1015-03 Buffer 
Manager Control Processor, WD1010A-05 Winchester 
Disk Controller, WD2293-07 Floppy Data Separator 



Control Device, WD2293-08 Floppy Clock and Support 
Device, and WD10C20 Winchester Data Separator and 
Write Precompensation Device. The WD1002-WA2 
also uses two 2K x 8 static RAM devices as a 16-bit 
wide Sector Buffer, an analog data separator with 
dual VCOs for four floppy data rates, and an NEC 
fiPD765A Floppy Disk Controller. 

The WD1014-01 provides error correction for the 
WD1002-WA2's Winchester control circuitry. The 
WD1014-01 generates four ECC bytes and appends 
these bytes to the sector data field. The maximum 
error correction span is 5-bits. The WD1014-01 also 
selects the proper drive and head. 

The WD1015-03 is an 8 bit microprocessor that con- 
trols and coordinates the activity of the Winchester 
disk drives, WD1010A-05, and WD1014-01. The 
WD1015-03 receives and sends commands or status 
Information over the internal WD1002-WA2 
multiplexed address/data bus, HDO through HD7. 
Controlling firmware resides in the WD1015-03's 2K 
Internal ROM. 

The WD1010A-05 controls all data transfers between 
the Sector Buffer and the drives. The WD1010A-05 per- 
forms multiple sector Read/Write, Implied and Buf- 
fered Seek commands. The WD1010A-05 also 
executes programmable format and error recovery 
algorithms. All Winchester commands are executed 
through the seven Task Files of the WD1010A-05 after 
limited inten/ention by the WD1015^ and WD1014-01. 

The Sector Buffer is two 2KB x 8 RAMS. Since the 
WD1010A-05, WD1014-01, and WD1015-03 are 8-bit 
devices, two RAMs are used because the Host pro- 
vides data in 16-bit words. An on board PAL selects 
the proper RAM. The Sector Buffer RAMs never con- 
tain more than 512 bytes. 

The WD10C20 performs phase-locked loop data syn- 
chronization on read data from the Winchester drives. 
This device also conditions write data to be recorded 
on the disk. The WD10C20 includes both frequency 
and phase detection. Zero phase error start-up cir- 
cuitry eliminates problems due to asymmetry. The 
WD10C20 requires no adjustments and contains all 
data separation circuitry in a single device. 

The NEC fiPD765A is a fl